2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
28 enum si_blitter_op
/* bitmask */
31 SI_SAVE_FRAMEBUFFER
= 2,
32 SI_SAVE_FRAGMENT_STATE
= 4,
33 SI_DISABLE_RENDER_COND
= 8,
35 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
37 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
39 SI_COPY
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
40 SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
42 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
43 SI_SAVE_FRAGMENT_STATE
,
45 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
|
46 SI_DISABLE_RENDER_COND
,
48 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
51 static void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
)
53 struct si_context
*sctx
= (struct si_context
*)ctx
;
55 util_blitter_save_vertex_buffer_slot(sctx
->blitter
, sctx
->vertex_buffer
);
56 util_blitter_save_vertex_elements(sctx
->blitter
, sctx
->vertex_elements
);
57 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
58 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
59 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
60 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
61 util_blitter_save_so_targets(sctx
->blitter
, sctx
->b
.streamout
.num_targets
,
62 (struct pipe_stream_output_target
**)sctx
->b
.streamout
.targets
);
63 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
65 if (op
& SI_SAVE_FRAGMENT_STATE
) {
66 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
67 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
68 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
69 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
70 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
.sample_mask
);
71 util_blitter_save_viewport(sctx
->blitter
, &sctx
->b
.viewports
.states
[0]);
72 util_blitter_save_scissor(sctx
->blitter
, &sctx
->b
.scissors
.states
[0]);
75 if (op
& SI_SAVE_FRAMEBUFFER
)
76 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
78 if (op
& SI_SAVE_TEXTURES
) {
79 util_blitter_save_fragment_sampler_states(
81 (void**)sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.sampler_states
);
83 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
84 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.views
);
87 if (op
& SI_DISABLE_RENDER_COND
)
88 sctx
->b
.render_cond_force_off
= true;
91 static void si_blitter_end(struct pipe_context
*ctx
)
93 struct si_context
*sctx
= (struct si_context
*)ctx
;
95 sctx
->b
.render_cond_force_off
= false;
98 static unsigned u_max_sample(struct pipe_resource
*r
)
100 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
104 si_blit_dbcb_copy(struct si_context
*sctx
,
105 struct r600_texture
*src
,
106 struct r600_texture
*dst
,
107 unsigned planes
, unsigned level_mask
,
108 unsigned first_layer
, unsigned last_layer
,
109 unsigned first_sample
, unsigned last_sample
)
111 struct pipe_surface surf_tmpl
= {{0}};
112 unsigned layer
, sample
, checked_last_layer
, max_layer
;
113 unsigned fully_copied_levels
= 0;
115 if (planes
& PIPE_MASK_Z
)
116 sctx
->dbcb_depth_copy_enabled
= true;
117 if (planes
& PIPE_MASK_S
)
118 sctx
->dbcb_stencil_copy_enabled
= true;
119 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
121 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
124 unsigned level
= u_bit_scan(&level_mask
);
126 /* The smaller the mipmap level, the less layers there are
127 * as far as 3D textures are concerned. */
128 max_layer
= util_max_layer(&src
->resource
.b
.b
, level
);
129 checked_last_layer
= MIN2(last_layer
, max_layer
);
131 surf_tmpl
.u
.tex
.level
= level
;
133 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
134 struct pipe_surface
*zsurf
, *cbsurf
;
136 surf_tmpl
.format
= src
->resource
.b
.b
.format
;
137 surf_tmpl
.u
.tex
.first_layer
= layer
;
138 surf_tmpl
.u
.tex
.last_layer
= layer
;
140 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &src
->resource
.b
.b
, &surf_tmpl
);
142 surf_tmpl
.format
= dst
->resource
.b
.b
.format
;
143 cbsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &dst
->resource
.b
.b
, &surf_tmpl
);
145 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
146 if (sample
!= sctx
->dbcb_copy_sample
) {
147 sctx
->dbcb_copy_sample
= sample
;
148 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
151 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
152 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
153 sctx
->custom_dsa_flush
, 1.0f
);
154 si_blitter_end(&sctx
->b
.b
);
157 pipe_surface_reference(&zsurf
, NULL
);
158 pipe_surface_reference(&cbsurf
, NULL
);
161 if (first_layer
== 0 && last_layer
>= max_layer
&&
162 first_sample
== 0 && last_sample
>= u_max_sample(&src
->resource
.b
.b
))
163 fully_copied_levels
|= 1u << level
;
166 sctx
->dbcb_depth_copy_enabled
= false;
167 sctx
->dbcb_stencil_copy_enabled
= false;
168 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
170 return fully_copied_levels
;
173 static void si_blit_decompress_depth(struct pipe_context
*ctx
,
174 struct r600_texture
*texture
,
175 struct r600_texture
*staging
,
176 unsigned first_level
, unsigned last_level
,
177 unsigned first_layer
, unsigned last_layer
,
178 unsigned first_sample
, unsigned last_sample
)
180 const struct util_format_description
*desc
;
183 assert(staging
!= NULL
&& "use si_blit_decompress_zs_in_place instead");
185 desc
= util_format_description(staging
->resource
.b
.b
.format
);
187 if (util_format_has_depth(desc
))
188 planes
|= PIPE_MASK_Z
;
189 if (util_format_has_stencil(desc
))
190 planes
|= PIPE_MASK_S
;
193 (struct si_context
*)ctx
, texture
, staging
, planes
,
194 u_bit_consecutive(first_level
, last_level
- first_level
+ 1),
195 first_layer
, last_layer
, first_sample
, last_sample
);
198 /* Helper function for si_blit_decompress_zs_in_place.
201 si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
202 struct r600_texture
*texture
,
203 unsigned planes
, unsigned level_mask
,
204 unsigned first_layer
, unsigned last_layer
)
206 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
207 unsigned layer
, max_layer
, checked_last_layer
;
208 unsigned fully_decompressed_mask
= 0;
213 if (planes
& PIPE_MASK_S
)
214 sctx
->db_flush_stencil_inplace
= true;
215 if (planes
& PIPE_MASK_Z
)
216 sctx
->db_flush_depth_inplace
= true;
217 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
219 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
222 unsigned level
= u_bit_scan(&level_mask
);
224 surf_tmpl
.u
.tex
.level
= level
;
226 /* The smaller the mipmap level, the less layers there are
227 * as far as 3D textures are concerned. */
228 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
229 checked_last_layer
= MIN2(last_layer
, max_layer
);
231 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
232 surf_tmpl
.u
.tex
.first_layer
= layer
;
233 surf_tmpl
.u
.tex
.last_layer
= layer
;
235 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &texture
->resource
.b
.b
, &surf_tmpl
);
237 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
238 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0,
239 sctx
->custom_dsa_flush
,
241 si_blitter_end(&sctx
->b
.b
);
243 pipe_surface_reference(&zsurf
, NULL
);
246 /* The texture will always be dirty if some layers aren't flushed.
247 * I don't think this case occurs often though. */
248 if (first_layer
== 0 && last_layer
>= max_layer
) {
249 fully_decompressed_mask
|= 1u << level
;
253 if (planes
& PIPE_MASK_Z
)
254 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
255 if (planes
& PIPE_MASK_S
)
256 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
258 sctx
->db_flush_depth_inplace
= false;
259 sctx
->db_flush_stencil_inplace
= false;
260 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
263 /* Helper function of si_flush_depth_texture: decompress the given levels
264 * of Z and/or S planes in place.
267 si_blit_decompress_zs_in_place(struct si_context
*sctx
,
268 struct r600_texture
*texture
,
269 unsigned levels_z
, unsigned levels_s
,
270 unsigned first_layer
, unsigned last_layer
)
272 unsigned both
= levels_z
& levels_s
;
274 /* First, do combined Z & S decompresses for levels that need it. */
276 si_blit_decompress_zs_planes_in_place(
277 sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
,
279 first_layer
, last_layer
);
284 /* Now do separate Z and S decompresses. */
286 si_blit_decompress_zs_planes_in_place(
287 sctx
, texture
, PIPE_MASK_Z
,
289 first_layer
, last_layer
);
293 si_blit_decompress_zs_planes_in_place(
294 sctx
, texture
, PIPE_MASK_S
,
296 first_layer
, last_layer
);
301 si_flush_depth_texture(struct si_context
*sctx
,
302 struct r600_texture
*tex
,
303 unsigned required_planes
,
304 unsigned first_level
, unsigned last_level
,
305 unsigned first_layer
, unsigned last_layer
)
307 unsigned inplace_planes
= 0;
308 unsigned copy_planes
= 0;
309 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
310 unsigned levels_z
= 0;
311 unsigned levels_s
= 0;
313 if (required_planes
& PIPE_MASK_Z
) {
314 levels_z
= level_mask
& tex
->dirty_level_mask
;
317 if (r600_can_sample_zs(tex
, false))
318 inplace_planes
|= PIPE_MASK_Z
;
320 copy_planes
|= PIPE_MASK_Z
;
323 if (required_planes
& PIPE_MASK_S
) {
324 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
327 if (r600_can_sample_zs(tex
, true))
328 inplace_planes
|= PIPE_MASK_S
;
330 copy_planes
|= PIPE_MASK_S
;
334 assert(!tex
->tc_compatible_htile
|| levels_z
== 0);
336 /* We may have to allocate the flushed texture here when called from
337 * si_decompress_subresource.
340 (tex
->flushed_depth_texture
||
341 r600_init_flushed_depth_texture(&sctx
->b
.b
, &tex
->resource
.b
.b
, NULL
))) {
342 struct r600_texture
*dst
= tex
->flushed_depth_texture
;
343 unsigned fully_copied_levels
;
346 assert(tex
->flushed_depth_texture
);
348 if (util_format_is_depth_and_stencil(dst
->resource
.b
.b
.format
))
349 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
351 if (copy_planes
& PIPE_MASK_Z
) {
355 if (copy_planes
& PIPE_MASK_S
) {
360 fully_copied_levels
= si_blit_dbcb_copy(
361 sctx
, tex
, dst
, copy_planes
, levels
,
362 first_layer
, last_layer
,
363 0, u_max_sample(&tex
->resource
.b
.b
));
365 if (copy_planes
& PIPE_MASK_Z
)
366 tex
->dirty_level_mask
&= ~fully_copied_levels
;
367 if (copy_planes
& PIPE_MASK_S
)
368 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
371 if (inplace_planes
) {
372 si_blit_decompress_zs_in_place(
375 first_layer
, last_layer
);
380 si_flush_depth_textures(struct si_context
*sctx
,
381 struct si_textures_info
*textures
)
384 unsigned mask
= textures
->depth_texture_mask
;
387 struct pipe_sampler_view
*view
;
388 struct si_sampler_view
*sview
;
389 struct r600_texture
*tex
;
391 i
= u_bit_scan(&mask
);
393 view
= textures
->views
.views
[i
];
395 sview
= (struct si_sampler_view
*)view
;
397 tex
= (struct r600_texture
*)view
->texture
;
398 assert(tex
->db_compatible
);
400 si_flush_depth_texture(
402 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
403 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
404 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
408 static void si_blit_decompress_color(struct pipe_context
*ctx
,
409 struct r600_texture
*rtex
,
410 unsigned first_level
, unsigned last_level
,
411 unsigned first_layer
, unsigned last_layer
,
412 bool need_dcc_decompress
)
414 struct si_context
*sctx
= (struct si_context
*)ctx
;
416 unsigned layer
, checked_last_layer
, max_layer
;
417 unsigned level_mask
=
418 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
420 if (!need_dcc_decompress
)
421 level_mask
&= rtex
->dirty_level_mask
;
425 if (rtex
->dcc_offset
&& need_dcc_decompress
) {
426 custom_blend
= sctx
->custom_blend_dcc_decompress
;
428 /* disable levels without DCC */
429 for (int i
= first_level
; i
<= last_level
; i
++) {
430 if (!vi_dcc_enabled(rtex
, i
))
431 level_mask
&= ~(1 << i
);
433 } else if (rtex
->fmask
.size
) {
434 custom_blend
= sctx
->custom_blend_decompress
;
436 custom_blend
= sctx
->custom_blend_fastclear
;
440 unsigned level
= u_bit_scan(&level_mask
);
442 /* The smaller the mipmap level, the less layers there are
443 * as far as 3D textures are concerned. */
444 max_layer
= util_max_layer(&rtex
->resource
.b
.b
, level
);
445 checked_last_layer
= MIN2(last_layer
, max_layer
);
447 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
448 struct pipe_surface
*cbsurf
, surf_tmpl
;
450 surf_tmpl
.format
= rtex
->resource
.b
.b
.format
;
451 surf_tmpl
.u
.tex
.level
= level
;
452 surf_tmpl
.u
.tex
.first_layer
= layer
;
453 surf_tmpl
.u
.tex
.last_layer
= layer
;
454 cbsurf
= ctx
->create_surface(ctx
, &rtex
->resource
.b
.b
, &surf_tmpl
);
456 si_blitter_begin(ctx
, SI_DECOMPRESS
);
457 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
460 pipe_surface_reference(&cbsurf
, NULL
);
463 /* The texture will always be dirty if some layers aren't flushed.
464 * I don't think this case occurs often though. */
465 if (first_layer
== 0 && last_layer
>= max_layer
) {
466 rtex
->dirty_level_mask
&= ~(1 << level
);
472 si_decompress_color_texture(struct si_context
*sctx
, struct r600_texture
*tex
,
473 unsigned first_level
, unsigned last_level
)
475 /* CMASK or DCC can be discarded and we can still end up here. */
476 if (!tex
->cmask
.size
&& !tex
->fmask
.size
&& !tex
->dcc_offset
)
479 si_blit_decompress_color(&sctx
->b
.b
, tex
, first_level
, last_level
, 0,
480 util_max_layer(&tex
->resource
.b
.b
, first_level
),
485 si_decompress_sampler_color_textures(struct si_context
*sctx
,
486 struct si_textures_info
*textures
)
489 unsigned mask
= textures
->compressed_colortex_mask
;
492 struct pipe_sampler_view
*view
;
493 struct r600_texture
*tex
;
495 i
= u_bit_scan(&mask
);
497 view
= textures
->views
.views
[i
];
500 tex
= (struct r600_texture
*)view
->texture
;
502 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
503 view
->u
.tex
.last_level
);
508 si_decompress_image_color_textures(struct si_context
*sctx
,
509 struct si_images_info
*images
)
512 unsigned mask
= images
->compressed_colortex_mask
;
515 const struct pipe_image_view
*view
;
516 struct r600_texture
*tex
;
518 i
= u_bit_scan(&mask
);
520 view
= &images
->views
[i
];
521 assert(view
->resource
->target
!= PIPE_BUFFER
);
523 tex
= (struct r600_texture
*)view
->resource
;
525 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
530 static void si_check_render_feedback_textures(struct si_context
*sctx
,
531 struct si_textures_info
*textures
)
533 uint32_t mask
= textures
->views
.enabled_mask
;
536 const struct pipe_sampler_view
*view
;
537 struct r600_texture
*tex
;
538 bool render_feedback
= false;
540 unsigned i
= u_bit_scan(&mask
);
542 view
= textures
->views
.views
[i
];
543 if(view
->texture
->target
== PIPE_BUFFER
)
546 tex
= (struct r600_texture
*)view
->texture
;
547 if (!tex
->dcc_offset
)
550 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
551 struct r600_surface
* surf
;
553 if (!sctx
->framebuffer
.state
.cbufs
[j
])
556 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
558 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
559 surf
->base
.u
.tex
.level
>= view
->u
.tex
.first_level
&&
560 surf
->base
.u
.tex
.level
<= view
->u
.tex
.last_level
&&
561 surf
->base
.u
.tex
.first_layer
<= view
->u
.tex
.last_layer
&&
562 surf
->base
.u
.tex
.last_layer
>= view
->u
.tex
.first_layer
) {
563 render_feedback
= true;
569 r600_texture_disable_dcc(&sctx
->b
, tex
);
573 static void si_check_render_feedback_images(struct si_context
*sctx
,
574 struct si_images_info
*images
)
576 uint32_t mask
= images
->enabled_mask
;
579 const struct pipe_image_view
*view
;
580 struct r600_texture
*tex
;
581 bool render_feedback
= false;
583 unsigned i
= u_bit_scan(&mask
);
585 view
= &images
->views
[i
];
586 if (view
->resource
->target
== PIPE_BUFFER
)
589 tex
= (struct r600_texture
*)view
->resource
;
590 if (!tex
->dcc_offset
)
593 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
594 struct r600_surface
* surf
;
596 if (!sctx
->framebuffer
.state
.cbufs
[j
])
599 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
601 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
602 surf
->base
.u
.tex
.level
== view
->u
.tex
.level
&&
603 surf
->base
.u
.tex
.first_layer
<= view
->u
.tex
.last_layer
&&
604 surf
->base
.u
.tex
.last_layer
>= view
->u
.tex
.first_layer
) {
605 render_feedback
= true;
611 r600_texture_disable_dcc(&sctx
->b
, tex
);
615 static void si_check_render_feedback(struct si_context
*sctx
)
618 if (!sctx
->need_check_render_feedback
)
621 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
622 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
623 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
625 sctx
->need_check_render_feedback
= false;
628 static void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
)
630 unsigned compressed_colortex_counter
, mask
;
632 if (sctx
->blitter
->running
)
635 /* Update the compressed_colortex_mask if necessary. */
636 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->b
.compressed_colortex_counter
);
637 if (compressed_colortex_counter
!= sctx
->b
.last_compressed_colortex_counter
) {
638 sctx
->b
.last_compressed_colortex_counter
= compressed_colortex_counter
;
639 si_update_compressed_colortex_masks(sctx
);
642 /* Decompress color & depth textures if needed. */
643 mask
= sctx
->compressed_tex_shader_mask
& shader_mask
;
645 unsigned i
= u_bit_scan(&mask
);
647 if (sctx
->samplers
[i
].depth_texture_mask
) {
648 si_flush_depth_textures(sctx
, &sctx
->samplers
[i
]);
650 if (sctx
->samplers
[i
].compressed_colortex_mask
) {
651 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
653 if (sctx
->images
[i
].compressed_colortex_mask
) {
654 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
658 si_check_render_feedback(sctx
);
661 void si_decompress_graphics_textures(struct si_context
*sctx
)
663 si_decompress_textures(sctx
, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
));
666 void si_decompress_compute_textures(struct si_context
*sctx
)
668 si_decompress_textures(sctx
, 1 << PIPE_SHADER_COMPUTE
);
671 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
672 const union pipe_color_union
*color
,
673 double depth
, unsigned stencil
)
675 struct si_context
*sctx
= (struct si_context
*)ctx
;
676 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
677 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
678 struct r600_texture
*zstex
=
679 zsbuf
? (struct r600_texture
*)zsbuf
->texture
: NULL
;
681 if (buffers
& PIPE_CLEAR_COLOR
) {
682 evergreen_do_fast_color_clear(&sctx
->b
, fb
,
683 &sctx
->framebuffer
.atom
, &buffers
,
684 &sctx
->framebuffer
.dirty_cbufs
,
687 return; /* all buffers have been fast cleared */
690 if (buffers
& PIPE_CLEAR_COLOR
) {
693 /* These buffers cannot use fast clear, make sure to disable expansion. */
694 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
695 struct r600_texture
*tex
;
697 /* If not clearing this buffer, skip. */
698 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
704 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
705 if (tex
->fmask
.size
== 0)
706 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
710 if (zstex
&& zstex
->htile_buffer
&&
711 zsbuf
->u
.tex
.level
== 0 &&
712 zsbuf
->u
.tex
.first_layer
== 0 &&
713 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->resource
.b
.b
, 0)) {
714 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
715 if (buffers
& PIPE_CLEAR_DEPTH
&&
716 (!zstex
->tc_compatible_htile
||
717 depth
== 0 || depth
== 1)) {
718 /* Need to disable EXPCLEAR temporarily if clearing
720 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
721 sctx
->db_depth_disable_expclear
= true;
724 zstex
->depth_clear_value
= depth
;
725 sctx
->framebuffer
.dirty_zsbuf
= true;
726 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_DEPTH_CLEAR */
727 sctx
->db_depth_clear
= true;
728 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
731 /* TC-compatible HTILE only supports stencil clears to 0. */
732 if (buffers
& PIPE_CLEAR_STENCIL
&&
733 (!zstex
->tc_compatible_htile
|| stencil
== 0)) {
736 /* Need to disable EXPCLEAR temporarily if clearing
738 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
739 sctx
->db_stencil_disable_expclear
= true;
742 zstex
->stencil_clear_value
= stencil
;
743 sctx
->framebuffer
.dirty_zsbuf
= true;
744 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_STENCIL_CLEAR */
745 sctx
->db_stencil_clear
= true;
746 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
750 si_blitter_begin(ctx
, SI_CLEAR
);
751 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
752 util_framebuffer_get_num_layers(fb
),
753 buffers
, color
, depth
, stencil
);
756 if (sctx
->db_depth_clear
) {
757 sctx
->db_depth_clear
= false;
758 sctx
->db_depth_disable_expclear
= false;
759 zstex
->depth_cleared
= true;
760 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
763 if (sctx
->db_stencil_clear
) {
764 sctx
->db_stencil_clear
= false;
765 sctx
->db_stencil_disable_expclear
= false;
766 zstex
->stencil_cleared
= true;
767 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
771 static void si_clear_render_target(struct pipe_context
*ctx
,
772 struct pipe_surface
*dst
,
773 const union pipe_color_union
*color
,
774 unsigned dstx
, unsigned dsty
,
775 unsigned width
, unsigned height
,
776 bool render_condition_enabled
)
778 struct si_context
*sctx
= (struct si_context
*)ctx
;
780 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
781 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
782 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
783 dstx
, dsty
, width
, height
);
787 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
788 struct pipe_surface
*dst
,
789 unsigned clear_flags
,
792 unsigned dstx
, unsigned dsty
,
793 unsigned width
, unsigned height
,
794 bool render_condition_enabled
)
796 struct si_context
*sctx
= (struct si_context
*)ctx
;
798 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
799 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
800 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
801 dstx
, dsty
, width
, height
);
805 /* Helper for decompressing a portion of a color or depth resource before
806 * blitting if any decompression is needed.
807 * The driver doesn't decompress resources automatically while u_blitter is
809 static void si_decompress_subresource(struct pipe_context
*ctx
,
810 struct pipe_resource
*tex
,
811 unsigned planes
, unsigned level
,
812 unsigned first_layer
, unsigned last_layer
)
814 struct si_context
*sctx
= (struct si_context
*)ctx
;
815 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
817 if (rtex
->db_compatible
) {
818 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
820 if (!(rtex
->surface
.flags
& RADEON_SURF_SBUFFER
))
821 planes
&= ~PIPE_MASK_S
;
823 si_flush_depth_texture(sctx
, rtex
, planes
,
825 first_layer
, last_layer
);
826 } else if (rtex
->fmask
.size
|| rtex
->cmask
.size
|| rtex
->dcc_offset
) {
827 si_blit_decompress_color(ctx
, rtex
, level
, level
,
828 first_layer
, last_layer
, false);
832 struct texture_orig_info
{
842 void si_resource_copy_region(struct pipe_context
*ctx
,
843 struct pipe_resource
*dst
,
845 unsigned dstx
, unsigned dsty
, unsigned dstz
,
846 struct pipe_resource
*src
,
848 const struct pipe_box
*src_box
)
850 struct si_context
*sctx
= (struct si_context
*)ctx
;
851 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
852 struct pipe_surface
*dst_view
, dst_templ
;
853 struct pipe_sampler_view src_templ
, *src_view
;
854 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
855 unsigned dst_width0
, dst_height0
, src_force_level
= 0;
856 struct pipe_box sbox
, dstbox
;
858 /* Handle buffers first. */
859 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
860 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
, 0);
864 assert(u_max_sample(dst
) == u_max_sample(src
));
866 /* The driver doesn't decompress resources automatically while
867 * u_blitter is rendering. */
868 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
,
869 src_box
->z
, src_box
->z
+ src_box
->depth
- 1);
871 dst_width
= u_minify(dst
->width0
, dst_level
);
872 dst_height
= u_minify(dst
->height0
, dst_level
);
873 dst_width0
= dst
->width0
;
874 dst_height0
= dst
->height0
;
875 src_width0
= src
->width0
;
876 src_height0
= src
->height0
;
878 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
879 util_blitter_default_src_texture(&src_templ
, src
, src_level
);
881 if (util_format_is_compressed(src
->format
) ||
882 util_format_is_compressed(dst
->format
)) {
883 unsigned blocksize
= rsrc
->surface
.bpe
;
886 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
888 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
889 dst_templ
.format
= src_templ
.format
;
891 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
892 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
893 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
894 dst_height0
= util_format_get_nblocksy(dst
->format
, dst_height0
);
895 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
896 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
898 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
899 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
901 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
902 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
904 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
905 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
906 sbox
.depth
= src_box
->depth
;
909 src_force_level
= src_level
;
910 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
)) {
911 if (util_format_is_subsampled_422(src
->format
)) {
912 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
913 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
915 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
916 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
917 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
919 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
922 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
923 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
926 unsigned blocksize
= rsrc
->surface
.bpe
;
930 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
931 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
934 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
935 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
938 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
939 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
942 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
943 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
946 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
947 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
950 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
951 util_format_short_name(src
->format
), blocksize
);
957 vi_disable_dcc_if_incompatible_format(&sctx
->b
, dst
, dst_level
,
959 vi_disable_dcc_if_incompatible_format(&sctx
->b
, src
, src_level
,
962 /* Initialize the surface. */
963 dst_view
= r600_create_surface_custom(ctx
, dst
, &dst_templ
,
964 dst_width0
, dst_height0
,
965 dst_width
, dst_height
);
967 /* Initialize the sampler view. */
968 src_view
= si_create_sampler_view_custom(ctx
, src
, &src_templ
,
969 src_width0
, src_height0
,
972 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
),
973 abs(src_box
->depth
), &dstbox
);
976 si_blitter_begin(ctx
, SI_COPY
);
977 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
,
978 src_view
, src_box
, src_width0
, src_height0
,
979 PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
,
983 pipe_surface_reference(&dst_view
, NULL
);
984 pipe_sampler_view_reference(&src_view
, NULL
);
987 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
,
988 const struct pipe_blit_info
*info
)
990 struct si_context
*sctx
= (struct si_context
*)ctx
;
991 struct r600_texture
*src
= (struct r600_texture
*)info
->src
.resource
;
992 struct r600_texture
*dst
= (struct r600_texture
*)info
->dst
.resource
;
993 MAYBE_UNUSED
struct r600_texture
*rtmp
;
994 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
995 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
996 enum pipe_format format
= info
->src
.format
;
997 unsigned sample_mask
= ~0;
998 struct pipe_resource
*tmp
, templ
;
999 struct pipe_blit_info blit
;
1001 /* Check basic requirements for hw resolve. */
1002 if (!(info
->src
.resource
->nr_samples
> 1 &&
1003 info
->dst
.resource
->nr_samples
<= 1 &&
1004 !util_format_is_pure_integer(format
) &&
1005 !util_format_is_depth_or_stencil(format
) &&
1006 util_max_layer(info
->src
.resource
, 0) == 0))
1009 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1010 * the format is R16G16. Use R16A16, which does work.
1012 if (format
== PIPE_FORMAT_R16G16_UNORM
)
1013 format
= PIPE_FORMAT_R16A16_UNORM
;
1014 if (format
== PIPE_FORMAT_R16G16_SNORM
)
1015 format
= PIPE_FORMAT_R16A16_SNORM
;
1017 /* Check the remaining requirements for hw resolve. */
1018 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 &&
1019 !info
->scissor_enable
&&
1020 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
1021 util_is_format_compatible(util_format_description(info
->src
.format
),
1022 util_format_description(info
->dst
.format
)) &&
1023 dst_width
== info
->src
.resource
->width0
&&
1024 dst_height
== info
->src
.resource
->height0
&&
1025 info
->dst
.box
.x
== 0 &&
1026 info
->dst
.box
.y
== 0 &&
1027 info
->dst
.box
.width
== dst_width
&&
1028 info
->dst
.box
.height
== dst_height
&&
1029 info
->dst
.box
.depth
== 1 &&
1030 info
->src
.box
.x
== 0 &&
1031 info
->src
.box
.y
== 0 &&
1032 info
->src
.box
.width
== dst_width
&&
1033 info
->src
.box
.height
== dst_height
&&
1034 info
->src
.box
.depth
== 1 &&
1035 !dst
->surface
.is_linear
&&
1036 (!dst
->cmask
.size
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1037 /* Check the last constraint. */
1038 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1039 /* The next fast clear will switch to this mode to
1040 * get direct hw resolve next time if the mode is
1043 src
->last_msaa_resolve_target_micro_mode
=
1044 dst
->surface
.micro_tile_mode
;
1045 goto resolve_to_temp
;
1048 /* Resolving into a surface with DCC is unsupported. Since
1049 * it's being overwritten anyway, clear it to uncompressed.
1050 * This is still the fastest codepath even with this clear.
1052 if (vi_dcc_enabled(dst
, info
->dst
.level
)) {
1053 /* TODO: Implement per-level DCC clears for GFX9. */
1054 if (sctx
->b
.chip_class
>= GFX9
&&
1055 info
->dst
.resource
->last_level
!= 0)
1056 goto resolve_to_temp
;
1058 vi_dcc_clear_level(&sctx
->b
, dst
, info
->dst
.level
,
1060 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1063 /* Resolve directly from src to dst. */
1064 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
1065 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1066 util_blitter_custom_resolve_color(sctx
->blitter
,
1067 info
->dst
.resource
, info
->dst
.level
,
1069 info
->src
.resource
, info
->src
.box
.z
,
1070 sample_mask
, sctx
->custom_blend_resolve
,
1072 si_blitter_end(ctx
);
1077 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1078 * a temporary texture and blit.
1080 memset(&templ
, 0, sizeof(templ
));
1081 templ
.target
= PIPE_TEXTURE_2D
;
1082 templ
.format
= info
->src
.resource
->format
;
1083 templ
.width0
= info
->src
.resource
->width0
;
1084 templ
.height0
= info
->src
.resource
->height0
;
1086 templ
.array_size
= 1;
1087 templ
.usage
= PIPE_USAGE_DEFAULT
;
1088 templ
.flags
= R600_RESOURCE_FLAG_FORCE_TILING
|
1089 R600_RESOURCE_FLAG_DISABLE_DCC
;
1091 /* The src and dst microtile modes must be the same. */
1092 if (src
->surface
.micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1093 templ
.bind
= PIPE_BIND_SCANOUT
;
1097 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1100 rtmp
= (struct r600_texture
*)tmp
;
1102 assert(!rtmp
->surface
.is_linear
);
1103 assert(src
->surface
.micro_tile_mode
== rtmp
->surface
.micro_tile_mode
);
1106 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
1107 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1108 util_blitter_custom_resolve_color(sctx
->blitter
, tmp
, 0, 0,
1109 info
->src
.resource
, info
->src
.box
.z
,
1110 sample_mask
, sctx
->custom_blend_resolve
,
1112 si_blitter_end(ctx
);
1116 blit
.src
.resource
= tmp
;
1119 si_blitter_begin(ctx
, SI_BLIT
|
1120 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1121 util_blitter_blit(sctx
->blitter
, &blit
);
1122 si_blitter_end(ctx
);
1124 pipe_resource_reference(&tmp
, NULL
);
1128 static void si_blit(struct pipe_context
*ctx
,
1129 const struct pipe_blit_info
*info
)
1131 struct si_context
*sctx
= (struct si_context
*)ctx
;
1132 struct r600_texture
*rdst
= (struct r600_texture
*)info
->dst
.resource
;
1134 if (do_hardware_msaa_resolve(ctx
, info
)) {
1138 /* Using SDMA for copying to a linear texture in GTT is much faster.
1139 * This improves DRI PRIME performance.
1141 * resource_copy_region can't do this yet, because dma_copy calls it
1142 * on failure (recursion).
1144 if (rdst
->surface
.is_linear
&&
1146 util_can_blit_via_copy_region(info
, false)) {
1147 sctx
->b
.dma_copy(ctx
, info
->dst
.resource
, info
->dst
.level
,
1148 info
->dst
.box
.x
, info
->dst
.box
.y
,
1150 info
->src
.resource
, info
->src
.level
,
1155 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1157 /* The driver doesn't decompress resources automatically while
1158 * u_blitter is rendering. */
1159 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->src
.resource
,
1162 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->dst
.resource
,
1165 si_decompress_subresource(ctx
, info
->src
.resource
, info
->mask
,
1168 info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1170 if (sctx
->screen
->b
.debug_flags
& DBG_FORCE_DMA
&&
1171 util_try_blit_via_copy_region(ctx
, info
))
1174 si_blitter_begin(ctx
, SI_BLIT
|
1175 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1176 util_blitter_blit(sctx
->blitter
, info
);
1177 si_blitter_end(ctx
);
1180 static boolean
si_generate_mipmap(struct pipe_context
*ctx
,
1181 struct pipe_resource
*tex
,
1182 enum pipe_format format
,
1183 unsigned base_level
, unsigned last_level
,
1184 unsigned first_layer
, unsigned last_layer
)
1186 struct si_context
*sctx
= (struct si_context
*)ctx
;
1187 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1189 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1192 /* The driver doesn't decompress resources automatically while
1193 * u_blitter is rendering. */
1194 vi_disable_dcc_if_incompatible_format(&sctx
->b
, tex
, base_level
,
1196 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
,
1197 base_level
, first_layer
, last_layer
);
1199 /* Clear dirty_level_mask for the levels that will be overwritten. */
1200 assert(base_level
< last_level
);
1201 rtex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1,
1202 last_level
- base_level
);
1204 si_blitter_begin(ctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1205 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
,
1206 base_level
, last_level
,
1207 first_layer
, last_layer
);
1208 si_blitter_end(ctx
);
1212 static void si_flush_resource(struct pipe_context
*ctx
,
1213 struct pipe_resource
*res
)
1215 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
1217 assert(res
->target
!= PIPE_BUFFER
);
1218 assert(!rtex
->dcc_separate_buffer
|| rtex
->dcc_gather_statistics
);
1220 /* st/dri calls flush twice per frame (not a bug), this prevents double
1222 if (rtex
->dcc_separate_buffer
&& !rtex
->separate_dcc_dirty
)
1225 if (!rtex
->is_depth
&& (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
1226 si_blit_decompress_color(ctx
, rtex
, 0, res
->last_level
,
1227 0, util_max_layer(res
, 0),
1228 rtex
->dcc_separate_buffer
!= NULL
);
1231 /* Always do the analysis even if DCC is disabled at the moment. */
1232 if (rtex
->dcc_gather_statistics
&& rtex
->separate_dcc_dirty
) {
1233 rtex
->separate_dcc_dirty
= false;
1234 vi_separate_dcc_process_and_reset_stats(ctx
, rtex
);
1238 static void si_decompress_dcc(struct pipe_context
*ctx
,
1239 struct r600_texture
*rtex
)
1241 if (!rtex
->dcc_offset
)
1244 si_blit_decompress_color(ctx
, rtex
, 0, rtex
->resource
.b
.b
.last_level
,
1245 0, util_max_layer(&rtex
->resource
.b
.b
, 0),
1249 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
1250 struct pipe_resource
*dst
,
1251 unsigned offset
, unsigned size
,
1252 const void *clear_value_ptr
,
1253 int clear_value_size
)
1255 struct si_context
*sctx
= (struct si_context
*)ctx
;
1256 uint32_t dword_value
;
1259 assert(offset
% clear_value_size
== 0);
1260 assert(size
% clear_value_size
== 0);
1262 if (clear_value_size
> 4) {
1263 const uint32_t *u32
= clear_value_ptr
;
1264 bool clear_dword_duplicated
= true;
1266 /* See if we can lower large fills to dword fills. */
1267 for (i
= 1; i
< clear_value_size
/ 4; i
++)
1268 if (u32
[0] != u32
[i
]) {
1269 clear_dword_duplicated
= false;
1273 if (!clear_dword_duplicated
) {
1274 /* Use transform feedback for 64-bit, 96-bit, and
1277 union pipe_color_union clear_value
;
1279 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
1280 si_blitter_begin(ctx
, SI_DISABLE_RENDER_COND
);
1281 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
1282 size
, clear_value_size
/ 4,
1284 si_blitter_end(ctx
);
1289 /* Expand the clear value to a dword. */
1290 switch (clear_value_size
) {
1292 dword_value
= *(uint8_t*)clear_value_ptr
;
1293 dword_value
|= (dword_value
<< 8) |
1294 (dword_value
<< 16) |
1295 (dword_value
<< 24);
1298 dword_value
= *(uint16_t*)clear_value_ptr
;
1299 dword_value
|= dword_value
<< 16;
1302 dword_value
= *(uint32_t*)clear_value_ptr
;
1305 sctx
->b
.clear_buffer(ctx
, dst
, offset
, size
, dword_value
,
1306 R600_COHERENCY_SHADER
);
1309 void si_init_blit_functions(struct si_context
*sctx
)
1311 sctx
->b
.b
.clear
= si_clear
;
1312 sctx
->b
.b
.clear_buffer
= si_pipe_clear_buffer
;
1313 sctx
->b
.b
.clear_render_target
= si_clear_render_target
;
1314 sctx
->b
.b
.clear_depth_stencil
= si_clear_depth_stencil
;
1315 sctx
->b
.b
.resource_copy_region
= si_resource_copy_region
;
1316 sctx
->b
.b
.blit
= si_blit
;
1317 sctx
->b
.b
.flush_resource
= si_flush_resource
;
1318 sctx
->b
.b
.generate_mipmap
= si_generate_mipmap
;
1319 sctx
->b
.blit_decompress_depth
= si_blit_decompress_depth
;
1320 sctx
->b
.decompress_dcc
= si_decompress_dcc
;