2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "radeonsi/si_pipe.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28 #include "util/u_transfer.h"
32 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
33 struct pb_buffer
*buf
,
34 enum radeon_bo_usage usage
)
36 if (sctx
->ws
->cs_is_buffer_referenced(sctx
->gfx_cs
, buf
, usage
)) {
39 if (radeon_emitted(sctx
->dma_cs
, 0) &&
40 sctx
->ws
->cs_is_buffer_referenced(sctx
->dma_cs
, buf
, usage
)) {
46 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
47 struct si_resource
*resource
,
50 enum radeon_bo_usage rusage
= RADEON_USAGE_READWRITE
;
53 assert(!(resource
->flags
& RADEON_FLAG_SPARSE
));
55 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
56 return sctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
59 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
60 /* have to wait for the last write */
61 rusage
= RADEON_USAGE_WRITE
;
64 if (radeon_emitted(sctx
->gfx_cs
, sctx
->initial_gfx_cs_size
) &&
65 sctx
->ws
->cs_is_buffer_referenced(sctx
->gfx_cs
,
66 resource
->buf
, rusage
)) {
67 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
68 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
71 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
75 if (radeon_emitted(sctx
->dma_cs
, 0) &&
76 sctx
->ws
->cs_is_buffer_referenced(sctx
->dma_cs
,
77 resource
->buf
, rusage
)) {
78 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
79 si_flush_dma_cs(sctx
, PIPE_FLUSH_ASYNC
, NULL
);
82 si_flush_dma_cs(sctx
, 0, NULL
);
87 if (busy
|| !sctx
->ws
->buffer_wait(resource
->buf
, 0, rusage
)) {
88 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
91 /* We will be wait for the GPU. Wait for any offloaded
92 * CS flush to complete to avoid busy-waiting in the winsys. */
93 sctx
->ws
->cs_sync_flush(sctx
->gfx_cs
);
95 sctx
->ws
->cs_sync_flush(sctx
->dma_cs
);
99 /* Setting the CS to NULL will prevent doing checks we have done already. */
100 return sctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
103 void si_init_resource_fields(struct si_screen
*sscreen
,
104 struct si_resource
*res
,
105 uint64_t size
, unsigned alignment
)
107 struct si_texture
*tex
= (struct si_texture
*)res
;
110 res
->bo_alignment
= alignment
;
112 res
->texture_handle_allocated
= false;
113 res
->image_handle_allocated
= false;
115 switch (res
->b
.b
.usage
) {
116 case PIPE_USAGE_STREAM
:
117 res
->flags
= RADEON_FLAG_GTT_WC
;
119 case PIPE_USAGE_STAGING
:
120 /* Transfers are likely to occur more often with these
122 res
->domains
= RADEON_DOMAIN_GTT
;
124 case PIPE_USAGE_DYNAMIC
:
125 /* Older kernels didn't always flush the HDP cache before
128 if (!sscreen
->info
.kernel_flushes_hdp_before_ib
) {
129 res
->domains
= RADEON_DOMAIN_GTT
;
130 res
->flags
|= RADEON_FLAG_GTT_WC
;
134 case PIPE_USAGE_DEFAULT
:
135 case PIPE_USAGE_IMMUTABLE
:
137 /* Not listing GTT here improves performance in some
139 res
->domains
= RADEON_DOMAIN_VRAM
;
140 res
->flags
|= RADEON_FLAG_GTT_WC
;
144 if (res
->b
.b
.target
== PIPE_BUFFER
&&
145 res
->b
.b
.flags
& PIPE_RESOURCE_FLAG_MAP_PERSISTENT
) {
146 /* Use GTT for all persistent mappings with older
147 * kernels, because they didn't always flush the HDP
148 * cache before CS execution.
150 * Write-combined CPU mappings are fine, the kernel
151 * ensures all CPU writes finish before the GPU
152 * executes a command stream.
154 * radeon doesn't have good BO move throttling, so put all
155 * persistent buffers into GTT to prevent VRAM CPU page faults.
157 if (!sscreen
->info
.kernel_flushes_hdp_before_ib
||
158 sscreen
->info
.drm_major
== 2)
159 res
->domains
= RADEON_DOMAIN_GTT
;
162 /* Tiled textures are unmappable. Always put them in VRAM. */
163 if ((res
->b
.b
.target
!= PIPE_BUFFER
&& !tex
->surface
.is_linear
) ||
164 res
->b
.b
.flags
& SI_RESOURCE_FLAG_UNMAPPABLE
) {
165 res
->domains
= RADEON_DOMAIN_VRAM
;
166 res
->flags
|= RADEON_FLAG_NO_CPU_ACCESS
|
170 /* Displayable and shareable surfaces are not suballocated. */
171 if (res
->b
.b
.bind
& (PIPE_BIND_SHARED
| PIPE_BIND_SCANOUT
))
172 res
->flags
|= RADEON_FLAG_NO_SUBALLOC
; /* shareable */
174 res
->flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
176 if (sscreen
->debug_flags
& DBG(NO_WC
))
177 res
->flags
&= ~RADEON_FLAG_GTT_WC
;
179 if (res
->b
.b
.flags
& SI_RESOURCE_FLAG_READ_ONLY
)
180 res
->flags
|= RADEON_FLAG_READ_ONLY
;
182 if (res
->b
.b
.flags
& SI_RESOURCE_FLAG_32BIT
)
183 res
->flags
|= RADEON_FLAG_32BIT
;
185 /* Set expected VRAM and GART usage for the buffer. */
188 res
->max_forced_staging_uploads
= 0;
189 res
->b
.max_forced_staging_uploads
= 0;
191 if (res
->domains
& RADEON_DOMAIN_VRAM
) {
192 res
->vram_usage
= size
;
194 res
->max_forced_staging_uploads
=
195 res
->b
.max_forced_staging_uploads
=
196 sscreen
->info
.has_dedicated_vram
&&
197 size
>= sscreen
->info
.vram_vis_size
/ 4 ? 1 : 0;
198 } else if (res
->domains
& RADEON_DOMAIN_GTT
) {
199 res
->gart_usage
= size
;
203 bool si_alloc_resource(struct si_screen
*sscreen
,
204 struct si_resource
*res
)
206 struct pb_buffer
*old_buf
, *new_buf
;
208 /* Allocate a new resource. */
209 new_buf
= sscreen
->ws
->buffer_create(sscreen
->ws
, res
->bo_size
,
211 res
->domains
, res
->flags
);
216 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
217 * NULL. This should prevent crashes with multiple contexts using
218 * the same buffer where one of the contexts invalidates it while
219 * the others are using it. */
221 res
->buf
= new_buf
; /* should be atomic */
222 res
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(res
->buf
);
224 if (res
->flags
& RADEON_FLAG_32BIT
) {
225 uint64_t start
= res
->gpu_address
;
226 uint64_t last
= start
+ res
->bo_size
- 1;
230 assert((start
>> 32) == sscreen
->info
.address32_hi
);
231 assert((last
>> 32) == sscreen
->info
.address32_hi
);
234 pb_reference(&old_buf
, NULL
);
236 util_range_set_empty(&res
->valid_buffer_range
);
237 res
->TC_L2_dirty
= false;
239 /* Print debug information. */
240 if (sscreen
->debug_flags
& DBG(VM
) && res
->b
.b
.target
== PIPE_BUFFER
) {
241 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Buffer %"PRIu64
" bytes\n",
242 res
->gpu_address
, res
->gpu_address
+ res
->buf
->size
,
246 if (res
->b
.b
.flags
& SI_RESOURCE_FLAG_CLEAR
)
247 si_screen_clear_buffer(sscreen
, &res
->b
.b
, 0, res
->bo_size
, 0);
252 static void si_buffer_destroy(struct pipe_screen
*screen
,
253 struct pipe_resource
*buf
)
255 struct si_resource
*buffer
= si_resource(buf
);
257 threaded_resource_deinit(buf
);
258 util_range_destroy(&buffer
->valid_buffer_range
);
259 pb_reference(&buffer
->buf
, NULL
);
263 /* Reallocate the buffer a update all resource bindings where the buffer is
266 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
267 * idle by discarding its contents.
270 si_invalidate_buffer(struct si_context
*sctx
,
271 struct si_resource
*buf
)
273 /* Shared buffers can't be reallocated. */
274 if (buf
->b
.is_shared
)
277 /* Sparse buffers can't be reallocated. */
278 if (buf
->flags
& RADEON_FLAG_SPARSE
)
281 /* In AMD_pinned_memory, the user pointer association only gets
282 * broken when the buffer is explicitly re-allocated.
284 if (buf
->b
.is_user_ptr
)
287 /* Check if mapping this buffer would cause waiting for the GPU. */
288 if (si_rings_is_buffer_referenced(sctx
, buf
->buf
, RADEON_USAGE_READWRITE
) ||
289 !sctx
->ws
->buffer_wait(buf
->buf
, 0, RADEON_USAGE_READWRITE
)) {
290 uint64_t old_va
= buf
->gpu_address
;
292 /* Reallocate the buffer in the same pipe_resource. */
293 si_alloc_resource(sctx
->screen
, buf
);
294 si_rebind_buffer(sctx
, &buf
->b
.b
, old_va
);
296 util_range_set_empty(&buf
->valid_buffer_range
);
302 /* Replace the storage of dst with src. */
303 void si_replace_buffer_storage(struct pipe_context
*ctx
,
304 struct pipe_resource
*dst
,
305 struct pipe_resource
*src
)
307 struct si_context
*sctx
= (struct si_context
*)ctx
;
308 struct si_resource
*sdst
= si_resource(dst
);
309 struct si_resource
*ssrc
= si_resource(src
);
310 uint64_t old_gpu_address
= sdst
->gpu_address
;
312 pb_reference(&sdst
->buf
, ssrc
->buf
);
313 sdst
->gpu_address
= ssrc
->gpu_address
;
314 sdst
->b
.b
.bind
= ssrc
->b
.b
.bind
;
315 sdst
->b
.max_forced_staging_uploads
= ssrc
->b
.max_forced_staging_uploads
;
316 sdst
->max_forced_staging_uploads
= ssrc
->max_forced_staging_uploads
;
317 sdst
->flags
= ssrc
->flags
;
319 assert(sdst
->vram_usage
== ssrc
->vram_usage
);
320 assert(sdst
->gart_usage
== ssrc
->gart_usage
);
321 assert(sdst
->bo_size
== ssrc
->bo_size
);
322 assert(sdst
->bo_alignment
== ssrc
->bo_alignment
);
323 assert(sdst
->domains
== ssrc
->domains
);
325 si_rebind_buffer(sctx
, dst
, old_gpu_address
);
328 static void si_invalidate_resource(struct pipe_context
*ctx
,
329 struct pipe_resource
*resource
)
331 struct si_context
*sctx
= (struct si_context
*)ctx
;
332 struct si_resource
*buf
= si_resource(resource
);
334 /* We currently only do anyting here for buffers */
335 if (resource
->target
== PIPE_BUFFER
)
336 (void)si_invalidate_buffer(sctx
, buf
);
339 static void *si_buffer_get_transfer(struct pipe_context
*ctx
,
340 struct pipe_resource
*resource
,
342 const struct pipe_box
*box
,
343 struct pipe_transfer
**ptransfer
,
344 void *data
, struct si_resource
*staging
,
347 struct si_context
*sctx
= (struct si_context
*)ctx
;
348 struct si_transfer
*transfer
;
350 if (usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
)
351 transfer
= slab_alloc(&sctx
->pool_transfers_unsync
);
353 transfer
= slab_alloc(&sctx
->pool_transfers
);
355 transfer
->b
.b
.resource
= NULL
;
356 pipe_resource_reference(&transfer
->b
.b
.resource
, resource
);
357 transfer
->b
.b
.level
= 0;
358 transfer
->b
.b
.usage
= usage
;
359 transfer
->b
.b
.box
= *box
;
360 transfer
->b
.b
.stride
= 0;
361 transfer
->b
.b
.layer_stride
= 0;
362 transfer
->b
.staging
= NULL
;
363 transfer
->offset
= offset
;
364 transfer
->staging
= staging
;
365 *ptransfer
= &transfer
->b
.b
;
369 static void *si_buffer_transfer_map(struct pipe_context
*ctx
,
370 struct pipe_resource
*resource
,
373 const struct pipe_box
*box
,
374 struct pipe_transfer
**ptransfer
)
376 struct si_context
*sctx
= (struct si_context
*)ctx
;
377 struct si_resource
*buf
= si_resource(resource
);
380 assert(box
->x
+ box
->width
<= resource
->width0
);
382 /* From GL_AMD_pinned_memory issues:
384 * 4) Is glMapBuffer on a shared buffer guaranteed to return the
385 * same system address which was specified at creation time?
387 * RESOLVED: NO. The GL implementation might return a different
388 * virtual mapping of that memory, although the same physical
391 * So don't ever use staging buffers.
393 if (buf
->b
.is_user_ptr
)
394 usage
|= PIPE_TRANSFER_PERSISTENT
;
396 /* See if the buffer range being mapped has never been initialized,
397 * in which case it can be mapped unsynchronized. */
398 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
399 TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
)) &&
400 usage
& PIPE_TRANSFER_WRITE
&&
402 !util_ranges_intersect(&buf
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
)) {
403 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
406 /* If discarding the entire range, discard the whole resource instead. */
407 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
&&
408 box
->x
== 0 && box
->width
== resource
->width0
) {
409 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
412 /* If a buffer in VRAM is too large and the range is discarded, don't
413 * map it directly. This makes sure that the buffer stays in VRAM.
415 bool force_discard_range
= false;
416 if (usage
& (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
417 PIPE_TRANSFER_DISCARD_RANGE
) &&
418 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
419 /* Try not to decrement the counter if it's not positive. Still racy,
420 * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
421 buf
->max_forced_staging_uploads
> 0 &&
422 p_atomic_dec_return(&buf
->max_forced_staging_uploads
) >= 0) {
423 usage
&= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
424 PIPE_TRANSFER_UNSYNCHRONIZED
);
425 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
426 force_discard_range
= true;
429 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
&&
430 !(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
431 TC_TRANSFER_MAP_NO_INVALIDATE
))) {
432 assert(usage
& PIPE_TRANSFER_WRITE
);
434 if (si_invalidate_buffer(sctx
, buf
)) {
435 /* At this point, the buffer is always idle. */
436 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
438 /* Fall back to a temporary buffer. */
439 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
443 if (usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
&&
444 buf
->b
.b
.flags
& SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
) {
445 usage
&= ~(PIPE_TRANSFER_UNSYNCHRONIZED
|
446 PIPE_TRANSFER_PERSISTENT
);
447 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
448 force_discard_range
= true;
451 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
&&
452 ((!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
453 PIPE_TRANSFER_PERSISTENT
))) ||
454 (buf
->flags
& RADEON_FLAG_SPARSE
))) {
455 assert(usage
& PIPE_TRANSFER_WRITE
);
457 /* Check if mapping this buffer would cause waiting for the GPU.
459 if (buf
->flags
& RADEON_FLAG_SPARSE
||
460 force_discard_range
||
461 si_rings_is_buffer_referenced(sctx
, buf
->buf
, RADEON_USAGE_READWRITE
) ||
462 !sctx
->ws
->buffer_wait(buf
->buf
, 0, RADEON_USAGE_READWRITE
)) {
463 /* Do a wait-free write-only transfer using a temporary buffer. */
464 struct u_upload_mgr
*uploader
;
465 struct si_resource
*staging
= NULL
;
468 /* If we are not called from the driver thread, we have
469 * to use the uploader from u_threaded_context, which is
470 * local to the calling thread.
472 if (usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
)
473 uploader
= sctx
->tc
->base
.stream_uploader
;
475 uploader
= sctx
->b
.stream_uploader
;
477 u_upload_alloc(uploader
, 0,
478 box
->width
+ (box
->x
% SI_MAP_BUFFER_ALIGNMENT
),
479 sctx
->screen
->info
.tcc_cache_line_size
,
480 &offset
, (struct pipe_resource
**)&staging
,
484 data
+= box
->x
% SI_MAP_BUFFER_ALIGNMENT
;
485 return si_buffer_get_transfer(ctx
, resource
, usage
, box
,
486 ptransfer
, data
, staging
, offset
);
487 } else if (buf
->flags
& RADEON_FLAG_SPARSE
) {
491 /* At this point, the buffer is always idle (we checked it above). */
492 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
495 /* Use a staging buffer in cached GTT for reads. */
496 else if (((usage
& PIPE_TRANSFER_READ
) &&
497 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
498 (buf
->domains
& RADEON_DOMAIN_VRAM
||
499 buf
->flags
& RADEON_FLAG_GTT_WC
)) ||
500 (buf
->flags
& RADEON_FLAG_SPARSE
)) {
501 struct si_resource
*staging
;
503 assert(!(usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
));
504 staging
= si_resource(pipe_buffer_create(
505 ctx
->screen
, 0, PIPE_USAGE_STAGING
,
506 box
->width
+ (box
->x
% SI_MAP_BUFFER_ALIGNMENT
)));
508 /* Copy the VRAM buffer to the staging buffer. */
509 sctx
->dma_copy(ctx
, &staging
->b
.b
, 0,
510 box
->x
% SI_MAP_BUFFER_ALIGNMENT
,
511 0, 0, resource
, 0, box
);
513 data
= si_buffer_map_sync_with_rings(sctx
, staging
,
514 usage
& ~PIPE_TRANSFER_UNSYNCHRONIZED
);
516 si_resource_reference(&staging
, NULL
);
519 data
+= box
->x
% SI_MAP_BUFFER_ALIGNMENT
;
521 return si_buffer_get_transfer(ctx
, resource
, usage
, box
,
522 ptransfer
, data
, staging
, 0);
523 } else if (buf
->flags
& RADEON_FLAG_SPARSE
) {
528 data
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
);
534 return si_buffer_get_transfer(ctx
, resource
, usage
, box
,
535 ptransfer
, data
, NULL
, 0);
538 static void si_buffer_do_flush_region(struct pipe_context
*ctx
,
539 struct pipe_transfer
*transfer
,
540 const struct pipe_box
*box
)
542 struct si_context
*sctx
= (struct si_context
*)ctx
;
543 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
544 struct si_resource
*buf
= si_resource(transfer
->resource
);
546 if (stransfer
->staging
) {
547 unsigned src_offset
= stransfer
->offset
+
548 transfer
->box
.x
% SI_MAP_BUFFER_ALIGNMENT
+
549 (box
->x
- transfer
->box
.x
);
551 if (buf
->b
.b
.flags
& SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
) {
552 /* This should be true for all uploaders. */
553 assert(transfer
->box
.x
== 0);
555 /* Find a previous upload and extend its range. The last
556 * upload is likely to be at the end of the list.
558 for (int i
= sctx
->num_sdma_uploads
- 1; i
>= 0; i
--) {
559 struct si_sdma_upload
*up
= &sctx
->sdma_uploads
[i
];
564 assert(up
->src
== stransfer
->staging
);
565 assert(box
->x
> up
->dst_offset
);
566 up
->size
= box
->x
+ box
->width
- up
->dst_offset
;
570 /* Enlarge the array if it's full. */
571 if (sctx
->num_sdma_uploads
== sctx
->max_sdma_uploads
) {
574 sctx
->max_sdma_uploads
+= 4;
575 size
= sctx
->max_sdma_uploads
* sizeof(sctx
->sdma_uploads
[0]);
576 sctx
->sdma_uploads
= realloc(sctx
->sdma_uploads
, size
);
579 /* Add a new upload. */
580 struct si_sdma_upload
*up
=
581 &sctx
->sdma_uploads
[sctx
->num_sdma_uploads
++];
582 up
->dst
= up
->src
= NULL
;
583 si_resource_reference(&up
->dst
, buf
);
584 si_resource_reference(&up
->src
, stransfer
->staging
);
585 up
->dst_offset
= box
->x
;
586 up
->src_offset
= src_offset
;
587 up
->size
= box
->width
;
591 /* Copy the staging buffer into the original one. */
592 si_copy_buffer(sctx
, transfer
->resource
, &stransfer
->staging
->b
.b
,
593 box
->x
, src_offset
, box
->width
);
596 util_range_add(&buf
->valid_buffer_range
, box
->x
,
597 box
->x
+ box
->width
);
600 static void si_buffer_flush_region(struct pipe_context
*ctx
,
601 struct pipe_transfer
*transfer
,
602 const struct pipe_box
*rel_box
)
604 unsigned required_usage
= PIPE_TRANSFER_WRITE
|
605 PIPE_TRANSFER_FLUSH_EXPLICIT
;
607 if ((transfer
->usage
& required_usage
) == required_usage
) {
610 u_box_1d(transfer
->box
.x
+ rel_box
->x
, rel_box
->width
, &box
);
611 si_buffer_do_flush_region(ctx
, transfer
, &box
);
615 static void si_buffer_transfer_unmap(struct pipe_context
*ctx
,
616 struct pipe_transfer
*transfer
)
618 struct si_context
*sctx
= (struct si_context
*)ctx
;
619 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
621 if (transfer
->usage
& PIPE_TRANSFER_WRITE
&&
622 !(transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
))
623 si_buffer_do_flush_region(ctx
, transfer
, &transfer
->box
);
625 si_resource_reference(&stransfer
->staging
, NULL
);
626 assert(stransfer
->b
.staging
== NULL
); /* for threaded context only */
627 pipe_resource_reference(&transfer
->resource
, NULL
);
629 /* Don't use pool_transfers_unsync. We are always in the driver
631 slab_free(&sctx
->pool_transfers
, transfer
);
634 static void si_buffer_subdata(struct pipe_context
*ctx
,
635 struct pipe_resource
*buffer
,
636 unsigned usage
, unsigned offset
,
637 unsigned size
, const void *data
)
639 struct pipe_transfer
*transfer
= NULL
;
643 u_box_1d(offset
, size
, &box
);
644 map
= si_buffer_transfer_map(ctx
, buffer
, 0,
645 PIPE_TRANSFER_WRITE
|
646 PIPE_TRANSFER_DISCARD_RANGE
|
652 memcpy(map
, data
, size
);
653 si_buffer_transfer_unmap(ctx
, transfer
);
656 static const struct u_resource_vtbl si_buffer_vtbl
=
658 NULL
, /* get_handle */
659 si_buffer_destroy
, /* resource_destroy */
660 si_buffer_transfer_map
, /* transfer_map */
661 si_buffer_flush_region
, /* transfer_flush_region */
662 si_buffer_transfer_unmap
, /* transfer_unmap */
665 static struct si_resource
*
666 si_alloc_buffer_struct(struct pipe_screen
*screen
,
667 const struct pipe_resource
*templ
)
669 struct si_resource
*buf
;
671 buf
= MALLOC_STRUCT(si_resource
);
674 buf
->b
.b
.next
= NULL
;
675 pipe_reference_init(&buf
->b
.b
.reference
, 1);
676 buf
->b
.b
.screen
= screen
;
678 buf
->b
.vtbl
= &si_buffer_vtbl
;
679 threaded_resource_init(&buf
->b
.b
);
682 buf
->bind_history
= 0;
683 buf
->TC_L2_dirty
= false;
684 util_range_init(&buf
->valid_buffer_range
);
688 static struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
689 const struct pipe_resource
*templ
,
692 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
693 struct si_resource
*buf
= si_alloc_buffer_struct(screen
, templ
);
695 if (templ
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
696 buf
->b
.b
.flags
|= SI_RESOURCE_FLAG_UNMAPPABLE
;
698 si_init_resource_fields(sscreen
, buf
, templ
->width0
, alignment
);
700 if (templ
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
701 buf
->flags
|= RADEON_FLAG_SPARSE
;
703 if (!si_alloc_resource(sscreen
, buf
)) {
710 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
711 unsigned flags
, unsigned usage
,
712 unsigned size
, unsigned alignment
)
714 struct pipe_resource buffer
;
716 memset(&buffer
, 0, sizeof buffer
);
717 buffer
.target
= PIPE_BUFFER
;
718 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
720 buffer
.usage
= usage
;
721 buffer
.flags
= flags
;
722 buffer
.width0
= size
;
725 buffer
.array_size
= 1;
726 return si_buffer_create(screen
, &buffer
, alignment
);
729 struct si_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
730 unsigned flags
, unsigned usage
,
731 unsigned size
, unsigned alignment
)
733 return si_resource(pipe_aligned_buffer_create(screen
, flags
, usage
,
737 static struct pipe_resource
*
738 si_buffer_from_user_memory(struct pipe_screen
*screen
,
739 const struct pipe_resource
*templ
,
742 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
743 struct radeon_winsys
*ws
= sscreen
->ws
;
744 struct si_resource
*buf
= si_alloc_buffer_struct(screen
, templ
);
746 buf
->domains
= RADEON_DOMAIN_GTT
;
748 buf
->b
.is_user_ptr
= true;
749 util_range_add(&buf
->valid_buffer_range
, 0, templ
->width0
);
750 util_range_add(&buf
->b
.valid_buffer_range
, 0, templ
->width0
);
752 /* Convert a user pointer to a buffer. */
753 buf
->buf
= ws
->buffer_from_ptr(ws
, user_memory
, templ
->width0
);
759 buf
->gpu_address
= ws
->buffer_get_virtual_address(buf
->buf
);
761 buf
->gart_usage
= templ
->width0
;
766 static struct pipe_resource
*si_resource_create(struct pipe_screen
*screen
,
767 const struct pipe_resource
*templ
)
769 if (templ
->target
== PIPE_BUFFER
) {
770 return si_buffer_create(screen
, templ
, 256);
772 return si_texture_create(screen
, templ
);
776 static bool si_resource_commit(struct pipe_context
*pctx
,
777 struct pipe_resource
*resource
,
778 unsigned level
, struct pipe_box
*box
,
781 struct si_context
*ctx
= (struct si_context
*)pctx
;
782 struct si_resource
*res
= si_resource(resource
);
785 * Since buffer commitment changes cannot be pipelined, we need to
786 * (a) flush any pending commands that refer to the buffer we're about
788 * (b) wait for threaded submit to finish, including those that were
789 * triggered by some other, earlier operation.
791 if (radeon_emitted(ctx
->gfx_cs
, ctx
->initial_gfx_cs_size
) &&
792 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx_cs
,
793 res
->buf
, RADEON_USAGE_READWRITE
)) {
794 si_flush_gfx_cs(ctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
796 if (radeon_emitted(ctx
->dma_cs
, 0) &&
797 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma_cs
,
798 res
->buf
, RADEON_USAGE_READWRITE
)) {
799 si_flush_dma_cs(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
802 ctx
->ws
->cs_sync_flush(ctx
->dma_cs
);
803 ctx
->ws
->cs_sync_flush(ctx
->gfx_cs
);
805 assert(resource
->target
== PIPE_BUFFER
);
807 return ctx
->ws
->buffer_commit(res
->buf
, box
->x
, box
->width
, commit
);
810 void si_init_screen_buffer_functions(struct si_screen
*sscreen
)
812 sscreen
->b
.resource_create
= si_resource_create
;
813 sscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
814 sscreen
->b
.resource_from_user_memory
= si_buffer_from_user_memory
;
817 void si_init_buffer_functions(struct si_context
*sctx
)
819 sctx
->b
.invalidate_resource
= si_invalidate_resource
;
820 sctx
->b
.transfer_map
= u_transfer_map_vtbl
;
821 sctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
822 sctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
823 sctx
->b
.texture_subdata
= u_default_texture_subdata
;
824 sctx
->b
.buffer_subdata
= si_buffer_subdata
;
825 sctx
->b
.resource_commit
= si_resource_commit
;