src/gallium/drivers/radeonsi/si_buffer.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "radeonsi/si_pipe.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "util/u_transfer.h"
  29 #include <inttypes.h>
  30 #include <stdio.h>
  31
  32 bool si_rings_is_buffer_referenced(struct si_context *sctx,
  33                                    struct pb_buffer *buf,
  34                                    enum radeon_bo_usage usage)
  35 {
  36         if (sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs, buf, usage)) {
  37                 return true;
  38         }
  39         if (radeon_emitted(sctx->dma_cs, 0) &&
  40             sctx->ws->cs_is_buffer_referenced(sctx->dma_cs, buf, usage)) {
  41                 return true;
  42         }
  43         return false;
  44 }
  45
  46 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
  47                                     struct r600_resource *resource,
  48                                     unsigned usage)
  49 {
  50         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  51         bool busy = false;
  52
  53         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  54
  55         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  56                 return sctx->ws->buffer_map(resource->buf, NULL, usage);
  57         }
  58
  59         if (!(usage & PIPE_TRANSFER_WRITE)) {
  60                 /* have to wait for the last write */
  61                 rusage = RADEON_USAGE_WRITE;
  62         }
  63
  64         if (radeon_emitted(sctx->gfx_cs, sctx->initial_gfx_cs_size) &&
  65             sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs,
  66                                                 resource->buf, rusage)) {
  67                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  68                         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  69                         return NULL;
  70                 } else {
  71                         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  72                         busy = true;
  73                 }
  74         }
  75         if (radeon_emitted(sctx->dma_cs, 0) &&
  76             sctx->ws->cs_is_buffer_referenced(sctx->dma_cs,
  77                                                 resource->buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         si_flush_dma_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         si_flush_dma_cs(sctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || !sctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         sctx->ws->cs_sync_flush(sctx->gfx_cs);
  94                         if (sctx->dma_cs)
  95                                 sctx->ws->cs_sync_flush(sctx->dma_cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return sctx->ws->buffer_map(resource->buf, NULL, usage);
 101 }
 102
 103 void si_init_resource_fields(struct si_screen *sscreen,
 104                              struct r600_resource *res,
 105                              uint64_t size, unsigned alignment)
 106 {
 107         struct si_texture *tex = (struct si_texture*)res;
 108
 109         res->bo_size = size;
 110         res->bo_alignment = alignment;
 111         res->flags = 0;
 112         res->texture_handle_allocated = false;
 113         res->image_handle_allocated = false;
 114
 115         switch (res->b.b.usage) {
 116         case PIPE_USAGE_STREAM:
 117                 res->flags = RADEON_FLAG_GTT_WC;
 118                 /* fall through */
 119         case PIPE_USAGE_STAGING:
 120                 /* Transfers are likely to occur more often with these
 121                  * resources. */
 122                 res->domains = RADEON_DOMAIN_GTT;
 123                 break;
 124         case PIPE_USAGE_DYNAMIC:
 125                 /* Older kernels didn't always flush the HDP cache before
 126                  * CS execution
 127                  */
 128                 if (!sscreen->info.kernel_flushes_hdp_before_ib) {
 129                         res->domains = RADEON_DOMAIN_GTT;
 130                         res->flags |= RADEON_FLAG_GTT_WC;
 131                         break;
 132                 }
 133                 /* fall through */
 134         case PIPE_USAGE_DEFAULT:
 135         case PIPE_USAGE_IMMUTABLE:
 136         default:
 137                 /* Not listing GTT here improves performance in some
 138                  * apps. */
 139                 res->domains = RADEON_DOMAIN_VRAM;
 140                 res->flags |= RADEON_FLAG_GTT_WC;
 141                 break;
 142         }
 143
 144         if (res->b.b.target == PIPE_BUFFER &&
 145             res->b.b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
 146                 /* Use GTT for all persistent mappings with older
 147                  * kernels, because they didn't always flush the HDP
 148                  * cache before CS execution.
 149                  *
 150                  * Write-combined CPU mappings are fine, the kernel
 151                  * ensures all CPU writes finish before the GPU
 152                  * executes a command stream.
 153                  *
 154                  * radeon doesn't have good BO move throttling, so put all
 155                  * persistent buffers into GTT to prevent VRAM CPU page faults.
 156                  */
 157                 if (!sscreen->info.kernel_flushes_hdp_before_ib ||
 158                     sscreen->info.drm_major == 2)
 159                         res->domains = RADEON_DOMAIN_GTT;
 160         }
 161
 162         /* Tiled textures are unmappable. Always put them in VRAM. */
 163         if ((res->b.b.target != PIPE_BUFFER && !tex->surface.is_linear) ||
 164             res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
 165                 res->domains = RADEON_DOMAIN_VRAM;
 166                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 167                          RADEON_FLAG_GTT_WC;
 168         }
 169
 170         /* Displayable and shareable surfaces are not suballocated. */
 171         if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 172                 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 173         else
 174                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 175
 176         if (sscreen->debug_flags & DBG(NO_WC))
 177                 res->flags &= ~RADEON_FLAG_GTT_WC;
 178
 179         if (res->b.b.flags & SI_RESOURCE_FLAG_READ_ONLY)
 180                 res->flags |= RADEON_FLAG_READ_ONLY;
 181
 182         if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
 183                 res->flags |= RADEON_FLAG_32BIT;
 184
 185         /* Set expected VRAM and GART usage for the buffer. */
 186         res->vram_usage = 0;
 187         res->gart_usage = 0;
 188         res->max_forced_staging_uploads = 0;
 189         res->b.max_forced_staging_uploads = 0;
 190
 191         if (res->domains & RADEON_DOMAIN_VRAM) {
 192                 res->vram_usage = size;
 193
 194                 res->max_forced_staging_uploads =
 195                 res->b.max_forced_staging_uploads =
 196                         sscreen->info.has_dedicated_vram &&
 197                         size >= sscreen->info.vram_vis_size / 4 ? 1 : 0;
 198         } else if (res->domains & RADEON_DOMAIN_GTT) {
 199                 res->gart_usage = size;
 200         }
 201 }
 202
 203 bool si_alloc_resource(struct si_screen *sscreen,
 204                        struct r600_resource *res)
 205 {
 206         struct pb_buffer *old_buf, *new_buf;
 207
 208         /* Allocate a new resource. */
 209         new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size,
 210                                              res->bo_alignment,
 211                                              res->domains, res->flags);
 212         if (!new_buf) {
 213                 return false;
 214         }
 215
 216         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 217          * NULL. This should prevent crashes with multiple contexts using
 218          * the same buffer where one of the contexts invalidates it while
 219          * the others are using it. */
 220         old_buf = res->buf;
 221         res->buf = new_buf; /* should be atomic */
 222         res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
 223
 224         if (res->flags & RADEON_FLAG_32BIT) {
 225                 uint64_t start = res->gpu_address;
 226                 uint64_t last = start + res->bo_size - 1;
 227                 (void)start;
 228                 (void)last;
 229
 230                 assert((start >> 32) == sscreen->info.address32_hi);
 231                 assert((last >> 32) == sscreen->info.address32_hi);
 232         }
 233
 234         pb_reference(&old_buf, NULL);
 235
 236         util_range_set_empty(&res->valid_buffer_range);
 237         res->TC_L2_dirty = false;
 238
 239         /* Print debug information. */
 240         if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
 241                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 242                         res->gpu_address, res->gpu_address + res->buf->size,
 243                         res->buf->size);
 244         }
 245         return true;
 246 }
 247
 248 static void si_buffer_destroy(struct pipe_screen *screen,
 249                               struct pipe_resource *buf)
 250 {
 251         struct r600_resource *rbuffer = r600_resource(buf);
 252
 253         threaded_resource_deinit(buf);
 254         util_range_destroy(&rbuffer->valid_buffer_range);
 255         pb_reference(&rbuffer->buf, NULL);
 256         FREE(rbuffer);
 257 }
 258
 259 /* Reallocate the buffer a update all resource bindings where the buffer is
 260  * bound.
 261  *
 262  * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
 263  * idle by discarding its contents.
 264  */
 265 static bool
 266 si_invalidate_buffer(struct si_context *sctx,
 267                      struct r600_resource *rbuffer)
 268 {
 269         /* Shared buffers can't be reallocated. */
 270         if (rbuffer->b.is_shared)
 271                 return false;
 272
 273         /* Sparse buffers can't be reallocated. */
 274         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 275                 return false;
 276
 277         /* In AMD_pinned_memory, the user pointer association only gets
 278          * broken when the buffer is explicitly re-allocated.
 279          */
 280         if (rbuffer->b.is_user_ptr)
 281                 return false;
 282
 283         /* Check if mapping this buffer would cause waiting for the GPU. */
 284         if (si_rings_is_buffer_referenced(sctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 285             !sctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 286                 uint64_t old_va = rbuffer->gpu_address;
 287
 288                 /* Reallocate the buffer in the same pipe_resource. */
 289                 si_alloc_resource(sctx->screen, rbuffer);
 290                 si_rebind_buffer(sctx, &rbuffer->b.b, old_va);
 291         } else {
 292                 util_range_set_empty(&rbuffer->valid_buffer_range);
 293         }
 294
 295         return true;
 296 }
 297
 298 /* Replace the storage of dst with src. */
 299 void si_replace_buffer_storage(struct pipe_context *ctx,
 300                                  struct pipe_resource *dst,
 301                                  struct pipe_resource *src)
 302 {
 303         struct si_context *sctx = (struct si_context*)ctx;
 304         struct r600_resource *rdst = r600_resource(dst);
 305         struct r600_resource *rsrc = r600_resource(src);
 306         uint64_t old_gpu_address = rdst->gpu_address;
 307
 308         pb_reference(&rdst->buf, rsrc->buf);
 309         rdst->gpu_address = rsrc->gpu_address;
 310         rdst->b.b.bind = rsrc->b.b.bind;
 311         rdst->b.max_forced_staging_uploads = rsrc->b.max_forced_staging_uploads;
 312         rdst->max_forced_staging_uploads = rsrc->max_forced_staging_uploads;
 313         rdst->flags = rsrc->flags;
 314
 315         assert(rdst->vram_usage == rsrc->vram_usage);
 316         assert(rdst->gart_usage == rsrc->gart_usage);
 317         assert(rdst->bo_size == rsrc->bo_size);
 318         assert(rdst->bo_alignment == rsrc->bo_alignment);
 319         assert(rdst->domains == rsrc->domains);
 320
 321         si_rebind_buffer(sctx, dst, old_gpu_address);
 322 }
 323
 324 static void si_invalidate_resource(struct pipe_context *ctx,
 325                                    struct pipe_resource *resource)
 326 {
 327         struct si_context *sctx = (struct si_context*)ctx;
 328         struct r600_resource *rbuffer = r600_resource(resource);
 329
 330         /* We currently only do anyting here for buffers */
 331         if (resource->target == PIPE_BUFFER)
 332                 (void)si_invalidate_buffer(sctx, rbuffer);
 333 }
 334
 335 static void *si_buffer_get_transfer(struct pipe_context *ctx,
 336                                     struct pipe_resource *resource,
 337                                     unsigned usage,
 338                                     const struct pipe_box *box,
 339                                     struct pipe_transfer **ptransfer,
 340                                     void *data, struct r600_resource *staging,
 341                                     unsigned offset)
 342 {
 343         struct si_context *sctx = (struct si_context*)ctx;
 344         struct si_transfer *transfer;
 345
 346         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 347                 transfer = slab_alloc(&sctx->pool_transfers_unsync);
 348         else
 349                 transfer = slab_alloc(&sctx->pool_transfers);
 350
 351         transfer->b.b.resource = NULL;
 352         pipe_resource_reference(&transfer->b.b.resource, resource);
 353         transfer->b.b.level = 0;
 354         transfer->b.b.usage = usage;
 355         transfer->b.b.box = *box;
 356         transfer->b.b.stride = 0;
 357         transfer->b.b.layer_stride = 0;
 358         transfer->b.staging = NULL;
 359         transfer->offset = offset;
 360         transfer->staging = staging;
 361         *ptransfer = &transfer->b.b;
 362         return data;
 363 }
 364
 365 static void *si_buffer_transfer_map(struct pipe_context *ctx,
 366                                     struct pipe_resource *resource,
 367                                     unsigned level,
 368                                     unsigned usage,
 369                                     const struct pipe_box *box,
 370                                     struct pipe_transfer **ptransfer)
 371 {
 372         struct si_context *sctx = (struct si_context*)ctx;
 373         struct r600_resource *rbuffer = r600_resource(resource);
 374         uint8_t *data;
 375
 376         assert(box->x + box->width <= resource->width0);
 377
 378         /* From GL_AMD_pinned_memory issues:
 379          *
 380          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 381          *        same system address which was specified at creation time?
 382          *
 383          *        RESOLVED: NO. The GL implementation might return a different
 384          *        virtual mapping of that memory, although the same physical
 385          *        page will be used.
 386          *
 387          * So don't ever use staging buffers.
 388          */
 389         if (rbuffer->b.is_user_ptr)
 390                 usage |= PIPE_TRANSFER_PERSISTENT;
 391
 392         /* See if the buffer range being mapped has never been initialized,
 393          * in which case it can be mapped unsynchronized. */
 394         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 395                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 396             usage & PIPE_TRANSFER_WRITE &&
 397             !rbuffer->b.is_shared &&
 398             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 399                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 400         }
 401
 402         /* If discarding the entire range, discard the whole resource instead. */
 403         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 404             box->x == 0 && box->width == resource->width0) {
 405                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 406         }
 407
 408         /* If a buffer in VRAM is too large and the range is discarded, don't
 409          * map it directly. This makes sure that the buffer stays in VRAM.
 410          */
 411         bool force_discard_range = false;
 412         if (usage & (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 413                      PIPE_TRANSFER_DISCARD_RANGE) &&
 414             !(usage & PIPE_TRANSFER_PERSISTENT) &&
 415             /* Try not to decrement the counter if it's not positive. Still racy,
 416              * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
 417             rbuffer->max_forced_staging_uploads > 0 &&
 418             p_atomic_dec_return(&rbuffer->max_forced_staging_uploads) >= 0) {
 419                 usage &= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 420                            PIPE_TRANSFER_UNSYNCHRONIZED);
 421                 usage |= PIPE_TRANSFER_DISCARD_RANGE;
 422                 force_discard_range = true;
 423         }
 424
 425         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 426             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 427                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 428                 assert(usage & PIPE_TRANSFER_WRITE);
 429
 430                 if (si_invalidate_buffer(sctx, rbuffer)) {
 431                         /* At this point, the buffer is always idle. */
 432                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 433                 } else {
 434                         /* Fall back to a temporary buffer. */
 435                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 436                 }
 437         }
 438
 439         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 440             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 441                          PIPE_TRANSFER_PERSISTENT))) ||
 442              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 443                 assert(usage & PIPE_TRANSFER_WRITE);
 444
 445                 /* Check if mapping this buffer would cause waiting for the GPU.
 446                  */
 447                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 448                     force_discard_range ||
 449                     si_rings_is_buffer_referenced(sctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 450                     !sctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 451                         /* Do a wait-free write-only transfer using a temporary buffer. */
 452                         unsigned offset;
 453                         struct r600_resource *staging = NULL;
 454
 455                         u_upload_alloc(ctx->stream_uploader, 0,
 456                                        box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT),
 457                                        sctx->screen->info.tcc_cache_line_size,
 458                                        &offset, (struct pipe_resource**)&staging,
 459                                        (void**)&data);
 460
 461                         if (staging) {
 462                                 data += box->x % SI_MAP_BUFFER_ALIGNMENT;
 463                                 return si_buffer_get_transfer(ctx, resource, usage, box,
 464                                                                 ptransfer, data, staging, offset);
 465                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 466                                 return NULL;
 467                         }
 468                 } else {
 469                         /* At this point, the buffer is always idle (we checked it above). */
 470                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 471                 }
 472         }
 473         /* Use a staging buffer in cached GTT for reads. */
 474         else if (((usage & PIPE_TRANSFER_READ) &&
 475                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 476                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 477                    rbuffer->flags & RADEON_FLAG_GTT_WC)) ||
 478                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 479                 struct r600_resource *staging;
 480
 481                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 482                 staging = r600_resource(pipe_buffer_create(
 483                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 484                                 box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT)));
 485                 if (staging) {
 486                         /* Copy the VRAM buffer to the staging buffer. */
 487                         sctx->dma_copy(ctx, &staging->b.b, 0,
 488                                        box->x % SI_MAP_BUFFER_ALIGNMENT,
 489                                        0, 0, resource, 0, box);
 490
 491                         data = si_buffer_map_sync_with_rings(sctx, staging,
 492                                                              usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 493                         if (!data) {
 494                                 r600_resource_reference(&staging, NULL);
 495                                 return NULL;
 496                         }
 497                         data += box->x % SI_MAP_BUFFER_ALIGNMENT;
 498
 499                         return si_buffer_get_transfer(ctx, resource, usage, box,
 500                                                         ptransfer, data, staging, 0);
 501                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 502                         return NULL;
 503                 }
 504         }
 505
 506         data = si_buffer_map_sync_with_rings(sctx, rbuffer, usage);
 507         if (!data) {
 508                 return NULL;
 509         }
 510         data += box->x;
 511
 512         return si_buffer_get_transfer(ctx, resource, usage, box,
 513                                         ptransfer, data, NULL, 0);
 514 }
 515
 516 static void si_buffer_do_flush_region(struct pipe_context *ctx,
 517                                       struct pipe_transfer *transfer,
 518                                       const struct pipe_box *box)
 519 {
 520         struct si_transfer *stransfer = (struct si_transfer*)transfer;
 521         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 522
 523         if (stransfer->staging) {
 524                 /* Copy the staging buffer into the original one. */
 525                 si_copy_buffer((struct si_context*)ctx, transfer->resource,
 526                                &stransfer->staging->b.b, box->x,
 527                                stransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT,
 528                                box->width);
 529         }
 530
 531         util_range_add(&rbuffer->valid_buffer_range, box->x,
 532                        box->x + box->width);
 533 }
 534
 535 static void si_buffer_flush_region(struct pipe_context *ctx,
 536                                    struct pipe_transfer *transfer,
 537                                    const struct pipe_box *rel_box)
 538 {
 539         unsigned required_usage = PIPE_TRANSFER_WRITE |
 540                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 541
 542         if ((transfer->usage & required_usage) == required_usage) {
 543                 struct pipe_box box;
 544
 545                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 546                 si_buffer_do_flush_region(ctx, transfer, &box);
 547         }
 548 }
 549
 550 static void si_buffer_transfer_unmap(struct pipe_context *ctx,
 551                                      struct pipe_transfer *transfer)
 552 {
 553         struct si_context *sctx = (struct si_context*)ctx;
 554         struct si_transfer *stransfer = (struct si_transfer*)transfer;
 555
 556         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 557             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 558                 si_buffer_do_flush_region(ctx, transfer, &transfer->box);
 559
 560         r600_resource_reference(&stransfer->staging, NULL);
 561         assert(stransfer->b.staging == NULL); /* for threaded context only */
 562         pipe_resource_reference(&transfer->resource, NULL);
 563
 564         /* Don't use pool_transfers_unsync. We are always in the driver
 565          * thread. */
 566         slab_free(&sctx->pool_transfers, transfer);
 567 }
 568
 569 static void si_buffer_subdata(struct pipe_context *ctx,
 570                               struct pipe_resource *buffer,
 571                               unsigned usage, unsigned offset,
 572                               unsigned size, const void *data)
 573 {
 574         struct pipe_transfer *transfer = NULL;
 575         struct pipe_box box;
 576         uint8_t *map = NULL;
 577
 578         u_box_1d(offset, size, &box);
 579         map = si_buffer_transfer_map(ctx, buffer, 0,
 580                                        PIPE_TRANSFER_WRITE |
 581                                        PIPE_TRANSFER_DISCARD_RANGE |
 582                                        usage,
 583                                        &box, &transfer);
 584         if (!map)
 585                 return;
 586
 587         memcpy(map, data, size);
 588         si_buffer_transfer_unmap(ctx, transfer);
 589 }
 590
 591 static const struct u_resource_vtbl si_buffer_vtbl =
 592 {
 593         NULL,                           /* get_handle */
 594         si_buffer_destroy,              /* resource_destroy */
 595         si_buffer_transfer_map, /* transfer_map */
 596         si_buffer_flush_region, /* transfer_flush_region */
 597         si_buffer_transfer_unmap,       /* transfer_unmap */
 598 };
 599
 600 static struct r600_resource *
 601 si_alloc_buffer_struct(struct pipe_screen *screen,
 602                        const struct pipe_resource *templ)
 603 {
 604         struct r600_resource *rbuffer;
 605
 606         rbuffer = MALLOC_STRUCT(r600_resource);
 607
 608         rbuffer->b.b = *templ;
 609         rbuffer->b.b.next = NULL;
 610         pipe_reference_init(&rbuffer->b.b.reference, 1);
 611         rbuffer->b.b.screen = screen;
 612
 613         rbuffer->b.vtbl = &si_buffer_vtbl;
 614         threaded_resource_init(&rbuffer->b.b);
 615
 616         rbuffer->buf = NULL;
 617         rbuffer->bind_history = 0;
 618         rbuffer->TC_L2_dirty = false;
 619         util_range_init(&rbuffer->valid_buffer_range);
 620         return rbuffer;
 621 }
 622
 623 static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 624                                               const struct pipe_resource *templ,
 625                                               unsigned alignment)
 626 {
 627         struct si_screen *sscreen = (struct si_screen*)screen;
 628         struct r600_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
 629
 630         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 631                 rbuffer->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
 632
 633         si_init_resource_fields(sscreen, rbuffer, templ->width0, alignment);
 634
 635         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 636                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 637
 638         if (!si_alloc_resource(sscreen, rbuffer)) {
 639                 FREE(rbuffer);
 640                 return NULL;
 641         }
 642         return &rbuffer->b.b;
 643 }
 644
 645 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
 646                                                  unsigned flags, unsigned usage,
 647                                                  unsigned size, unsigned alignment)
 648 {
 649         struct pipe_resource buffer;
 650
 651         memset(&buffer, 0, sizeof buffer);
 652         buffer.target = PIPE_BUFFER;
 653         buffer.format = PIPE_FORMAT_R8_UNORM;
 654         buffer.bind = 0;
 655         buffer.usage = usage;
 656         buffer.flags = flags;
 657         buffer.width0 = size;
 658         buffer.height0 = 1;
 659         buffer.depth0 = 1;
 660         buffer.array_size = 1;
 661         return si_buffer_create(screen, &buffer, alignment);
 662 }
 663
 664 struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 665                                                unsigned flags, unsigned usage,
 666                                                unsigned size, unsigned alignment)
 667 {
 668         return r600_resource(pipe_aligned_buffer_create(screen, flags, usage,
 669                                                         size, alignment));
 670 }
 671
 672 static struct pipe_resource *
 673 si_buffer_from_user_memory(struct pipe_screen *screen,
 674                            const struct pipe_resource *templ,
 675                            void *user_memory)
 676 {
 677         struct si_screen *sscreen = (struct si_screen*)screen;
 678         struct radeon_winsys *ws = sscreen->ws;
 679         struct r600_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
 680
 681         rbuffer->domains = RADEON_DOMAIN_GTT;
 682         rbuffer->flags = 0;
 683         rbuffer->b.is_user_ptr = true;
 684         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 685         util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 686
 687         /* Convert a user pointer to a buffer. */
 688         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 689         if (!rbuffer->buf) {
 690                 FREE(rbuffer);
 691                 return NULL;
 692         }
 693
 694         rbuffer->gpu_address = ws->buffer_get_virtual_address(rbuffer->buf);
 695         rbuffer->vram_usage = 0;
 696         rbuffer->gart_usage = templ->width0;
 697
 698         return &rbuffer->b.b;
 699 }
 700
 701 static struct pipe_resource *si_resource_create(struct pipe_screen *screen,
 702                                                 const struct pipe_resource *templ)
 703 {
 704         if (templ->target == PIPE_BUFFER) {
 705                 return si_buffer_create(screen, templ, 256);
 706         } else {
 707                 return si_texture_create(screen, templ);
 708         }
 709 }
 710
 711 static bool si_resource_commit(struct pipe_context *pctx,
 712                                struct pipe_resource *resource,
 713                                unsigned level, struct pipe_box *box,
 714                                bool commit)
 715 {
 716         struct si_context *ctx = (struct si_context *)pctx;
 717         struct r600_resource *res = r600_resource(resource);
 718
 719         /*
 720          * Since buffer commitment changes cannot be pipelined, we need to
 721          * (a) flush any pending commands that refer to the buffer we're about
 722          *     to change, and
 723          * (b) wait for threaded submit to finish, including those that were
 724          *     triggered by some other, earlier operation.
 725          */
 726         if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
 727             ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs,
 728                                                res->buf, RADEON_USAGE_READWRITE)) {
 729                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 730         }
 731         if (radeon_emitted(ctx->dma_cs, 0) &&
 732             ctx->ws->cs_is_buffer_referenced(ctx->dma_cs,
 733                                                res->buf, RADEON_USAGE_READWRITE)) {
 734                 si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
 735         }
 736
 737         ctx->ws->cs_sync_flush(ctx->dma_cs);
 738         ctx->ws->cs_sync_flush(ctx->gfx_cs);
 739
 740         assert(resource->target == PIPE_BUFFER);
 741
 742         return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
 743 }
 744
 745 void si_init_screen_buffer_functions(struct si_screen *sscreen)
 746 {
 747         sscreen->b.resource_create = si_resource_create;
 748         sscreen->b.resource_destroy = u_resource_destroy_vtbl;
 749         sscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
 750 }
 751
 752 void si_init_buffer_functions(struct si_context *sctx)
 753 {
 754         sctx->b.invalidate_resource = si_invalidate_resource;
 755         sctx->b.transfer_map = u_transfer_map_vtbl;
 756         sctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
 757         sctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 758         sctx->b.texture_subdata = u_default_texture_subdata;
 759         sctx->b.buffer_subdata = si_buffer_subdata;
 760         sctx->b.resource_commit = si_resource_commit;
 761 }