src/gallium/drivers/radeonsi/si_buffer.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "radeonsi/si_pipe.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "util/u_transfer.h"
  29 #include <inttypes.h>
  30 #include <stdio.h>
  31
  32 bool si_rings_is_buffer_referenced(struct si_context *sctx,
  33                                    struct pb_buffer *buf,
  34                                    enum radeon_bo_usage usage)
  35 {
  36         if (sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs, buf, usage)) {
  37                 return true;
  38         }
  39         if (radeon_emitted(sctx->dma_cs, 0) &&
  40             sctx->ws->cs_is_buffer_referenced(sctx->dma_cs, buf, usage)) {
  41                 return true;
  42         }
  43         return false;
  44 }
  45
  46 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
  47                                     struct si_resource *resource,
  48                                     unsigned usage)
  49 {
  50         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  51         bool busy = false;
  52
  53         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  54
  55         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  56                 return sctx->ws->buffer_map(resource->buf, NULL, usage);
  57         }
  58
  59         if (!(usage & PIPE_TRANSFER_WRITE)) {
  60                 /* have to wait for the last write */
  61                 rusage = RADEON_USAGE_WRITE;
  62         }
  63
  64         if (radeon_emitted(sctx->gfx_cs, sctx->initial_gfx_cs_size) &&
  65             sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs,
  66                                                 resource->buf, rusage)) {
  67                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  68                         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  69                         return NULL;
  70                 } else {
  71                         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  72                         busy = true;
  73                 }
  74         }
  75         if (radeon_emitted(sctx->dma_cs, 0) &&
  76             sctx->ws->cs_is_buffer_referenced(sctx->dma_cs,
  77                                                 resource->buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         si_flush_dma_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         si_flush_dma_cs(sctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || !sctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         sctx->ws->cs_sync_flush(sctx->gfx_cs);
  94                         if (sctx->dma_cs)
  95                                 sctx->ws->cs_sync_flush(sctx->dma_cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return sctx->ws->buffer_map(resource->buf, NULL, usage);
 101 }
 102
 103 void si_init_resource_fields(struct si_screen *sscreen,
 104                              struct si_resource *res,
 105                              uint64_t size, unsigned alignment)
 106 {
 107         struct si_texture *tex = (struct si_texture*)res;
 108
 109         res->bo_size = size;
 110         res->bo_alignment = alignment;
 111         res->flags = 0;
 112         res->texture_handle_allocated = false;
 113         res->image_handle_allocated = false;
 114
 115         switch (res->b.b.usage) {
 116         case PIPE_USAGE_STREAM:
 117                 res->flags = RADEON_FLAG_GTT_WC;
 118                 /* fall through */
 119         case PIPE_USAGE_STAGING:
 120                 /* Transfers are likely to occur more often with these
 121                  * resources. */
 122                 res->domains = RADEON_DOMAIN_GTT;
 123                 break;
 124         case PIPE_USAGE_DYNAMIC:
 125                 /* Older kernels didn't always flush the HDP cache before
 126                  * CS execution
 127                  */
 128                 if (!sscreen->info.kernel_flushes_hdp_before_ib) {
 129                         res->domains = RADEON_DOMAIN_GTT;
 130                         res->flags |= RADEON_FLAG_GTT_WC;
 131                         break;
 132                 }
 133                 /* fall through */
 134         case PIPE_USAGE_DEFAULT:
 135         case PIPE_USAGE_IMMUTABLE:
 136         default:
 137                 /* Not listing GTT here improves performance in some
 138                  * apps. */
 139                 res->domains = RADEON_DOMAIN_VRAM;
 140                 res->flags |= RADEON_FLAG_GTT_WC;
 141                 break;
 142         }
 143
 144         if (res->b.b.target == PIPE_BUFFER &&
 145             res->b.b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
 146                 /* Use GTT for all persistent mappings with older
 147                  * kernels, because they didn't always flush the HDP
 148                  * cache before CS execution.
 149                  *
 150                  * Write-combined CPU mappings are fine, the kernel
 151                  * ensures all CPU writes finish before the GPU
 152                  * executes a command stream.
 153                  *
 154                  * radeon doesn't have good BO move throttling, so put all
 155                  * persistent buffers into GTT to prevent VRAM CPU page faults.
 156                  */
 157                 if (!sscreen->info.kernel_flushes_hdp_before_ib ||
 158                     sscreen->info.drm_major == 2)
 159                         res->domains = RADEON_DOMAIN_GTT;
 160         }
 161
 162         /* Tiled textures are unmappable. Always put them in VRAM. */
 163         if ((res->b.b.target != PIPE_BUFFER && !tex->surface.is_linear) ||
 164             res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
 165                 res->domains = RADEON_DOMAIN_VRAM;
 166                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 167                          RADEON_FLAG_GTT_WC;
 168         }
 169
 170         /* Displayable and shareable surfaces are not suballocated. */
 171         if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 172                 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 173         else
 174                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 175
 176         if (sscreen->debug_flags & DBG(NO_WC))
 177                 res->flags &= ~RADEON_FLAG_GTT_WC;
 178
 179         if (res->b.b.flags & SI_RESOURCE_FLAG_READ_ONLY)
 180                 res->flags |= RADEON_FLAG_READ_ONLY;
 181
 182         if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
 183                 res->flags |= RADEON_FLAG_32BIT;
 184
 185         /* Set expected VRAM and GART usage for the buffer. */
 186         res->vram_usage = 0;
 187         res->gart_usage = 0;
 188         res->max_forced_staging_uploads = 0;
 189         res->b.max_forced_staging_uploads = 0;
 190
 191         if (res->domains & RADEON_DOMAIN_VRAM) {
 192                 res->vram_usage = size;
 193
 194                 res->max_forced_staging_uploads =
 195                 res->b.max_forced_staging_uploads =
 196                         sscreen->info.has_dedicated_vram &&
 197                         size >= sscreen->info.vram_vis_size / 4 ? 1 : 0;
 198         } else if (res->domains & RADEON_DOMAIN_GTT) {
 199                 res->gart_usage = size;
 200         }
 201 }
 202
 203 bool si_alloc_resource(struct si_screen *sscreen,
 204                        struct si_resource *res)
 205 {
 206         struct pb_buffer *old_buf, *new_buf;
 207
 208         /* Allocate a new resource. */
 209         new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size,
 210                                              res->bo_alignment,
 211                                              res->domains, res->flags);
 212         if (!new_buf) {
 213                 return false;
 214         }
 215
 216         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 217          * NULL. This should prevent crashes with multiple contexts using
 218          * the same buffer where one of the contexts invalidates it while
 219          * the others are using it. */
 220         old_buf = res->buf;
 221         res->buf = new_buf; /* should be atomic */
 222         res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
 223
 224         if (res->flags & RADEON_FLAG_32BIT) {
 225                 uint64_t start = res->gpu_address;
 226                 uint64_t last = start + res->bo_size - 1;
 227                 (void)start;
 228                 (void)last;
 229
 230                 assert((start >> 32) == sscreen->info.address32_hi);
 231                 assert((last >> 32) == sscreen->info.address32_hi);
 232         }
 233
 234         pb_reference(&old_buf, NULL);
 235
 236         util_range_set_empty(&res->valid_buffer_range);
 237         res->TC_L2_dirty = false;
 238
 239         /* Print debug information. */
 240         if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
 241                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 242                         res->gpu_address, res->gpu_address + res->buf->size,
 243                         res->buf->size);
 244         }
 245
 246         if (res->b.b.flags & SI_RESOURCE_FLAG_CLEAR)
 247                 si_screen_clear_buffer(sscreen, &res->b.b, 0, res->bo_size, 0);
 248
 249         return true;
 250 }
 251
 252 static void si_buffer_destroy(struct pipe_screen *screen,
 253                               struct pipe_resource *buf)
 254 {
 255         struct si_resource *buffer = si_resource(buf);
 256
 257         threaded_resource_deinit(buf);
 258         util_range_destroy(&buffer->valid_buffer_range);
 259         pb_reference(&buffer->buf, NULL);
 260         FREE(buffer);
 261 }
 262
 263 /* Reallocate the buffer a update all resource bindings where the buffer is
 264  * bound.
 265  *
 266  * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
 267  * idle by discarding its contents.
 268  */
 269 static bool
 270 si_invalidate_buffer(struct si_context *sctx,
 271                      struct si_resource *buf)
 272 {
 273         /* Shared buffers can't be reallocated. */
 274         if (buf->b.is_shared)
 275                 return false;
 276
 277         /* Sparse buffers can't be reallocated. */
 278         if (buf->flags & RADEON_FLAG_SPARSE)
 279                 return false;
 280
 281         /* In AMD_pinned_memory, the user pointer association only gets
 282          * broken when the buffer is explicitly re-allocated.
 283          */
 284         if (buf->b.is_user_ptr)
 285                 return false;
 286
 287         /* Check if mapping this buffer would cause waiting for the GPU. */
 288         if (si_rings_is_buffer_referenced(sctx, buf->buf, RADEON_USAGE_READWRITE) ||
 289             !sctx->ws->buffer_wait(buf->buf, 0, RADEON_USAGE_READWRITE)) {
 290                 uint64_t old_va = buf->gpu_address;
 291
 292                 /* Reallocate the buffer in the same pipe_resource. */
 293                 si_alloc_resource(sctx->screen, buf);
 294                 si_rebind_buffer(sctx, &buf->b.b, old_va);
 295         } else {
 296                 util_range_set_empty(&buf->valid_buffer_range);
 297         }
 298
 299         return true;
 300 }
 301
 302 /* Replace the storage of dst with src. */
 303 void si_replace_buffer_storage(struct pipe_context *ctx,
 304                                  struct pipe_resource *dst,
 305                                  struct pipe_resource *src)
 306 {
 307         struct si_context *sctx = (struct si_context*)ctx;
 308         struct si_resource *sdst = si_resource(dst);
 309         struct si_resource *ssrc = si_resource(src);
 310         uint64_t old_gpu_address = sdst->gpu_address;
 311
 312         pb_reference(&sdst->buf, ssrc->buf);
 313         sdst->gpu_address = ssrc->gpu_address;
 314         sdst->b.b.bind = ssrc->b.b.bind;
 315         sdst->b.max_forced_staging_uploads = ssrc->b.max_forced_staging_uploads;
 316         sdst->max_forced_staging_uploads = ssrc->max_forced_staging_uploads;
 317         sdst->flags = ssrc->flags;
 318
 319         assert(sdst->vram_usage == ssrc->vram_usage);
 320         assert(sdst->gart_usage == ssrc->gart_usage);
 321         assert(sdst->bo_size == ssrc->bo_size);
 322         assert(sdst->bo_alignment == ssrc->bo_alignment);
 323         assert(sdst->domains == ssrc->domains);
 324
 325         si_rebind_buffer(sctx, dst, old_gpu_address);
 326 }
 327
 328 static void si_invalidate_resource(struct pipe_context *ctx,
 329                                    struct pipe_resource *resource)
 330 {
 331         struct si_context *sctx = (struct si_context*)ctx;
 332         struct si_resource *buf = si_resource(resource);
 333
 334         /* We currently only do anyting here for buffers */
 335         if (resource->target == PIPE_BUFFER)
 336                 (void)si_invalidate_buffer(sctx, buf);
 337 }
 338
 339 static void *si_buffer_get_transfer(struct pipe_context *ctx,
 340                                     struct pipe_resource *resource,
 341                                     unsigned usage,
 342                                     const struct pipe_box *box,
 343                                     struct pipe_transfer **ptransfer,
 344                                     void *data, struct si_resource *staging,
 345                                     unsigned offset)
 346 {
 347         struct si_context *sctx = (struct si_context*)ctx;
 348         struct si_transfer *transfer;
 349
 350         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 351                 transfer = slab_alloc(&sctx->pool_transfers_unsync);
 352         else
 353                 transfer = slab_alloc(&sctx->pool_transfers);
 354
 355         transfer->b.b.resource = NULL;
 356         pipe_resource_reference(&transfer->b.b.resource, resource);
 357         transfer->b.b.level = 0;
 358         transfer->b.b.usage = usage;
 359         transfer->b.b.box = *box;
 360         transfer->b.b.stride = 0;
 361         transfer->b.b.layer_stride = 0;
 362         transfer->b.staging = NULL;
 363         transfer->offset = offset;
 364         transfer->staging = staging;
 365         *ptransfer = &transfer->b.b;
 366         return data;
 367 }
 368
 369 static void *si_buffer_transfer_map(struct pipe_context *ctx,
 370                                     struct pipe_resource *resource,
 371                                     unsigned level,
 372                                     unsigned usage,
 373                                     const struct pipe_box *box,
 374                                     struct pipe_transfer **ptransfer)
 375 {
 376         struct si_context *sctx = (struct si_context*)ctx;
 377         struct si_resource *buf = si_resource(resource);
 378         uint8_t *data;
 379
 380         assert(box->x + box->width <= resource->width0);
 381
 382         /* From GL_AMD_pinned_memory issues:
 383          *
 384          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 385          *        same system address which was specified at creation time?
 386          *
 387          *        RESOLVED: NO. The GL implementation might return a different
 388          *        virtual mapping of that memory, although the same physical
 389          *        page will be used.
 390          *
 391          * So don't ever use staging buffers.
 392          */
 393         if (buf->b.is_user_ptr)
 394                 usage |= PIPE_TRANSFER_PERSISTENT;
 395
 396         /* See if the buffer range being mapped has never been initialized,
 397          * in which case it can be mapped unsynchronized. */
 398         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 399                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 400             usage & PIPE_TRANSFER_WRITE &&
 401             !buf->b.is_shared &&
 402             !util_ranges_intersect(&buf->valid_buffer_range, box->x, box->x + box->width)) {
 403                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 404         }
 405
 406         /* If discarding the entire range, discard the whole resource instead. */
 407         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 408             box->x == 0 && box->width == resource->width0) {
 409                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 410         }
 411
 412         /* If a buffer in VRAM is too large and the range is discarded, don't
 413          * map it directly. This makes sure that the buffer stays in VRAM.
 414          */
 415         bool force_discard_range = false;
 416         if (usage & (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 417                      PIPE_TRANSFER_DISCARD_RANGE) &&
 418             !(usage & PIPE_TRANSFER_PERSISTENT) &&
 419             /* Try not to decrement the counter if it's not positive. Still racy,
 420              * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
 421             buf->max_forced_staging_uploads > 0 &&
 422             p_atomic_dec_return(&buf->max_forced_staging_uploads) >= 0) {
 423                 usage &= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 424                            PIPE_TRANSFER_UNSYNCHRONIZED);
 425                 usage |= PIPE_TRANSFER_DISCARD_RANGE;
 426                 force_discard_range = true;
 427         }
 428
 429         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 430             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 431                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 432                 assert(usage & PIPE_TRANSFER_WRITE);
 433
 434                 if (si_invalidate_buffer(sctx, buf)) {
 435                         /* At this point, the buffer is always idle. */
 436                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 437                 } else {
 438                         /* Fall back to a temporary buffer. */
 439                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 440                 }
 441         }
 442
 443         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 444             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 445                          PIPE_TRANSFER_PERSISTENT))) ||
 446              (buf->flags & RADEON_FLAG_SPARSE))) {
 447                 assert(usage & PIPE_TRANSFER_WRITE);
 448
 449                 /* Check if mapping this buffer would cause waiting for the GPU.
 450                  */
 451                 if (buf->flags & RADEON_FLAG_SPARSE ||
 452                     force_discard_range ||
 453                     si_rings_is_buffer_referenced(sctx, buf->buf, RADEON_USAGE_READWRITE) ||
 454                     !sctx->ws->buffer_wait(buf->buf, 0, RADEON_USAGE_READWRITE)) {
 455                         /* Do a wait-free write-only transfer using a temporary buffer. */
 456                         unsigned offset;
 457                         struct si_resource *staging = NULL;
 458
 459                         u_upload_alloc(ctx->stream_uploader, 0,
 460                                        box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT),
 461                                        sctx->screen->info.tcc_cache_line_size,
 462                                        &offset, (struct pipe_resource**)&staging,
 463                                        (void**)&data);
 464
 465                         if (staging) {
 466                                 data += box->x % SI_MAP_BUFFER_ALIGNMENT;
 467                                 return si_buffer_get_transfer(ctx, resource, usage, box,
 468                                                                 ptransfer, data, staging, offset);
 469                         } else if (buf->flags & RADEON_FLAG_SPARSE) {
 470                                 return NULL;
 471                         }
 472                 } else {
 473                         /* At this point, the buffer is always idle (we checked it above). */
 474                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 475                 }
 476         }
 477         /* Use a staging buffer in cached GTT for reads. */
 478         else if (((usage & PIPE_TRANSFER_READ) &&
 479                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 480                   (buf->domains & RADEON_DOMAIN_VRAM ||
 481                    buf->flags & RADEON_FLAG_GTT_WC)) ||
 482                  (buf->flags & RADEON_FLAG_SPARSE)) {
 483                 struct si_resource *staging;
 484
 485                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 486                 staging = si_resource(pipe_buffer_create(
 487                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 488                                 box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT)));
 489                 if (staging) {
 490                         /* Copy the VRAM buffer to the staging buffer. */
 491                         sctx->dma_copy(ctx, &staging->b.b, 0,
 492                                        box->x % SI_MAP_BUFFER_ALIGNMENT,
 493                                        0, 0, resource, 0, box);
 494
 495                         data = si_buffer_map_sync_with_rings(sctx, staging,
 496                                                              usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 497                         if (!data) {
 498                                 si_resource_reference(&staging, NULL);
 499                                 return NULL;
 500                         }
 501                         data += box->x % SI_MAP_BUFFER_ALIGNMENT;
 502
 503                         return si_buffer_get_transfer(ctx, resource, usage, box,
 504                                                         ptransfer, data, staging, 0);
 505                 } else if (buf->flags & RADEON_FLAG_SPARSE) {
 506                         return NULL;
 507                 }
 508         }
 509
 510         data = si_buffer_map_sync_with_rings(sctx, buf, usage);
 511         if (!data) {
 512                 return NULL;
 513         }
 514         data += box->x;
 515
 516         return si_buffer_get_transfer(ctx, resource, usage, box,
 517                                         ptransfer, data, NULL, 0);
 518 }
 519
 520 static void si_buffer_do_flush_region(struct pipe_context *ctx,
 521                                       struct pipe_transfer *transfer,
 522                                       const struct pipe_box *box)
 523 {
 524         struct si_transfer *stransfer = (struct si_transfer*)transfer;
 525         struct si_resource *buf = si_resource(transfer->resource);
 526
 527         if (stransfer->staging) {
 528                 unsigned src_offset = stransfer->offset +
 529                                       transfer->box.x % SI_MAP_BUFFER_ALIGNMENT +
 530                                       (box->x - transfer->box.x);
 531
 532                 /* Copy the staging buffer into the original one. */
 533                 si_copy_buffer((struct si_context*)ctx, transfer->resource,
 534                                &stransfer->staging->b.b, box->x, src_offset,
 535                                box->width);
 536         }
 537
 538         util_range_add(&buf->valid_buffer_range, box->x,
 539                        box->x + box->width);
 540 }
 541
 542 static void si_buffer_flush_region(struct pipe_context *ctx,
 543                                    struct pipe_transfer *transfer,
 544                                    const struct pipe_box *rel_box)
 545 {
 546         unsigned required_usage = PIPE_TRANSFER_WRITE |
 547                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 548
 549         if ((transfer->usage & required_usage) == required_usage) {
 550                 struct pipe_box box;
 551
 552                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 553                 si_buffer_do_flush_region(ctx, transfer, &box);
 554         }
 555 }
 556
 557 static void si_buffer_transfer_unmap(struct pipe_context *ctx,
 558                                      struct pipe_transfer *transfer)
 559 {
 560         struct si_context *sctx = (struct si_context*)ctx;
 561         struct si_transfer *stransfer = (struct si_transfer*)transfer;
 562
 563         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 564             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 565                 si_buffer_do_flush_region(ctx, transfer, &transfer->box);
 566
 567         si_resource_reference(&stransfer->staging, NULL);
 568         assert(stransfer->b.staging == NULL); /* for threaded context only */
 569         pipe_resource_reference(&transfer->resource, NULL);
 570
 571         /* Don't use pool_transfers_unsync. We are always in the driver
 572          * thread. */
 573         slab_free(&sctx->pool_transfers, transfer);
 574 }
 575
 576 static void si_buffer_subdata(struct pipe_context *ctx,
 577                               struct pipe_resource *buffer,
 578                               unsigned usage, unsigned offset,
 579                               unsigned size, const void *data)
 580 {
 581         struct pipe_transfer *transfer = NULL;
 582         struct pipe_box box;
 583         uint8_t *map = NULL;
 584
 585         u_box_1d(offset, size, &box);
 586         map = si_buffer_transfer_map(ctx, buffer, 0,
 587                                        PIPE_TRANSFER_WRITE |
 588                                        PIPE_TRANSFER_DISCARD_RANGE |
 589                                        usage,
 590                                        &box, &transfer);
 591         if (!map)
 592                 return;
 593
 594         memcpy(map, data, size);
 595         si_buffer_transfer_unmap(ctx, transfer);
 596 }
 597
 598 static const struct u_resource_vtbl si_buffer_vtbl =
 599 {
 600         NULL,                           /* get_handle */
 601         si_buffer_destroy,              /* resource_destroy */
 602         si_buffer_transfer_map, /* transfer_map */
 603         si_buffer_flush_region, /* transfer_flush_region */
 604         si_buffer_transfer_unmap,       /* transfer_unmap */
 605 };
 606
 607 static struct si_resource *
 608 si_alloc_buffer_struct(struct pipe_screen *screen,
 609                        const struct pipe_resource *templ)
 610 {
 611         struct si_resource *buf;
 612
 613         buf = MALLOC_STRUCT(si_resource);
 614
 615         buf->b.b = *templ;
 616         buf->b.b.next = NULL;
 617         pipe_reference_init(&buf->b.b.reference, 1);
 618         buf->b.b.screen = screen;
 619
 620         buf->b.vtbl = &si_buffer_vtbl;
 621         threaded_resource_init(&buf->b.b);
 622
 623         buf->buf = NULL;
 624         buf->bind_history = 0;
 625         buf->TC_L2_dirty = false;
 626         util_range_init(&buf->valid_buffer_range);
 627         return buf;
 628 }
 629
 630 static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 631                                               const struct pipe_resource *templ,
 632                                               unsigned alignment)
 633 {
 634         struct si_screen *sscreen = (struct si_screen*)screen;
 635         struct si_resource *buf = si_alloc_buffer_struct(screen, templ);
 636
 637         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 638                 buf->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
 639
 640         si_init_resource_fields(sscreen, buf, templ->width0, alignment);
 641
 642         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 643                 buf->flags |= RADEON_FLAG_SPARSE;
 644
 645         if (!si_alloc_resource(sscreen, buf)) {
 646                 FREE(buf);
 647                 return NULL;
 648         }
 649         return &buf->b.b;
 650 }
 651
 652 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
 653                                                  unsigned flags, unsigned usage,
 654                                                  unsigned size, unsigned alignment)
 655 {
 656         struct pipe_resource buffer;
 657
 658         memset(&buffer, 0, sizeof buffer);
 659         buffer.target = PIPE_BUFFER;
 660         buffer.format = PIPE_FORMAT_R8_UNORM;
 661         buffer.bind = 0;
 662         buffer.usage = usage;
 663         buffer.flags = flags;
 664         buffer.width0 = size;
 665         buffer.height0 = 1;
 666         buffer.depth0 = 1;
 667         buffer.array_size = 1;
 668         return si_buffer_create(screen, &buffer, alignment);
 669 }
 670
 671 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 672                                                unsigned flags, unsigned usage,
 673                                                unsigned size, unsigned alignment)
 674 {
 675         return si_resource(pipe_aligned_buffer_create(screen, flags, usage,
 676                                                         size, alignment));
 677 }
 678
 679 static struct pipe_resource *
 680 si_buffer_from_user_memory(struct pipe_screen *screen,
 681                            const struct pipe_resource *templ,
 682                            void *user_memory)
 683 {
 684         struct si_screen *sscreen = (struct si_screen*)screen;
 685         struct radeon_winsys *ws = sscreen->ws;
 686         struct si_resource *buf = si_alloc_buffer_struct(screen, templ);
 687
 688         buf->domains = RADEON_DOMAIN_GTT;
 689         buf->flags = 0;
 690         buf->b.is_user_ptr = true;
 691         util_range_add(&buf->valid_buffer_range, 0, templ->width0);
 692         util_range_add(&buf->b.valid_buffer_range, 0, templ->width0);
 693
 694         /* Convert a user pointer to a buffer. */
 695         buf->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 696         if (!buf->buf) {
 697                 FREE(buf);
 698                 return NULL;
 699         }
 700
 701         buf->gpu_address = ws->buffer_get_virtual_address(buf->buf);
 702         buf->vram_usage = 0;
 703         buf->gart_usage = templ->width0;
 704
 705         return &buf->b.b;
 706 }
 707
 708 static struct pipe_resource *si_resource_create(struct pipe_screen *screen,
 709                                                 const struct pipe_resource *templ)
 710 {
 711         if (templ->target == PIPE_BUFFER) {
 712                 return si_buffer_create(screen, templ, 256);
 713         } else {
 714                 return si_texture_create(screen, templ);
 715         }
 716 }
 717
 718 static bool si_resource_commit(struct pipe_context *pctx,
 719                                struct pipe_resource *resource,
 720                                unsigned level, struct pipe_box *box,
 721                                bool commit)
 722 {
 723         struct si_context *ctx = (struct si_context *)pctx;
 724         struct si_resource *res = si_resource(resource);
 725
 726         /*
 727          * Since buffer commitment changes cannot be pipelined, we need to
 728          * (a) flush any pending commands that refer to the buffer we're about
 729          *     to change, and
 730          * (b) wait for threaded submit to finish, including those that were
 731          *     triggered by some other, earlier operation.
 732          */
 733         if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
 734             ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs,
 735                                                res->buf, RADEON_USAGE_READWRITE)) {
 736                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 737         }
 738         if (radeon_emitted(ctx->dma_cs, 0) &&
 739             ctx->ws->cs_is_buffer_referenced(ctx->dma_cs,
 740                                                res->buf, RADEON_USAGE_READWRITE)) {
 741                 si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
 742         }
 743
 744         ctx->ws->cs_sync_flush(ctx->dma_cs);
 745         ctx->ws->cs_sync_flush(ctx->gfx_cs);
 746
 747         assert(resource->target == PIPE_BUFFER);
 748
 749         return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
 750 }
 751
 752 void si_init_screen_buffer_functions(struct si_screen *sscreen)
 753 {
 754         sscreen->b.resource_create = si_resource_create;
 755         sscreen->b.resource_destroy = u_resource_destroy_vtbl;
 756         sscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
 757 }
 758
 759 void si_init_buffer_functions(struct si_context *sctx)
 760 {
 761         sctx->b.invalidate_resource = si_invalidate_resource;
 762         sctx->b.transfer_map = u_transfer_map_vtbl;
 763         sctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
 764         sctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 765         sctx->b.texture_subdata = u_default_texture_subdata;
 766         sctx->b.buffer_subdata = si_buffer_subdata;
 767         sctx->b.resource_commit = si_resource_commit;
 768 }