src/gallium/drivers/radeonsi/si_buffer.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "radeonsi/si_pipe.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "util/u_transfer.h"
  29 #include <inttypes.h>
  30 #include <stdio.h>
  31
  32 bool si_rings_is_buffer_referenced(struct si_context *sctx,
  33                                    struct pb_buffer *buf,
  34                                    enum radeon_bo_usage usage)
  35 {
  36         if (sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs, buf, usage)) {
  37                 return true;
  38         }
  39         if (radeon_emitted(sctx->dma_cs, 0) &&
  40             sctx->ws->cs_is_buffer_referenced(sctx->dma_cs, buf, usage)) {
  41                 return true;
  42         }
  43         return false;
  44 }
  45
  46 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
  47                                     struct r600_resource *resource,
  48                                     unsigned usage)
  49 {
  50         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  51         bool busy = false;
  52
  53         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  54
  55         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  56                 return sctx->ws->buffer_map(resource->buf, NULL, usage);
  57         }
  58
  59         if (!(usage & PIPE_TRANSFER_WRITE)) {
  60                 /* have to wait for the last write */
  61                 rusage = RADEON_USAGE_WRITE;
  62         }
  63
  64         if (radeon_emitted(sctx->gfx_cs, sctx->initial_gfx_cs_size) &&
  65             sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs,
  66                                                 resource->buf, rusage)) {
  67                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  68                         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  69                         return NULL;
  70                 } else {
  71                         si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  72                         busy = true;
  73                 }
  74         }
  75         if (radeon_emitted(sctx->dma_cs, 0) &&
  76             sctx->ws->cs_is_buffer_referenced(sctx->dma_cs,
  77                                                 resource->buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         si_flush_dma_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         si_flush_dma_cs(sctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || !sctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         sctx->ws->cs_sync_flush(sctx->gfx_cs);
  94                         if (sctx->dma_cs)
  95                                 sctx->ws->cs_sync_flush(sctx->dma_cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return sctx->ws->buffer_map(resource->buf, NULL, usage);
 101 }
 102
 103 void si_init_resource_fields(struct si_screen *sscreen,
 104                              struct r600_resource *res,
 105                              uint64_t size, unsigned alignment)
 106 {
 107         struct r600_texture *rtex = (struct r600_texture*)res;
 108
 109         res->bo_size = size;
 110         res->bo_alignment = alignment;
 111         res->flags = 0;
 112         res->texture_handle_allocated = false;
 113         res->image_handle_allocated = false;
 114
 115         switch (res->b.b.usage) {
 116         case PIPE_USAGE_STREAM:
 117                 res->flags = RADEON_FLAG_GTT_WC;
 118                 /* fall through */
 119         case PIPE_USAGE_STAGING:
 120                 /* Transfers are likely to occur more often with these
 121                  * resources. */
 122                 res->domains = RADEON_DOMAIN_GTT;
 123                 break;
 124         case PIPE_USAGE_DYNAMIC:
 125                 /* Older kernels didn't always flush the HDP cache before
 126                  * CS execution
 127                  */
 128                 if (sscreen->info.drm_major == 2 &&
 129                     sscreen->info.drm_minor < 40) {
 130                         res->domains = RADEON_DOMAIN_GTT;
 131                         res->flags |= RADEON_FLAG_GTT_WC;
 132                         break;
 133                 }
 134                 /* fall through */
 135         case PIPE_USAGE_DEFAULT:
 136         case PIPE_USAGE_IMMUTABLE:
 137         default:
 138                 /* Not listing GTT here improves performance in some
 139                  * apps. */
 140                 res->domains = RADEON_DOMAIN_VRAM;
 141                 res->flags |= RADEON_FLAG_GTT_WC;
 142                 break;
 143         }
 144
 145         if (res->b.b.target == PIPE_BUFFER &&
 146             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 147                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 148                 /* Use GTT for all persistent mappings with older
 149                  * kernels, because they didn't always flush the HDP
 150                  * cache before CS execution.
 151                  *
 152                  * Write-combined CPU mappings are fine, the kernel
 153                  * ensures all CPU writes finish before the GPU
 154                  * executes a command stream.
 155                  */
 156                 if (sscreen->info.drm_major == 2 &&
 157                     sscreen->info.drm_minor < 40)
 158                         res->domains = RADEON_DOMAIN_GTT;
 159         }
 160
 161         /* Tiled textures are unmappable. Always put them in VRAM. */
 162         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 163             res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
 164                 res->domains = RADEON_DOMAIN_VRAM;
 165                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 166                          RADEON_FLAG_GTT_WC;
 167         }
 168
 169         /* Displayable and shareable surfaces are not suballocated. */
 170         if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 171                 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 172         else
 173                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 174
 175         if (sscreen->debug_flags & DBG(NO_WC))
 176                 res->flags &= ~RADEON_FLAG_GTT_WC;
 177
 178         if (res->b.b.flags & SI_RESOURCE_FLAG_READ_ONLY)
 179                 res->flags |= RADEON_FLAG_READ_ONLY;
 180
 181         if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
 182                 res->flags |= RADEON_FLAG_32BIT;
 183
 184         /* Set expected VRAM and GART usage for the buffer. */
 185         res->vram_usage = 0;
 186         res->gart_usage = 0;
 187         res->max_forced_staging_uploads = 0;
 188         res->b.max_forced_staging_uploads = 0;
 189
 190         if (res->domains & RADEON_DOMAIN_VRAM) {
 191                 res->vram_usage = size;
 192
 193                 res->max_forced_staging_uploads =
 194                 res->b.max_forced_staging_uploads =
 195                         sscreen->info.has_dedicated_vram &&
 196                         size >= sscreen->info.vram_vis_size / 4 ? 1 : 0;
 197         } else if (res->domains & RADEON_DOMAIN_GTT) {
 198                 res->gart_usage = size;
 199         }
 200 }
 201
 202 bool si_alloc_resource(struct si_screen *sscreen,
 203                        struct r600_resource *res)
 204 {
 205         struct pb_buffer *old_buf, *new_buf;
 206
 207         /* Allocate a new resource. */
 208         new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size,
 209                                              res->bo_alignment,
 210                                              res->domains, res->flags);
 211         if (!new_buf) {
 212                 return false;
 213         }
 214
 215         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 216          * NULL. This should prevent crashes with multiple contexts using
 217          * the same buffer where one of the contexts invalidates it while
 218          * the others are using it. */
 219         old_buf = res->buf;
 220         res->buf = new_buf; /* should be atomic */
 221         res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
 222
 223         if (res->flags & RADEON_FLAG_32BIT) {
 224                 uint64_t start = res->gpu_address;
 225                 uint64_t last = start + res->bo_size - 1;
 226                 (void)start;
 227                 (void)last;
 228
 229                 assert((start >> 32) == sscreen->info.address32_hi);
 230                 assert((last >> 32) == sscreen->info.address32_hi);
 231         }
 232
 233         pb_reference(&old_buf, NULL);
 234
 235         util_range_set_empty(&res->valid_buffer_range);
 236         res->TC_L2_dirty = false;
 237
 238         /* Print debug information. */
 239         if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
 240                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 241                         res->gpu_address, res->gpu_address + res->buf->size,
 242                         res->buf->size);
 243         }
 244         return true;
 245 }
 246
 247 static void si_buffer_destroy(struct pipe_screen *screen,
 248                               struct pipe_resource *buf)
 249 {
 250         struct r600_resource *rbuffer = r600_resource(buf);
 251
 252         threaded_resource_deinit(buf);
 253         util_range_destroy(&rbuffer->valid_buffer_range);
 254         pb_reference(&rbuffer->buf, NULL);
 255         FREE(rbuffer);
 256 }
 257
 258 /* Reallocate the buffer a update all resource bindings where the buffer is
 259  * bound.
 260  *
 261  * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
 262  * idle by discarding its contents.
 263  */
 264 static bool
 265 si_invalidate_buffer(struct si_context *sctx,
 266                      struct r600_resource *rbuffer)
 267 {
 268         /* Shared buffers can't be reallocated. */
 269         if (rbuffer->b.is_shared)
 270                 return false;
 271
 272         /* Sparse buffers can't be reallocated. */
 273         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 274                 return false;
 275
 276         /* In AMD_pinned_memory, the user pointer association only gets
 277          * broken when the buffer is explicitly re-allocated.
 278          */
 279         if (rbuffer->b.is_user_ptr)
 280                 return false;
 281
 282         /* Check if mapping this buffer would cause waiting for the GPU. */
 283         if (si_rings_is_buffer_referenced(sctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 284             !sctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 285                 uint64_t old_va = rbuffer->gpu_address;
 286
 287                 /* Reallocate the buffer in the same pipe_resource. */
 288                 si_alloc_resource(sctx->screen, rbuffer);
 289                 si_rebind_buffer(sctx, &rbuffer->b.b, old_va);
 290         } else {
 291                 util_range_set_empty(&rbuffer->valid_buffer_range);
 292         }
 293
 294         return true;
 295 }
 296
 297 /* Replace the storage of dst with src. */
 298 void si_replace_buffer_storage(struct pipe_context *ctx,
 299                                  struct pipe_resource *dst,
 300                                  struct pipe_resource *src)
 301 {
 302         struct si_context *sctx = (struct si_context*)ctx;
 303         struct r600_resource *rdst = r600_resource(dst);
 304         struct r600_resource *rsrc = r600_resource(src);
 305         uint64_t old_gpu_address = rdst->gpu_address;
 306
 307         pb_reference(&rdst->buf, rsrc->buf);
 308         rdst->gpu_address = rsrc->gpu_address;
 309         rdst->b.b.bind = rsrc->b.b.bind;
 310         rdst->b.max_forced_staging_uploads = rsrc->b.max_forced_staging_uploads;
 311         rdst->max_forced_staging_uploads = rsrc->max_forced_staging_uploads;
 312         rdst->flags = rsrc->flags;
 313
 314         assert(rdst->vram_usage == rsrc->vram_usage);
 315         assert(rdst->gart_usage == rsrc->gart_usage);
 316         assert(rdst->bo_size == rsrc->bo_size);
 317         assert(rdst->bo_alignment == rsrc->bo_alignment);
 318         assert(rdst->domains == rsrc->domains);
 319
 320         si_rebind_buffer(sctx, dst, old_gpu_address);
 321 }
 322
 323 static void si_invalidate_resource(struct pipe_context *ctx,
 324                                    struct pipe_resource *resource)
 325 {
 326         struct si_context *sctx = (struct si_context*)ctx;
 327         struct r600_resource *rbuffer = r600_resource(resource);
 328
 329         /* We currently only do anyting here for buffers */
 330         if (resource->target == PIPE_BUFFER)
 331                 (void)si_invalidate_buffer(sctx, rbuffer);
 332 }
 333
 334 static void *si_buffer_get_transfer(struct pipe_context *ctx,
 335                                     struct pipe_resource *resource,
 336                                     unsigned usage,
 337                                     const struct pipe_box *box,
 338                                     struct pipe_transfer **ptransfer,
 339                                     void *data, struct r600_resource *staging,
 340                                     unsigned offset)
 341 {
 342         struct si_context *sctx = (struct si_context*)ctx;
 343         struct r600_transfer *transfer;
 344
 345         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 346                 transfer = slab_alloc(&sctx->pool_transfers_unsync);
 347         else
 348                 transfer = slab_alloc(&sctx->pool_transfers);
 349
 350         transfer->b.b.resource = NULL;
 351         pipe_resource_reference(&transfer->b.b.resource, resource);
 352         transfer->b.b.level = 0;
 353         transfer->b.b.usage = usage;
 354         transfer->b.b.box = *box;
 355         transfer->b.b.stride = 0;
 356         transfer->b.b.layer_stride = 0;
 357         transfer->b.staging = NULL;
 358         transfer->offset = offset;
 359         transfer->staging = staging;
 360         *ptransfer = &transfer->b.b;
 361         return data;
 362 }
 363
 364 static void *si_buffer_transfer_map(struct pipe_context *ctx,
 365                                     struct pipe_resource *resource,
 366                                     unsigned level,
 367                                     unsigned usage,
 368                                     const struct pipe_box *box,
 369                                     struct pipe_transfer **ptransfer)
 370 {
 371         struct si_context *sctx = (struct si_context*)ctx;
 372         struct r600_resource *rbuffer = r600_resource(resource);
 373         uint8_t *data;
 374
 375         assert(box->x + box->width <= resource->width0);
 376
 377         /* From GL_AMD_pinned_memory issues:
 378          *
 379          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 380          *        same system address which was specified at creation time?
 381          *
 382          *        RESOLVED: NO. The GL implementation might return a different
 383          *        virtual mapping of that memory, although the same physical
 384          *        page will be used.
 385          *
 386          * So don't ever use staging buffers.
 387          */
 388         if (rbuffer->b.is_user_ptr)
 389                 usage |= PIPE_TRANSFER_PERSISTENT;
 390
 391         /* See if the buffer range being mapped has never been initialized,
 392          * in which case it can be mapped unsynchronized. */
 393         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 394                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 395             usage & PIPE_TRANSFER_WRITE &&
 396             !rbuffer->b.is_shared &&
 397             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 398                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 399         }
 400
 401         /* If discarding the entire range, discard the whole resource instead. */
 402         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 403             box->x == 0 && box->width == resource->width0) {
 404                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 405         }
 406
 407         /* If a buffer in VRAM is too large and the range is discarded, don't
 408          * map it directly. This makes sure that the buffer stays in VRAM.
 409          */
 410         bool force_discard_range = false;
 411         if (usage & (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 412                      PIPE_TRANSFER_DISCARD_RANGE) &&
 413             !(usage & PIPE_TRANSFER_PERSISTENT) &&
 414             /* Try not to decrement the counter if it's not positive. Still racy,
 415              * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
 416             rbuffer->max_forced_staging_uploads > 0 &&
 417             p_atomic_dec_return(&rbuffer->max_forced_staging_uploads) >= 0) {
 418                 usage &= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 419                            PIPE_TRANSFER_UNSYNCHRONIZED);
 420                 usage |= PIPE_TRANSFER_DISCARD_RANGE;
 421                 force_discard_range = true;
 422         }
 423
 424         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 425             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 426                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 427                 assert(usage & PIPE_TRANSFER_WRITE);
 428
 429                 if (si_invalidate_buffer(sctx, rbuffer)) {
 430                         /* At this point, the buffer is always idle. */
 431                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 432                 } else {
 433                         /* Fall back to a temporary buffer. */
 434                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 435                 }
 436         }
 437
 438         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 439             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 440                          PIPE_TRANSFER_PERSISTENT))) ||
 441              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 442                 assert(usage & PIPE_TRANSFER_WRITE);
 443
 444                 /* Check if mapping this buffer would cause waiting for the GPU.
 445                  */
 446                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 447                     force_discard_range ||
 448                     si_rings_is_buffer_referenced(sctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 449                     !sctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 450                         /* Do a wait-free write-only transfer using a temporary buffer. */
 451                         unsigned offset;
 452                         struct r600_resource *staging = NULL;
 453
 454                         u_upload_alloc(ctx->stream_uploader, 0,
 455                                        box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT),
 456                                        sctx->screen->info.tcc_cache_line_size,
 457                                        &offset, (struct pipe_resource**)&staging,
 458                                        (void**)&data);
 459
 460                         if (staging) {
 461                                 data += box->x % SI_MAP_BUFFER_ALIGNMENT;
 462                                 return si_buffer_get_transfer(ctx, resource, usage, box,
 463                                                                 ptransfer, data, staging, offset);
 464                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 465                                 return NULL;
 466                         }
 467                 } else {
 468                         /* At this point, the buffer is always idle (we checked it above). */
 469                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 470                 }
 471         }
 472         /* Use a staging buffer in cached GTT for reads. */
 473         else if (((usage & PIPE_TRANSFER_READ) &&
 474                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 475                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 476                    rbuffer->flags & RADEON_FLAG_GTT_WC)) ||
 477                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 478                 struct r600_resource *staging;
 479
 480                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 481                 staging = (struct r600_resource*) pipe_buffer_create(
 482                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 483                                 box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT));
 484                 if (staging) {
 485                         /* Copy the VRAM buffer to the staging buffer. */
 486                         sctx->dma_copy(ctx, &staging->b.b, 0,
 487                                        box->x % SI_MAP_BUFFER_ALIGNMENT,
 488                                        0, 0, resource, 0, box);
 489
 490                         data = si_buffer_map_sync_with_rings(sctx, staging,
 491                                                              usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 492                         if (!data) {
 493                                 r600_resource_reference(&staging, NULL);
 494                                 return NULL;
 495                         }
 496                         data += box->x % SI_MAP_BUFFER_ALIGNMENT;
 497
 498                         return si_buffer_get_transfer(ctx, resource, usage, box,
 499                                                         ptransfer, data, staging, 0);
 500                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 501                         return NULL;
 502                 }
 503         }
 504
 505         data = si_buffer_map_sync_with_rings(sctx, rbuffer, usage);
 506         if (!data) {
 507                 return NULL;
 508         }
 509         data += box->x;
 510
 511         return si_buffer_get_transfer(ctx, resource, usage, box,
 512                                         ptransfer, data, NULL, 0);
 513 }
 514
 515 static void si_buffer_do_flush_region(struct pipe_context *ctx,
 516                                       struct pipe_transfer *transfer,
 517                                       const struct pipe_box *box)
 518 {
 519         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 520         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 521
 522         if (rtransfer->staging) {
 523                 struct pipe_resource *dst, *src;
 524                 unsigned soffset;
 525                 struct pipe_box dma_box;
 526
 527                 dst = transfer->resource;
 528                 src = &rtransfer->staging->b.b;
 529                 soffset = rtransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT;
 530
 531                 u_box_1d(soffset, box->width, &dma_box);
 532
 533                 /* Copy the staging buffer into the original one. */
 534                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 535         }
 536
 537         util_range_add(&rbuffer->valid_buffer_range, box->x,
 538                        box->x + box->width);
 539 }
 540
 541 static void si_buffer_flush_region(struct pipe_context *ctx,
 542                                    struct pipe_transfer *transfer,
 543                                    const struct pipe_box *rel_box)
 544 {
 545         unsigned required_usage = PIPE_TRANSFER_WRITE |
 546                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 547
 548         if ((transfer->usage & required_usage) == required_usage) {
 549                 struct pipe_box box;
 550
 551                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 552                 si_buffer_do_flush_region(ctx, transfer, &box);
 553         }
 554 }
 555
 556 static void si_buffer_transfer_unmap(struct pipe_context *ctx,
 557                                      struct pipe_transfer *transfer)
 558 {
 559         struct si_context *sctx = (struct si_context*)ctx;
 560         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 561
 562         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 563             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 564                 si_buffer_do_flush_region(ctx, transfer, &transfer->box);
 565
 566         r600_resource_reference(&rtransfer->staging, NULL);
 567         assert(rtransfer->b.staging == NULL); /* for threaded context only */
 568         pipe_resource_reference(&transfer->resource, NULL);
 569
 570         /* Don't use pool_transfers_unsync. We are always in the driver
 571          * thread. */
 572         slab_free(&sctx->pool_transfers, transfer);
 573 }
 574
 575 static void si_buffer_subdata(struct pipe_context *ctx,
 576                               struct pipe_resource *buffer,
 577                               unsigned usage, unsigned offset,
 578                               unsigned size, const void *data)
 579 {
 580         struct pipe_transfer *transfer = NULL;
 581         struct pipe_box box;
 582         uint8_t *map = NULL;
 583
 584         u_box_1d(offset, size, &box);
 585         map = si_buffer_transfer_map(ctx, buffer, 0,
 586                                        PIPE_TRANSFER_WRITE |
 587                                        PIPE_TRANSFER_DISCARD_RANGE |
 588                                        usage,
 589                                        &box, &transfer);
 590         if (!map)
 591                 return;
 592
 593         memcpy(map, data, size);
 594         si_buffer_transfer_unmap(ctx, transfer);
 595 }
 596
 597 static const struct u_resource_vtbl si_buffer_vtbl =
 598 {
 599         NULL,                           /* get_handle */
 600         si_buffer_destroy,              /* resource_destroy */
 601         si_buffer_transfer_map, /* transfer_map */
 602         si_buffer_flush_region, /* transfer_flush_region */
 603         si_buffer_transfer_unmap,       /* transfer_unmap */
 604 };
 605
 606 static struct r600_resource *
 607 si_alloc_buffer_struct(struct pipe_screen *screen,
 608                        const struct pipe_resource *templ)
 609 {
 610         struct r600_resource *rbuffer;
 611
 612         rbuffer = MALLOC_STRUCT(r600_resource);
 613
 614         rbuffer->b.b = *templ;
 615         rbuffer->b.b.next = NULL;
 616         pipe_reference_init(&rbuffer->b.b.reference, 1);
 617         rbuffer->b.b.screen = screen;
 618
 619         rbuffer->b.vtbl = &si_buffer_vtbl;
 620         threaded_resource_init(&rbuffer->b.b);
 621
 622         rbuffer->buf = NULL;
 623         rbuffer->bind_history = 0;
 624         rbuffer->TC_L2_dirty = false;
 625         util_range_init(&rbuffer->valid_buffer_range);
 626         return rbuffer;
 627 }
 628
 629 static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 630                                               const struct pipe_resource *templ,
 631                                               unsigned alignment)
 632 {
 633         struct si_screen *sscreen = (struct si_screen*)screen;
 634         struct r600_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
 635
 636         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 637                 rbuffer->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
 638
 639         si_init_resource_fields(sscreen, rbuffer, templ->width0, alignment);
 640
 641         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 642                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 643
 644         if (!si_alloc_resource(sscreen, rbuffer)) {
 645                 FREE(rbuffer);
 646                 return NULL;
 647         }
 648         return &rbuffer->b.b;
 649 }
 650
 651 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 652                                                unsigned flags,
 653                                                unsigned usage,
 654                                                unsigned size,
 655                                                unsigned alignment)
 656 {
 657         struct pipe_resource buffer;
 658
 659         memset(&buffer, 0, sizeof buffer);
 660         buffer.target = PIPE_BUFFER;
 661         buffer.format = PIPE_FORMAT_R8_UNORM;
 662         buffer.bind = 0;
 663         buffer.usage = usage;
 664         buffer.flags = flags;
 665         buffer.width0 = size;
 666         buffer.height0 = 1;
 667         buffer.depth0 = 1;
 668         buffer.array_size = 1;
 669         return si_buffer_create(screen, &buffer, alignment);
 670 }
 671
 672 static struct pipe_resource *
 673 si_buffer_from_user_memory(struct pipe_screen *screen,
 674                            const struct pipe_resource *templ,
 675                            void *user_memory)
 676 {
 677         struct si_screen *sscreen = (struct si_screen*)screen;
 678         struct radeon_winsys *ws = sscreen->ws;
 679         struct r600_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
 680
 681         rbuffer->domains = RADEON_DOMAIN_GTT;
 682         rbuffer->flags = 0;
 683         rbuffer->b.is_user_ptr = true;
 684         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 685         util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 686
 687         /* Convert a user pointer to a buffer. */
 688         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 689         if (!rbuffer->buf) {
 690                 FREE(rbuffer);
 691                 return NULL;
 692         }
 693
 694         rbuffer->gpu_address = ws->buffer_get_virtual_address(rbuffer->buf);
 695         rbuffer->vram_usage = 0;
 696         rbuffer->gart_usage = templ->width0;
 697
 698         return &rbuffer->b.b;
 699 }
 700
 701 static struct pipe_resource *si_resource_create(struct pipe_screen *screen,
 702                                                 const struct pipe_resource *templ)
 703 {
 704         if (templ->target == PIPE_BUFFER) {
 705                 return si_buffer_create(screen, templ, 256);
 706         } else {
 707                 return si_texture_create(screen, templ);
 708         }
 709 }
 710
 711 static bool si_resource_commit(struct pipe_context *pctx,
 712                                struct pipe_resource *resource,
 713                                unsigned level, struct pipe_box *box,
 714                                bool commit)
 715 {
 716         struct si_context *ctx = (struct si_context *)pctx;
 717         struct r600_resource *res = r600_resource(resource);
 718
 719         /*
 720          * Since buffer commitment changes cannot be pipelined, we need to
 721          * (a) flush any pending commands that refer to the buffer we're about
 722          *     to change, and
 723          * (b) wait for threaded submit to finish, including those that were
 724          *     triggered by some other, earlier operation.
 725          */
 726         if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
 727             ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs,
 728                                                res->buf, RADEON_USAGE_READWRITE)) {
 729                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 730         }
 731         if (radeon_emitted(ctx->dma_cs, 0) &&
 732             ctx->ws->cs_is_buffer_referenced(ctx->dma_cs,
 733                                                res->buf, RADEON_USAGE_READWRITE)) {
 734                 si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
 735         }
 736
 737         ctx->ws->cs_sync_flush(ctx->dma_cs);
 738         ctx->ws->cs_sync_flush(ctx->gfx_cs);
 739
 740         assert(resource->target == PIPE_BUFFER);
 741
 742         return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
 743 }
 744
 745 void si_init_screen_buffer_functions(struct si_screen *sscreen)
 746 {
 747         sscreen->b.resource_create = si_resource_create;
 748         sscreen->b.resource_destroy = u_resource_destroy_vtbl;
 749         sscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
 750 }
 751
 752 void si_init_buffer_functions(struct si_context *sctx)
 753 {
 754         sctx->b.invalidate_resource = si_invalidate_resource;
 755         sctx->b.transfer_map = u_transfer_map_vtbl;
 756         sctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
 757         sctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 758         sctx->b.texture_subdata = u_default_texture_subdata;
 759         sctx->b.buffer_subdata = si_buffer_subdata;
 760         sctx->b.resource_commit = si_resource_commit;
 761 }