2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 * This file contains helpers for writing commands to commands streams.
29 #ifndef SI_BUILD_PM4_H
30 #define SI_BUILD_PM4_H
35 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
37 assert(reg
< SI_CONTEXT_REG_OFFSET
);
38 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
39 radeon_emit(cs
, PKT3(PKT3_SET_CONFIG_REG
, num
, 0));
40 radeon_emit(cs
, (reg
- SI_CONFIG_REG_OFFSET
) >> 2);
43 static inline void radeon_set_config_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
45 radeon_set_config_reg_seq(cs
, reg
, 1);
46 radeon_emit(cs
, value
);
49 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
51 assert(reg
>= SI_CONTEXT_REG_OFFSET
);
52 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
53 radeon_emit(cs
, PKT3(PKT3_SET_CONTEXT_REG
, num
, 0));
54 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
57 static inline void radeon_set_context_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
59 radeon_set_context_reg_seq(cs
, reg
, 1);
60 radeon_emit(cs
, value
);
63 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf
*cs
,
64 unsigned reg
, unsigned idx
,
67 assert(reg
>= SI_CONTEXT_REG_OFFSET
);
68 assert(cs
->current
.cdw
+ 3 <= cs
->current
.max_dw
);
69 radeon_emit(cs
, PKT3(PKT3_SET_CONTEXT_REG
, 1, 0));
70 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2 | (idx
<< 28));
71 radeon_emit(cs
, value
);
74 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
76 assert(reg
>= SI_SH_REG_OFFSET
&& reg
< SI_SH_REG_END
);
77 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
78 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, num
, 0));
79 radeon_emit(cs
, (reg
- SI_SH_REG_OFFSET
) >> 2);
82 static inline void radeon_set_sh_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
84 radeon_set_sh_reg_seq(cs
, reg
, 1);
85 radeon_emit(cs
, value
);
88 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
90 assert(reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
);
91 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
92 radeon_emit(cs
, PKT3(PKT3_SET_UCONFIG_REG
, num
, 0));
93 radeon_emit(cs
, (reg
- CIK_UCONFIG_REG_OFFSET
) >> 2);
96 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
98 radeon_set_uconfig_reg_seq(cs
, reg
, 1);
99 radeon_emit(cs
, value
);
102 static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf
*cs
,
103 struct si_screen
*screen
,
104 unsigned reg
, unsigned idx
,
107 assert(reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
);
108 assert(cs
->current
.cdw
+ 3 <= cs
->current
.max_dw
);
110 unsigned opcode
= PKT3_SET_UCONFIG_REG_INDEX
;
111 if (screen
->info
.chip_class
< GFX9
||
112 (screen
->info
.chip_class
== GFX9
&& screen
->info
.me_fw_version
< 26))
113 opcode
= PKT3_SET_UCONFIG_REG
;
114 radeon_emit(cs
, PKT3(opcode
, 1, 0));
115 radeon_emit(cs
, (reg
- CIK_UCONFIG_REG_OFFSET
) >> 2 | (idx
<< 28));
116 radeon_emit(cs
, value
);
119 static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf
*cs
, unsigned reg
,
120 unsigned value
, unsigned mask
)
122 assert(reg
>= SI_CONTEXT_REG_OFFSET
);
123 assert(cs
->current
.cdw
+ 4 <= cs
->current
.max_dw
);
124 radeon_emit(cs
, PKT3(PKT3_CONTEXT_REG_RMW
, 2, 0));
125 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
126 radeon_emit(cs
, mask
);
127 radeon_emit(cs
, value
);
130 /* Emit PKT3_CONTEXT_REG_RMW if the register value is different. */
131 static inline void radeon_opt_set_context_reg_rmw(struct si_context
*sctx
, unsigned offset
,
132 enum si_tracked_reg reg
, unsigned value
,
135 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
137 assert((value
& ~mask
) == 0);
140 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
141 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
142 radeon_set_context_reg_rmw(cs
, offset
, value
, mask
);
144 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
145 sctx
->tracked_regs
.reg_value
[reg
] = value
;
149 /* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
150 static inline void radeon_opt_set_context_reg(struct si_context
*sctx
, unsigned offset
,
151 enum si_tracked_reg reg
, unsigned value
)
153 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
155 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
156 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
157 radeon_set_context_reg(cs
, offset
, value
);
159 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
160 sctx
->tracked_regs
.reg_value
[reg
] = value
;
165 * Set 2 consecutive registers if any registers value is different.
166 * @param offset starting register offset
167 * @param value1 is written to first register
168 * @param value2 is written to second register
170 static inline void radeon_opt_set_context_reg2(struct si_context
*sctx
, unsigned offset
,
171 enum si_tracked_reg reg
, unsigned value1
,
174 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
176 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x3) != 0x3 ||
177 sctx
->tracked_regs
.reg_value
[reg
] != value1
||
178 sctx
->tracked_regs
.reg_value
[reg
+1] != value2
) {
179 radeon_set_context_reg_seq(cs
, offset
, 2);
180 radeon_emit(cs
, value1
);
181 radeon_emit(cs
, value2
);
183 sctx
->tracked_regs
.reg_value
[reg
] = value1
;
184 sctx
->tracked_regs
.reg_value
[reg
+1] = value2
;
185 sctx
->tracked_regs
.reg_saved
|= 0x3ull
<< reg
;
190 * Set 3 consecutive registers if any registers value is different.
192 static inline void radeon_opt_set_context_reg3(struct si_context
*sctx
, unsigned offset
,
193 enum si_tracked_reg reg
, unsigned value1
,
194 unsigned value2
, unsigned value3
)
196 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
198 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x7) != 0x7 ||
199 sctx
->tracked_regs
.reg_value
[reg
] != value1
||
200 sctx
->tracked_regs
.reg_value
[reg
+1] != value2
||
201 sctx
->tracked_regs
.reg_value
[reg
+2] != value3
) {
202 radeon_set_context_reg_seq(cs
, offset
, 3);
203 radeon_emit(cs
, value1
);
204 radeon_emit(cs
, value2
);
205 radeon_emit(cs
, value3
);
207 sctx
->tracked_regs
.reg_value
[reg
] = value1
;
208 sctx
->tracked_regs
.reg_value
[reg
+1] = value2
;
209 sctx
->tracked_regs
.reg_value
[reg
+2] = value3
;
210 sctx
->tracked_regs
.reg_saved
|= 0x7ull
<< reg
;
215 * Set 4 consecutive registers if any registers value is different.
217 static inline void radeon_opt_set_context_reg4(struct si_context
*sctx
, unsigned offset
,
218 enum si_tracked_reg reg
, unsigned value1
,
219 unsigned value2
, unsigned value3
,
222 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
224 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0xf) != 0xf ||
225 sctx
->tracked_regs
.reg_value
[reg
] != value1
||
226 sctx
->tracked_regs
.reg_value
[reg
+1] != value2
||
227 sctx
->tracked_regs
.reg_value
[reg
+2] != value3
||
228 sctx
->tracked_regs
.reg_value
[reg
+3] != value4
) {
229 radeon_set_context_reg_seq(cs
, offset
, 4);
230 radeon_emit(cs
, value1
);
231 radeon_emit(cs
, value2
);
232 radeon_emit(cs
, value3
);
233 radeon_emit(cs
, value4
);
235 sctx
->tracked_regs
.reg_value
[reg
] = value1
;
236 sctx
->tracked_regs
.reg_value
[reg
+1] = value2
;
237 sctx
->tracked_regs
.reg_value
[reg
+2] = value3
;
238 sctx
->tracked_regs
.reg_value
[reg
+3] = value4
;
239 sctx
->tracked_regs
.reg_saved
|= 0xfull
<< reg
;
244 * Set consecutive registers if any registers value is different.
246 static inline void radeon_opt_set_context_regn(struct si_context
*sctx
, unsigned offset
,
247 unsigned *value
, unsigned *saved_val
,
250 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
253 for (i
= 0; i
< num
; i
++) {
254 if (saved_val
[i
] != value
[i
]) {
255 radeon_set_context_reg_seq(cs
, offset
, num
);
256 for (j
= 0; j
< num
; j
++)
257 radeon_emit(cs
, value
[j
]);
259 memcpy(saved_val
, value
, sizeof(uint32_t) * num
);