2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 * This file contains helpers for writing commands to commands streams.
29 #ifndef SI_BUILD_PM4_H
30 #define SI_BUILD_PM4_H
35 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
37 assert(reg
< SI_CONTEXT_REG_OFFSET
);
38 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
39 radeon_emit(cs
, PKT3(PKT3_SET_CONFIG_REG
, num
, 0));
40 radeon_emit(cs
, (reg
- SI_CONFIG_REG_OFFSET
) >> 2);
43 static inline void radeon_set_config_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
45 radeon_set_config_reg_seq(cs
, reg
, 1);
46 radeon_emit(cs
, value
);
49 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
51 assert(reg
>= SI_CONTEXT_REG_OFFSET
);
52 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
53 radeon_emit(cs
, PKT3(PKT3_SET_CONTEXT_REG
, num
, 0));
54 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
57 static inline void radeon_set_context_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
59 radeon_set_context_reg_seq(cs
, reg
, 1);
60 radeon_emit(cs
, value
);
63 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned idx
,
66 assert(reg
>= SI_CONTEXT_REG_OFFSET
);
67 assert(cs
->current
.cdw
+ 3 <= cs
->current
.max_dw
);
68 radeon_emit(cs
, PKT3(PKT3_SET_CONTEXT_REG
, 1, 0));
69 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2 | (idx
<< 28));
70 radeon_emit(cs
, value
);
73 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
75 assert(reg
>= SI_SH_REG_OFFSET
&& reg
< SI_SH_REG_END
);
76 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
77 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, num
, 0));
78 radeon_emit(cs
, (reg
- SI_SH_REG_OFFSET
) >> 2);
81 static inline void radeon_set_sh_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
83 radeon_set_sh_reg_seq(cs
, reg
, 1);
84 radeon_emit(cs
, value
);
87 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned num
)
89 assert(reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
);
90 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
91 radeon_emit(cs
, PKT3(PKT3_SET_UCONFIG_REG
, num
, 0));
92 radeon_emit(cs
, (reg
- CIK_UCONFIG_REG_OFFSET
) >> 2);
95 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf
*cs
, unsigned reg
, unsigned value
)
97 radeon_set_uconfig_reg_seq(cs
, reg
, 1);
98 radeon_emit(cs
, value
);
101 static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf
*cs
, struct si_screen
*screen
,
102 unsigned reg
, unsigned idx
, unsigned value
)
104 assert(reg
>= CIK_UCONFIG_REG_OFFSET
&& reg
< CIK_UCONFIG_REG_END
);
105 assert(cs
->current
.cdw
+ 3 <= cs
->current
.max_dw
);
107 unsigned opcode
= PKT3_SET_UCONFIG_REG_INDEX
;
108 if (screen
->info
.chip_class
< GFX9
||
109 (screen
->info
.chip_class
== GFX9
&& screen
->info
.me_fw_version
< 26))
110 opcode
= PKT3_SET_UCONFIG_REG
;
111 radeon_emit(cs
, PKT3(opcode
, 1, 0));
112 radeon_emit(cs
, (reg
- CIK_UCONFIG_REG_OFFSET
) >> 2 | (idx
<< 28));
113 radeon_emit(cs
, value
);
116 static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf
*cs
, unsigned reg
,
117 unsigned value
, unsigned mask
)
119 assert(reg
>= SI_CONTEXT_REG_OFFSET
);
120 assert(cs
->current
.cdw
+ 4 <= cs
->current
.max_dw
);
121 radeon_emit(cs
, PKT3(PKT3_CONTEXT_REG_RMW
, 2, 0));
122 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
123 radeon_emit(cs
, mask
);
124 radeon_emit(cs
, value
);
127 /* Emit PKT3_CONTEXT_REG_RMW if the register value is different. */
128 static inline void radeon_opt_set_context_reg_rmw(struct si_context
*sctx
, unsigned offset
,
129 enum si_tracked_reg reg
, unsigned value
,
132 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
134 assert((value
& ~mask
) == 0);
137 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
138 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
139 radeon_set_context_reg_rmw(cs
, offset
, value
, mask
);
141 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
142 sctx
->tracked_regs
.reg_value
[reg
] = value
;
146 /* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
147 static inline void radeon_opt_set_context_reg(struct si_context
*sctx
, unsigned offset
,
148 enum si_tracked_reg reg
, unsigned value
)
150 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
152 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
153 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
154 radeon_set_context_reg(cs
, offset
, value
);
156 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
157 sctx
->tracked_regs
.reg_value
[reg
] = value
;
162 * Set 2 consecutive registers if any registers value is different.
163 * @param offset starting register offset
164 * @param value1 is written to first register
165 * @param value2 is written to second register
167 static inline void radeon_opt_set_context_reg2(struct si_context
*sctx
, unsigned offset
,
168 enum si_tracked_reg reg
, unsigned value1
,
171 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
173 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x3) != 0x3 ||
174 sctx
->tracked_regs
.reg_value
[reg
] != value1
||
175 sctx
->tracked_regs
.reg_value
[reg
+ 1] != value2
) {
176 radeon_set_context_reg_seq(cs
, offset
, 2);
177 radeon_emit(cs
, value1
);
178 radeon_emit(cs
, value2
);
180 sctx
->tracked_regs
.reg_value
[reg
] = value1
;
181 sctx
->tracked_regs
.reg_value
[reg
+ 1] = value2
;
182 sctx
->tracked_regs
.reg_saved
|= 0x3ull
<< reg
;
187 * Set 3 consecutive registers if any registers value is different.
189 static inline void radeon_opt_set_context_reg3(struct si_context
*sctx
, unsigned offset
,
190 enum si_tracked_reg reg
, unsigned value1
,
191 unsigned value2
, unsigned value3
)
193 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
195 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x7) != 0x7 ||
196 sctx
->tracked_regs
.reg_value
[reg
] != value1
||
197 sctx
->tracked_regs
.reg_value
[reg
+ 1] != value2
||
198 sctx
->tracked_regs
.reg_value
[reg
+ 2] != value3
) {
199 radeon_set_context_reg_seq(cs
, offset
, 3);
200 radeon_emit(cs
, value1
);
201 radeon_emit(cs
, value2
);
202 radeon_emit(cs
, value3
);
204 sctx
->tracked_regs
.reg_value
[reg
] = value1
;
205 sctx
->tracked_regs
.reg_value
[reg
+ 1] = value2
;
206 sctx
->tracked_regs
.reg_value
[reg
+ 2] = value3
;
207 sctx
->tracked_regs
.reg_saved
|= 0x7ull
<< reg
;
212 * Set 4 consecutive registers if any registers value is different.
214 static inline void radeon_opt_set_context_reg4(struct si_context
*sctx
, unsigned offset
,
215 enum si_tracked_reg reg
, unsigned value1
,
216 unsigned value2
, unsigned value3
, unsigned value4
)
218 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
220 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0xf) != 0xf ||
221 sctx
->tracked_regs
.reg_value
[reg
] != value1
||
222 sctx
->tracked_regs
.reg_value
[reg
+ 1] != value2
||
223 sctx
->tracked_regs
.reg_value
[reg
+ 2] != value3
||
224 sctx
->tracked_regs
.reg_value
[reg
+ 3] != value4
) {
225 radeon_set_context_reg_seq(cs
, offset
, 4);
226 radeon_emit(cs
, value1
);
227 radeon_emit(cs
, value2
);
228 radeon_emit(cs
, value3
);
229 radeon_emit(cs
, value4
);
231 sctx
->tracked_regs
.reg_value
[reg
] = value1
;
232 sctx
->tracked_regs
.reg_value
[reg
+ 1] = value2
;
233 sctx
->tracked_regs
.reg_value
[reg
+ 2] = value3
;
234 sctx
->tracked_regs
.reg_value
[reg
+ 3] = value4
;
235 sctx
->tracked_regs
.reg_saved
|= 0xfull
<< reg
;
240 * Set consecutive registers if any registers value is different.
242 static inline void radeon_opt_set_context_regn(struct si_context
*sctx
, unsigned offset
,
243 unsigned *value
, unsigned *saved_val
, unsigned num
)
245 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
248 for (i
= 0; i
< num
; i
++) {
249 if (saved_val
[i
] != value
[i
]) {
250 radeon_set_context_reg_seq(cs
, offset
, num
);
251 for (j
= 0; j
< num
; j
++)
252 radeon_emit(cs
, value
[j
]);
254 memcpy(saved_val
, value
, sizeof(uint32_t) * num
);