projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: switch back to standard DX sample positions
[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct si_texture *tex)
39 {
40 if (tex->cmask_buffer || !tex->surface.cmask_size)
41 return;
42
43 tex->cmask_buffer =
44 si_aligned_buffer_create(&sscreen->b,
45 SI_RESOURCE_FLAG_UNMAPPABLE,
46 PIPE_USAGE_DEFAULT,
47 tex->surface.cmask_size,
48 tex->surface.cmask_alignment);
49 if (tex->cmask_buffer == NULL)
50 return;
51
52 tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
53 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
54
55 p_atomic_inc(&sscreen->compressed_colortex_counter);
56 }
57
58 static bool si_set_clear_color(struct si_texture *tex,
59 enum pipe_format surface_format,
60 const union pipe_color_union *color)
61 {
62 union util_color uc;
63
64 memset(&uc, 0, sizeof(uc));
65
66 if (tex->surface.bpe == 16) {
67 /* DCC fast clear only:
68 * CLEAR_WORD0 = R = G = B
69 * CLEAR_WORD1 = A
70 */
71 assert(color->ui[0] == color->ui[1] &&
72 color->ui[0] == color->ui[2]);
73 uc.ui[0] = color->ui[0];
74 uc.ui[1] = color->ui[3];
75 } else if (util_format_is_pure_uint(surface_format)) {
76 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
77 } else if (util_format_is_pure_sint(surface_format)) {
78 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
79 } else {
80 util_pack_color(color->f, surface_format, &uc);
81 }
82
83 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
84 return false;
85
86 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
87 return true;
88 }
89
90 /** Linearize and convert luminace/intensity to red. */
91 enum pipe_format si_simplify_cb_format(enum pipe_format format)
92 {
93 format = util_format_linear(format);
94 format = util_format_luminance_to_red(format);
95 return util_format_intensity_to_red(format);
96 }
97
98 bool vi_alpha_is_on_msb(enum pipe_format format)
99 {
100 format = si_simplify_cb_format(format);
101
102 /* Formats with 3 channels can't have alpha. */
103 if (util_format_description(format)->nr_channels == 3)
104 return true; /* same as xxxA; is any value OK here? */
105
106 return si_translate_colorswap(format, false) <= 1;
107 }
108
109 static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
110 enum pipe_format surface_format,
111 const union pipe_color_union *color,
112 uint32_t* clear_value,
113 bool *eliminate_needed)
114 {
115 /* If we want to clear without needing a fast clear eliminate step, we
116 * can set color and alpha independently to 0 or 1 (or 0/max for integer
117 * formats).
118 */
119 bool values[4] = {}; /* whether to clear to 0 or 1 */
120 bool color_value = false; /* clear color to 0 or 1 */
121 bool alpha_value = false; /* clear alpha to 0 or 1 */
122 int alpha_channel; /* index of the alpha component */
123 bool has_color = false;
124 bool has_alpha = false;
125
126 const struct util_format_description *desc =
127 util_format_description(si_simplify_cb_format(surface_format));
128
129 /* 128-bit fast clear with different R,G,B values is unsupported. */
130 if (desc->block.bits == 128 &&
131 (color->ui[0] != color->ui[1] ||
132 color->ui[0] != color->ui[2]))
133 return false;
134
135 *eliminate_needed = true;
136 *clear_value = 0x20202020U; /* use CB clear color registers */
137
138 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
139 return true; /* need ELIMINATE_FAST_CLEAR */
140
141 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
142 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
143
144 /* Formats with 3 channels can't have alpha. */
145 if (desc->nr_channels == 3)
146 alpha_channel = -1;
147 else if (surf_alpha_is_on_msb)
148 alpha_channel = desc->nr_channels - 1;
149 else
150 alpha_channel = 0;
151
152 for (int i = 0; i < 4; ++i) {
153 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
154 continue;
155
156 if (desc->channel[i].pure_integer &&
157 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
158 /* Use the maximum value for clamping the clear color. */
159 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
160
161 values[i] = color->i[i] != 0;
162 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
163 return true; /* need ELIMINATE_FAST_CLEAR */
164 } else if (desc->channel[i].pure_integer &&
165 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
166 /* Use the maximum value for clamping the clear color. */
167 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
168
169 values[i] = color->ui[i] != 0U;
170 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
171 return true; /* need ELIMINATE_FAST_CLEAR */
172 } else {
173 values[i] = color->f[i] != 0.0F;
174 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
175 return true; /* need ELIMINATE_FAST_CLEAR */
176 }
177
178 if (desc->swizzle[i] == alpha_channel) {
179 alpha_value = values[i];
180 has_alpha = true;
181 } else {
182 color_value = values[i];
183 has_color = true;
184 }
185 }
186
187 /* If alpha isn't present, make it the same as color, and vice versa. */
188 if (!has_alpha)
189 alpha_value = color_value;
190 else if (!has_color)
191 color_value = alpha_value;
192
193 if (color_value != alpha_value &&
194 base_alpha_is_on_msb != surf_alpha_is_on_msb)
195 return true; /* require ELIMINATE_FAST_CLEAR */
196
197 /* Check if all color values are equal if they are present. */
198 for (int i = 0; i < 4; ++i) {
199 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
200 desc->swizzle[i] != alpha_channel &&
201 values[i] != color_value)
202 return true; /* require ELIMINATE_FAST_CLEAR */
203 }
204
205 /* This doesn't need ELIMINATE_FAST_CLEAR.
206 * CB uses both the DCC clear codes and the CB clear color registers,
207 * so they must match.
208 */
209 *eliminate_needed = false;
210
211 if (color_value)
212 *clear_value |= 0x80808080U;
213 if (alpha_value)
214 *clear_value |= 0x40404040U;
215 return true;
216 }
217
218 void vi_dcc_clear_level(struct si_context *sctx,
219 struct si_texture *tex,
220 unsigned level, unsigned clear_value)
221 {
222 struct pipe_resource *dcc_buffer;
223 uint64_t dcc_offset, clear_size;
224
225 assert(vi_dcc_enabled(tex, level));
226
227 if (tex->dcc_separate_buffer) {
228 dcc_buffer = &tex->dcc_separate_buffer->b.b;
229 dcc_offset = 0;
230 } else {
231 dcc_buffer = &tex->buffer.b.b;
232 dcc_offset = tex->dcc_offset;
233 }
234
235 if (sctx->chip_class >= GFX9) {
236 /* Mipmap level clears aren't implemented. */
237 assert(tex->buffer.b.b.last_level == 0);
238 /* 4x and 8x MSAA needs a sophisticated compute shader for
239 * the clear. See AMDVLK. */
240 assert(tex->buffer.b.b.nr_storage_samples <= 2);
241 clear_size = tex->surface.dcc_size;
242 } else {
243 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
244
245 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
246 assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
247 /* Layered 4x and 8x MSAA DCC fast clears need to clear
248 * dcc_fast_clear_size bytes for each layer. A compute shader
249 * would be more efficient than separate per-layer clear operations.
250 */
251 assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
252
253 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
254 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
255 num_layers;
256 }
257
258 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
259 clear_value, SI_COHERENCY_CB_META);
260 }
261
262 /* Set the same micro tile mode as the destination of the last MSAA resolve.
263 * This allows hitting the MSAA resolve fast path, which requires that both
264 * src and dst micro tile modes match.
265 */
266 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
267 struct si_texture *tex)
268 {
269 if (tex->buffer.b.is_shared ||
270 tex->buffer.b.b.nr_samples <= 1 ||
271 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
272 return;
273
274 assert(sscreen->info.chip_class >= GFX9 ||
275 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
276 assert(tex->buffer.b.b.last_level == 0);
277
278 if (sscreen->info.chip_class >= GFX9) {
279 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
280 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
281
282 /* If you do swizzle_mode % 4, you'll get:
283 * 0 = Depth
284 * 1 = Standard,
285 * 2 = Displayable
286 * 3 = Rotated
287 *
288 * Depth-sample order isn't allowed:
289 */
290 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
291
292 switch (tex->last_msaa_resolve_target_micro_mode) {
293 case RADEON_MICRO_MODE_DISPLAY:
294 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
295 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
296 break;
297 case RADEON_MICRO_MODE_THIN:
298 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
299 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
300 break;
301 case RADEON_MICRO_MODE_ROTATED:
302 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
303 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
304 break;
305 default: /* depth */
306 assert(!"unexpected micro mode");
307 return;
308 }
309 } else if (sscreen->info.chip_class >= CIK) {
310 /* These magic numbers were copied from addrlib. It doesn't use
311 * any definitions for them either. They are all 2D_TILED_THIN1
312 * modes with different bpp and micro tile mode.
313 */
314 switch (tex->last_msaa_resolve_target_micro_mode) {
315 case RADEON_MICRO_MODE_DISPLAY:
316 tex->surface.u.legacy.tiling_index[0] = 10;
317 break;
318 case RADEON_MICRO_MODE_THIN:
319 tex->surface.u.legacy.tiling_index[0] = 14;
320 break;
321 case RADEON_MICRO_MODE_ROTATED:
322 tex->surface.u.legacy.tiling_index[0] = 28;
323 break;
324 default: /* depth, thick */
325 assert(!"unexpected micro mode");
326 return;
327 }
328 } else { /* SI */
329 switch (tex->last_msaa_resolve_target_micro_mode) {
330 case RADEON_MICRO_MODE_DISPLAY:
331 switch (tex->surface.bpe) {
332 case 1:
333 tex->surface.u.legacy.tiling_index[0] = 10;
334 break;
335 case 2:
336 tex->surface.u.legacy.tiling_index[0] = 11;
337 break;
338 default: /* 4, 8 */
339 tex->surface.u.legacy.tiling_index[0] = 12;
340 break;
341 }
342 break;
343 case RADEON_MICRO_MODE_THIN:
344 switch (tex->surface.bpe) {
345 case 1:
346 tex->surface.u.legacy.tiling_index[0] = 14;
347 break;
348 case 2:
349 tex->surface.u.legacy.tiling_index[0] = 15;
350 break;
351 case 4:
352 tex->surface.u.legacy.tiling_index[0] = 16;
353 break;
354 default: /* 8, 16 */
355 tex->surface.u.legacy.tiling_index[0] = 17;
356 break;
357 }
358 break;
359 default: /* depth, thick */
360 assert(!"unexpected micro mode");
361 return;
362 }
363 }
364
365 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
366
367 p_atomic_inc(&sscreen->dirty_tex_counter);
368 }
369
370 static void si_do_fast_color_clear(struct si_context *sctx,
371 unsigned *buffers,
372 const union pipe_color_union *color)
373 {
374 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
375 int i;
376
377 /* This function is broken in BE, so just disable this path for now */
378 #ifdef PIPE_ARCH_BIG_ENDIAN
379 return;
380 #endif
381
382 if (sctx->render_cond)
383 return;
384
385 for (i = 0; i < fb->nr_cbufs; i++) {
386 struct si_texture *tex;
387 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
388
389 if (!fb->cbufs[i])
390 continue;
391
392 /* if this colorbuffer is not being cleared */
393 if (!(*buffers & clear_bit))
394 continue;
395
396 unsigned level = fb->cbufs[i]->u.tex.level;
397 if (level > 0)
398 continue;
399
400 tex = (struct si_texture *)fb->cbufs[i]->texture;
401
402 /* TODO: GFX9: Implement DCC fast clear for level 0 of
403 * mipmapped textures. Mipmapped DCC has to clear a rectangular
404 * area of DCC for level 0 (because the whole miptree is
405 * organized in a 2D plane).
406 */
407 if (sctx->chip_class >= GFX9 &&
408 tex->buffer.b.b.last_level > 0)
409 continue;
410
411 /* the clear is allowed if all layers are bound */
412 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
413 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
414 continue;
415 }
416
417 /* only supported on tiled surfaces */
418 if (tex->surface.is_linear) {
419 continue;
420 }
421
422 /* shared textures can't use fast clear without an explicit flush,
423 * because there is no way to communicate the clear color among
424 * all clients
425 */
426 if (tex->buffer.b.is_shared &&
427 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
428 continue;
429
430 if (sctx->chip_class <= VI &&
431 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
432 !sctx->screen->info.htile_cmask_support_1d_tiling)
433 continue;
434
435 bool need_decompress_pass = false;
436
437 /* Use a slow clear for small surfaces where the cost of
438 * the eliminate pass can be higher than the benefit of fast
439 * clear. The closed driver does this, but the numbers may differ.
440 *
441 * This helps on both dGPUs and APUs, even small APUs like Mullins.
442 */
443 bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
444 tex->buffer.b.b.width0 *
445 tex->buffer.b.b.height0 <= 512 * 512;
446
447 /* Fast clear is the most appropriate place to enable DCC for
448 * displayable surfaces.
449 */
450 if (sctx->family == CHIP_STONEY && !too_small) {
451 vi_separate_dcc_try_enable(sctx, tex);
452
453 /* RB+ isn't supported with a CMASK clear only on Stoney,
454 * so all clears are considered to be hypothetically slow
455 * clears, which is weighed when determining whether to
456 * enable separate DCC.
457 */
458 if (tex->dcc_gather_statistics) /* only for Stoney */
459 tex->num_slow_clears++;
460 }
461
462 /* Try to clear DCC first, otherwise try CMASK. */
463 if (vi_dcc_enabled(tex, 0)) {
464 uint32_t reset_value;
465 bool eliminate_needed;
466
467 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
468 continue;
469
470 /* This can happen with mipmapping or MSAA. */
471 if (sctx->chip_class == VI &&
472 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
473 continue;
474
475 if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
476 fb->cbufs[i]->format,
477 color, &reset_value,
478 &eliminate_needed))
479 continue;
480
481 if (eliminate_needed && too_small)
482 continue;
483
484 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
485 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
486 /* TODO: This doesn't work with MSAA. */
487 if (eliminate_needed)
488 continue;
489
490 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
491 tex->cmask_offset, tex->surface.cmask_size,
492 0xCCCCCCCC, SI_COHERENCY_CB_META);
493 need_decompress_pass = true;
494 }
495
496 vi_dcc_clear_level(sctx, tex, 0, reset_value);
497
498 if (eliminate_needed)
499 need_decompress_pass = true;
500
501 tex->separate_dcc_dirty = true;
502 } else {
503 if (too_small)
504 continue;
505
506 /* 128-bit formats are unusupported */
507 if (tex->surface.bpe > 8) {
508 continue;
509 }
510
511 /* RB+ doesn't work with CMASK fast clear on Stoney. */
512 if (sctx->family == CHIP_STONEY)
513 continue;
514
515 /* ensure CMASK is enabled */
516 si_alloc_separate_cmask(sctx->screen, tex);
517 if (!tex->cmask_buffer)
518 continue;
519
520 /* Do the fast clear. */
521 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
522 tex->cmask_offset, tex->surface.cmask_size, 0,
523 SI_COHERENCY_CB_META);
524 need_decompress_pass = true;
525 }
526
527 if (need_decompress_pass &&
528 !(tex->dirty_level_mask & (1 << level))) {
529 tex->dirty_level_mask |= 1 << level;
530 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
531 }
532
533 /* We can change the micro tile mode before a full clear. */
534 si_set_optimal_micro_tile_mode(sctx->screen, tex);
535
536 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
537 sctx->framebuffer.dirty_cbufs |= 1 << i;
538 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
539 }
540 *buffers &= ~clear_bit;
541 }
542 }
543
544 static void si_clear(struct pipe_context *ctx, unsigned buffers,
545 const union pipe_color_union *color,
546 double depth, unsigned stencil)
547 {
548 struct si_context *sctx = (struct si_context *)ctx;
549 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
550 struct pipe_surface *zsbuf = fb->zsbuf;
551 struct si_texture *zstex =
552 zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
553
554 if (buffers & PIPE_CLEAR_COLOR) {
555 si_do_fast_color_clear(sctx, &buffers, color);
556 if (!buffers)
557 return; /* all buffers have been fast cleared */
558
559 /* These buffers cannot use fast clear, make sure to disable expansion. */
560 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
561 struct si_texture *tex;
562
563 /* If not clearing this buffer, skip. */
564 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
565 continue;
566
567 tex = (struct si_texture *)fb->cbufs[i]->texture;
568 if (tex->surface.fmask_size == 0)
569 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
570 }
571 }
572
573 if (zstex &&
574 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
575 zsbuf->u.tex.first_layer == 0 &&
576 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
577 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
578 if (buffers & PIPE_CLEAR_DEPTH &&
579 (!zstex->tc_compatible_htile ||
580 depth == 0 || depth == 1)) {
581 /* Need to disable EXPCLEAR temporarily if clearing
582 * to a new value. */
583 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
584 sctx->db_depth_disable_expclear = true;
585 }
586
587 if (zstex->depth_clear_value != (float)depth) {
588 /* Update DB_DEPTH_CLEAR. */
589 zstex->depth_clear_value = depth;
590 sctx->framebuffer.dirty_zsbuf = true;
591 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
592 }
593 sctx->db_depth_clear = true;
594 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
595 }
596
597 /* TC-compatible HTILE only supports stencil clears to 0. */
598 if (buffers & PIPE_CLEAR_STENCIL &&
599 (!zstex->tc_compatible_htile || stencil == 0)) {
600 stencil &= 0xff;
601
602 /* Need to disable EXPCLEAR temporarily if clearing
603 * to a new value. */
604 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
605 sctx->db_stencil_disable_expclear = true;
606 }
607
608 if (zstex->stencil_clear_value != (uint8_t)stencil) {
609 /* Update DB_STENCIL_CLEAR. */
610 zstex->stencil_clear_value = stencil;
611 sctx->framebuffer.dirty_zsbuf = true;
612 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
613 }
614 sctx->db_stencil_clear = true;
615 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
616 }
617
618 /* TODO: Find out what's wrong here. Fast depth clear leads to
619 * corruption in ARK: Survival Evolved, but that may just be
620 * a coincidence and the root cause is elsewhere.
621 *
622 * The corruption can be fixed by putting the DB flush before
623 * or after the depth clear. (surprisingly)
624 *
625 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
626 *
627 * This hack decreases back-to-back ClearDepth performance.
628 */
629 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
630 sctx->screen->clear_db_cache_before_clear)
631 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
632 }
633
634 si_blitter_begin(sctx, SI_CLEAR);
635 util_blitter_clear(sctx->blitter, fb->width, fb->height,
636 util_framebuffer_get_num_layers(fb),
637 buffers, color, depth, stencil);
638 si_blitter_end(sctx);
639
640 if (sctx->db_depth_clear) {
641 sctx->db_depth_clear = false;
642 sctx->db_depth_disable_expclear = false;
643 zstex->depth_cleared = true;
644 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
645 }
646
647 if (sctx->db_stencil_clear) {
648 sctx->db_stencil_clear = false;
649 sctx->db_stencil_disable_expclear = false;
650 zstex->stencil_cleared = true;
651 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
652 }
653 }
654
655 static void si_clear_render_target(struct pipe_context *ctx,
656 struct pipe_surface *dst,
657 const union pipe_color_union *color,
658 unsigned dstx, unsigned dsty,
659 unsigned width, unsigned height,
660 bool render_condition_enabled)
661 {
662 struct si_context *sctx = (struct si_context *)ctx;
663
664 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
665 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
666 util_blitter_clear_render_target(sctx->blitter, dst, color,
667 dstx, dsty, width, height);
668 si_blitter_end(sctx);
669 }
670
671 static void si_clear_depth_stencil(struct pipe_context *ctx,
672 struct pipe_surface *dst,
673 unsigned clear_flags,
674 double depth,
675 unsigned stencil,
676 unsigned dstx, unsigned dsty,
677 unsigned width, unsigned height,
678 bool render_condition_enabled)
679 {
680 struct si_context *sctx = (struct si_context *)ctx;
681
682 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
683 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
684 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
685 dstx, dsty, width, height);
686 si_blitter_end(sctx);
687 }
688
689 static void si_clear_texture(struct pipe_context *pipe,
690 struct pipe_resource *tex,
691 unsigned level,
692 const struct pipe_box *box,
693 const void *data)
694 {
695 struct pipe_screen *screen = pipe->screen;
696 struct si_texture *stex = (struct si_texture*)tex;
697 struct pipe_surface tmpl = {{0}};
698 struct pipe_surface *sf;
699 const struct util_format_description *desc =
700 util_format_description(tex->format);
701
702 tmpl.format = tex->format;
703 tmpl.u.tex.first_layer = box->z;
704 tmpl.u.tex.last_layer = box->z + box->depth - 1;
705 tmpl.u.tex.level = level;
706 sf = pipe->create_surface(pipe, tex, &tmpl);
707 if (!sf)
708 return;
709
710 if (stex->is_depth) {
711 unsigned clear;
712 float depth;
713 uint8_t stencil = 0;
714
715 /* Depth is always present. */
716 clear = PIPE_CLEAR_DEPTH;
717 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
718
719 if (stex->surface.has_stencil) {
720 clear |= PIPE_CLEAR_STENCIL;
721 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
722 }
723
724 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
725 box->x, box->y,
726 box->width, box->height, false);
727 } else {
728 union pipe_color_union color;
729
730 /* pipe_color_union requires the full vec4 representation. */
731 if (util_format_is_pure_uint(tex->format))
732 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
733 else if (util_format_is_pure_sint(tex->format))
734 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
735 else
736 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
737
738 if (screen->is_format_supported(screen, tex->format,
739 tex->target, 0, 0,
740 PIPE_BIND_RENDER_TARGET)) {
741 si_clear_render_target(pipe, sf, &color,
742 box->x, box->y,
743 box->width, box->height, false);
744 } else {
745 /* Software fallback - just for R9G9B9E5_FLOAT */
746 util_clear_render_target(pipe, sf, &color,
747 box->x, box->y,
748 box->width, box->height);
749 }
750 }
751 pipe_surface_reference(&sf, NULL);
752 }
753
754 void si_init_clear_functions(struct si_context *sctx)
755 {
756 sctx->b.clear = si_clear;
757 sctx->b.clear_render_target = si_clear_render_target;
758 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
759 sctx->b.clear_texture = si_clear_texture;
760 }