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[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct si_texture *tex)
39 {
40 if (tex->cmask_buffer)
41 return;
42
43 assert(tex->cmask.size == 0);
44
45 si_texture_get_cmask_info(sscreen, tex, &tex->cmask);
46 if (!tex->cmask.size)
47 return;
48
49 tex->cmask_buffer =
50 si_aligned_buffer_create(&sscreen->b,
51 SI_RESOURCE_FLAG_UNMAPPABLE,
52 PIPE_USAGE_DEFAULT,
53 tex->cmask.size,
54 tex->cmask.alignment);
55 if (tex->cmask_buffer == NULL) {
56 tex->cmask.size = 0;
57 return;
58 }
59
60 /* update colorbuffer state bits */
61 tex->cmask.base_address_reg = tex->cmask_buffer->gpu_address >> 8;
62
63 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
64
65 p_atomic_inc(&sscreen->compressed_colortex_counter);
66 }
67
68 static bool si_set_clear_color(struct si_texture *tex,
69 enum pipe_format surface_format,
70 const union pipe_color_union *color)
71 {
72 union util_color uc;
73
74 memset(&uc, 0, sizeof(uc));
75
76 if (tex->surface.bpe == 16) {
77 /* DCC fast clear only:
78 * CLEAR_WORD0 = R = G = B
79 * CLEAR_WORD1 = A
80 */
81 assert(color->ui[0] == color->ui[1] &&
82 color->ui[0] == color->ui[2]);
83 uc.ui[0] = color->ui[0];
84 uc.ui[1] = color->ui[3];
85 } else if (util_format_is_pure_uint(surface_format)) {
86 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
87 } else if (util_format_is_pure_sint(surface_format)) {
88 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
89 } else {
90 util_pack_color(color->f, surface_format, &uc);
91 }
92
93 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
94 return false;
95
96 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
97 return true;
98 }
99
100 /** Linearize and convert luminace/intensity to red. */
101 enum pipe_format si_simplify_cb_format(enum pipe_format format)
102 {
103 format = util_format_linear(format);
104 format = util_format_luminance_to_red(format);
105 return util_format_intensity_to_red(format);
106 }
107
108 bool vi_alpha_is_on_msb(enum pipe_format format)
109 {
110 format = si_simplify_cb_format(format);
111
112 /* Formats with 3 channels can't have alpha. */
113 if (util_format_description(format)->nr_channels == 3)
114 return true; /* same as xxxA; is any value OK here? */
115
116 return si_translate_colorswap(format, false) <= 1;
117 }
118
119 static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
120 enum pipe_format surface_format,
121 const union pipe_color_union *color,
122 uint32_t* clear_value,
123 bool *eliminate_needed)
124 {
125 /* If we want to clear without needing a fast clear eliminate step, we
126 * can set color and alpha independently to 0 or 1 (or 0/max for integer
127 * formats).
128 */
129 bool values[4] = {}; /* whether to clear to 0 or 1 */
130 bool color_value = false; /* clear color to 0 or 1 */
131 bool alpha_value = false; /* clear alpha to 0 or 1 */
132 int alpha_channel; /* index of the alpha component */
133 bool has_color = false;
134 bool has_alpha = false;
135
136 const struct util_format_description *desc =
137 util_format_description(si_simplify_cb_format(surface_format));
138
139 /* 128-bit fast clear with different R,G,B values is unsupported. */
140 if (desc->block.bits == 128 &&
141 (color->ui[0] != color->ui[1] ||
142 color->ui[0] != color->ui[2]))
143 return false;
144
145 *eliminate_needed = true;
146 *clear_value = 0x20202020U; /* use CB clear color registers */
147
148 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
149 return true; /* need ELIMINATE_FAST_CLEAR */
150
151 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
152 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
153
154 /* Formats with 3 channels can't have alpha. */
155 if (desc->nr_channels == 3)
156 alpha_channel = -1;
157 else if (surf_alpha_is_on_msb)
158 alpha_channel = desc->nr_channels - 1;
159 else
160 alpha_channel = 0;
161
162 for (int i = 0; i < 4; ++i) {
163 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
164 continue;
165
166 if (desc->channel[i].pure_integer &&
167 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
168 /* Use the maximum value for clamping the clear color. */
169 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
170
171 values[i] = color->i[i] != 0;
172 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
173 return true; /* need ELIMINATE_FAST_CLEAR */
174 } else if (desc->channel[i].pure_integer &&
175 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
176 /* Use the maximum value for clamping the clear color. */
177 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
178
179 values[i] = color->ui[i] != 0U;
180 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
181 return true; /* need ELIMINATE_FAST_CLEAR */
182 } else {
183 values[i] = color->f[i] != 0.0F;
184 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
185 return true; /* need ELIMINATE_FAST_CLEAR */
186 }
187
188 if (desc->swizzle[i] == alpha_channel) {
189 alpha_value = values[i];
190 has_alpha = true;
191 } else {
192 color_value = values[i];
193 has_color = true;
194 }
195 }
196
197 /* If alpha isn't present, make it the same as color, and vice versa. */
198 if (!has_alpha)
199 alpha_value = color_value;
200 else if (!has_color)
201 color_value = alpha_value;
202
203 if (color_value != alpha_value &&
204 base_alpha_is_on_msb != surf_alpha_is_on_msb)
205 return true; /* require ELIMINATE_FAST_CLEAR */
206
207 /* Check if all color values are equal if they are present. */
208 for (int i = 0; i < 4; ++i) {
209 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
210 desc->swizzle[i] != alpha_channel &&
211 values[i] != color_value)
212 return true; /* require ELIMINATE_FAST_CLEAR */
213 }
214
215 /* This doesn't need ELIMINATE_FAST_CLEAR.
216 * CB uses both the DCC clear codes and the CB clear color registers,
217 * so they must match.
218 */
219 *eliminate_needed = false;
220
221 if (color_value)
222 *clear_value |= 0x80808080U;
223 if (alpha_value)
224 *clear_value |= 0x40404040U;
225 return true;
226 }
227
228 void vi_dcc_clear_level(struct si_context *sctx,
229 struct si_texture *tex,
230 unsigned level, unsigned clear_value)
231 {
232 struct pipe_resource *dcc_buffer;
233 uint64_t dcc_offset, clear_size;
234
235 assert(vi_dcc_enabled(tex, level));
236
237 if (tex->dcc_separate_buffer) {
238 dcc_buffer = &tex->dcc_separate_buffer->b.b;
239 dcc_offset = 0;
240 } else {
241 dcc_buffer = &tex->buffer.b.b;
242 dcc_offset = tex->dcc_offset;
243 }
244
245 if (sctx->chip_class >= GFX9) {
246 /* Mipmap level clears aren't implemented. */
247 assert(tex->buffer.b.b.last_level == 0);
248 /* 4x and 8x MSAA needs a sophisticated compute shader for
249 * the clear. See AMDVLK. */
250 assert(tex->num_color_samples <= 2);
251 clear_size = tex->surface.dcc_size;
252 } else {
253 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
254
255 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
256 assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
257 /* Layered 4x and 8x MSAA DCC fast clears need to clear
258 * dcc_fast_clear_size bytes for each layer. A compute shader
259 * would be more efficient than separate per-layer clear operations.
260 */
261 assert(tex->num_color_samples <= 2 || num_layers == 1);
262
263 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
264 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
265 num_layers;
266 }
267
268 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
269 clear_value, SI_COHERENCY_CB_META);
270 }
271
272 /* Set the same micro tile mode as the destination of the last MSAA resolve.
273 * This allows hitting the MSAA resolve fast path, which requires that both
274 * src and dst micro tile modes match.
275 */
276 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
277 struct si_texture *tex)
278 {
279 if (tex->buffer.b.is_shared ||
280 tex->buffer.b.b.nr_samples <= 1 ||
281 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
282 return;
283
284 assert(sscreen->info.chip_class >= GFX9 ||
285 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
286 assert(tex->buffer.b.b.last_level == 0);
287
288 if (sscreen->info.chip_class >= GFX9) {
289 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
290 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
291
292 /* If you do swizzle_mode % 4, you'll get:
293 * 0 = Depth
294 * 1 = Standard,
295 * 2 = Displayable
296 * 3 = Rotated
297 *
298 * Depth-sample order isn't allowed:
299 */
300 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
301
302 switch (tex->last_msaa_resolve_target_micro_mode) {
303 case RADEON_MICRO_MODE_DISPLAY:
304 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
305 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
306 break;
307 case RADEON_MICRO_MODE_THIN:
308 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
309 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
310 break;
311 case RADEON_MICRO_MODE_ROTATED:
312 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
313 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
314 break;
315 default: /* depth */
316 assert(!"unexpected micro mode");
317 return;
318 }
319 } else if (sscreen->info.chip_class >= CIK) {
320 /* These magic numbers were copied from addrlib. It doesn't use
321 * any definitions for them either. They are all 2D_TILED_THIN1
322 * modes with different bpp and micro tile mode.
323 */
324 switch (tex->last_msaa_resolve_target_micro_mode) {
325 case RADEON_MICRO_MODE_DISPLAY:
326 tex->surface.u.legacy.tiling_index[0] = 10;
327 break;
328 case RADEON_MICRO_MODE_THIN:
329 tex->surface.u.legacy.tiling_index[0] = 14;
330 break;
331 case RADEON_MICRO_MODE_ROTATED:
332 tex->surface.u.legacy.tiling_index[0] = 28;
333 break;
334 default: /* depth, thick */
335 assert(!"unexpected micro mode");
336 return;
337 }
338 } else { /* SI */
339 switch (tex->last_msaa_resolve_target_micro_mode) {
340 case RADEON_MICRO_MODE_DISPLAY:
341 switch (tex->surface.bpe) {
342 case 1:
343 tex->surface.u.legacy.tiling_index[0] = 10;
344 break;
345 case 2:
346 tex->surface.u.legacy.tiling_index[0] = 11;
347 break;
348 default: /* 4, 8 */
349 tex->surface.u.legacy.tiling_index[0] = 12;
350 break;
351 }
352 break;
353 case RADEON_MICRO_MODE_THIN:
354 switch (tex->surface.bpe) {
355 case 1:
356 tex->surface.u.legacy.tiling_index[0] = 14;
357 break;
358 case 2:
359 tex->surface.u.legacy.tiling_index[0] = 15;
360 break;
361 case 4:
362 tex->surface.u.legacy.tiling_index[0] = 16;
363 break;
364 default: /* 8, 16 */
365 tex->surface.u.legacy.tiling_index[0] = 17;
366 break;
367 }
368 break;
369 default: /* depth, thick */
370 assert(!"unexpected micro mode");
371 return;
372 }
373 }
374
375 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
376
377 p_atomic_inc(&sscreen->dirty_tex_counter);
378 }
379
380 static void si_do_fast_color_clear(struct si_context *sctx,
381 unsigned *buffers,
382 const union pipe_color_union *color)
383 {
384 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
385 int i;
386
387 /* This function is broken in BE, so just disable this path for now */
388 #ifdef PIPE_ARCH_BIG_ENDIAN
389 return;
390 #endif
391
392 if (sctx->render_cond)
393 return;
394
395 for (i = 0; i < fb->nr_cbufs; i++) {
396 struct si_texture *tex;
397 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
398
399 if (!fb->cbufs[i])
400 continue;
401
402 /* if this colorbuffer is not being cleared */
403 if (!(*buffers & clear_bit))
404 continue;
405
406 unsigned level = fb->cbufs[i]->u.tex.level;
407 if (level > 0)
408 continue;
409
410 tex = (struct si_texture *)fb->cbufs[i]->texture;
411
412 /* TODO: GFX9: Implement DCC fast clear for level 0 of
413 * mipmapped textures. Mipmapped DCC has to clear a rectangular
414 * area of DCC for level 0 (because the whole miptree is
415 * organized in a 2D plane).
416 */
417 if (sctx->chip_class >= GFX9 &&
418 tex->buffer.b.b.last_level > 0)
419 continue;
420
421 /* the clear is allowed if all layers are bound */
422 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
423 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
424 continue;
425 }
426
427 /* only supported on tiled surfaces */
428 if (tex->surface.is_linear) {
429 continue;
430 }
431
432 /* shared textures can't use fast clear without an explicit flush,
433 * because there is no way to communicate the clear color among
434 * all clients
435 */
436 if (tex->buffer.b.is_shared &&
437 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
438 continue;
439
440 if (sctx->chip_class <= VI &&
441 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
442 !sctx->screen->info.htile_cmask_support_1d_tiling)
443 continue;
444
445 /* Fast clear is the most appropriate place to enable DCC for
446 * displayable surfaces.
447 */
448 if (sctx->chip_class >= VI &&
449 !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
450 vi_separate_dcc_try_enable(sctx, tex);
451
452 /* RB+ isn't supported with a CMASK clear only on Stoney,
453 * so all clears are considered to be hypothetically slow
454 * clears, which is weighed when determining whether to
455 * enable separate DCC.
456 */
457 if (tex->dcc_gather_statistics &&
458 sctx->family == CHIP_STONEY)
459 tex->num_slow_clears++;
460 }
461
462 bool need_decompress_pass = false;
463
464 /* Use a slow clear for small surfaces where the cost of
465 * the eliminate pass can be higher than the benefit of fast
466 * clear. The closed driver does this, but the numbers may differ.
467 *
468 * This helps on both dGPUs and APUs, even small APUs like Mullins.
469 */
470 bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
471 tex->buffer.b.b.width0 *
472 tex->buffer.b.b.height0 <= 512 * 512;
473
474 /* Try to clear DCC first, otherwise try CMASK. */
475 if (vi_dcc_enabled(tex, 0)) {
476 uint32_t reset_value;
477 bool eliminate_needed;
478
479 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
480 continue;
481
482 /* This can happen with mipmapping or MSAA. */
483 if (sctx->chip_class == VI &&
484 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
485 continue;
486
487 if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
488 fb->cbufs[i]->format,
489 color, &reset_value,
490 &eliminate_needed))
491 continue;
492
493 if (eliminate_needed && too_small)
494 continue;
495
496 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
497 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask.size) {
498 /* TODO: This doesn't work with MSAA. */
499 if (eliminate_needed)
500 continue;
501
502 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
503 tex->cmask.offset, tex->cmask.size,
504 0xCCCCCCCC, SI_COHERENCY_CB_META);
505 need_decompress_pass = true;
506 }
507
508 vi_dcc_clear_level(sctx, tex, 0, reset_value);
509
510 if (eliminate_needed)
511 need_decompress_pass = true;
512
513 tex->separate_dcc_dirty = true;
514 } else {
515 if (too_small)
516 continue;
517
518 /* 128-bit formats are unusupported */
519 if (tex->surface.bpe > 8) {
520 continue;
521 }
522
523 /* RB+ doesn't work with CMASK fast clear on Stoney. */
524 if (sctx->family == CHIP_STONEY)
525 continue;
526
527 /* ensure CMASK is enabled */
528 si_alloc_separate_cmask(sctx->screen, tex);
529 if (tex->cmask.size == 0) {
530 continue;
531 }
532
533 /* Do the fast clear. */
534 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
535 tex->cmask.offset, tex->cmask.size, 0,
536 SI_COHERENCY_CB_META);
537 need_decompress_pass = true;
538 }
539
540 if (need_decompress_pass &&
541 !(tex->dirty_level_mask & (1 << level))) {
542 tex->dirty_level_mask |= 1 << level;
543 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
544 }
545
546 /* We can change the micro tile mode before a full clear. */
547 si_set_optimal_micro_tile_mode(sctx->screen, tex);
548
549 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
550 sctx->framebuffer.dirty_cbufs |= 1 << i;
551 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
552 }
553 *buffers &= ~clear_bit;
554 }
555 }
556
557 static void si_clear(struct pipe_context *ctx, unsigned buffers,
558 const union pipe_color_union *color,
559 double depth, unsigned stencil)
560 {
561 struct si_context *sctx = (struct si_context *)ctx;
562 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
563 struct pipe_surface *zsbuf = fb->zsbuf;
564 struct si_texture *zstex =
565 zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
566
567 if (buffers & PIPE_CLEAR_COLOR) {
568 si_do_fast_color_clear(sctx, &buffers, color);
569 if (!buffers)
570 return; /* all buffers have been fast cleared */
571
572 /* These buffers cannot use fast clear, make sure to disable expansion. */
573 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
574 struct si_texture *tex;
575
576 /* If not clearing this buffer, skip. */
577 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
578 continue;
579
580 tex = (struct si_texture *)fb->cbufs[i]->texture;
581 if (tex->surface.fmask_size == 0)
582 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
583 }
584 }
585
586 if (zstex &&
587 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
588 zsbuf->u.tex.first_layer == 0 &&
589 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
590 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
591 if (buffers & PIPE_CLEAR_DEPTH &&
592 (!zstex->tc_compatible_htile ||
593 depth == 0 || depth == 1)) {
594 /* Need to disable EXPCLEAR temporarily if clearing
595 * to a new value. */
596 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
597 sctx->db_depth_disable_expclear = true;
598 }
599
600 if (zstex->depth_clear_value != (float)depth) {
601 /* Update DB_DEPTH_CLEAR. */
602 zstex->depth_clear_value = depth;
603 sctx->framebuffer.dirty_zsbuf = true;
604 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
605 }
606 sctx->db_depth_clear = true;
607 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
608 }
609
610 /* TC-compatible HTILE only supports stencil clears to 0. */
611 if (buffers & PIPE_CLEAR_STENCIL &&
612 (!zstex->tc_compatible_htile || stencil == 0)) {
613 stencil &= 0xff;
614
615 /* Need to disable EXPCLEAR temporarily if clearing
616 * to a new value. */
617 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
618 sctx->db_stencil_disable_expclear = true;
619 }
620
621 if (zstex->stencil_clear_value != (uint8_t)stencil) {
622 /* Update DB_STENCIL_CLEAR. */
623 zstex->stencil_clear_value = stencil;
624 sctx->framebuffer.dirty_zsbuf = true;
625 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
626 }
627 sctx->db_stencil_clear = true;
628 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
629 }
630
631 /* TODO: Find out what's wrong here. Fast depth clear leads to
632 * corruption in ARK: Survival Evolved, but that may just be
633 * a coincidence and the root cause is elsewhere.
634 *
635 * The corruption can be fixed by putting the DB flush before
636 * or after the depth clear. (surprisingly)
637 *
638 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
639 *
640 * This hack decreases back-to-back ClearDepth performance.
641 */
642 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
643 sctx->screen->clear_db_cache_before_clear)
644 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
645 }
646
647 si_blitter_begin(sctx, SI_CLEAR);
648 util_blitter_clear(sctx->blitter, fb->width, fb->height,
649 util_framebuffer_get_num_layers(fb),
650 buffers, color, depth, stencil);
651 si_blitter_end(sctx);
652
653 if (sctx->db_depth_clear) {
654 sctx->db_depth_clear = false;
655 sctx->db_depth_disable_expclear = false;
656 zstex->depth_cleared = true;
657 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
658 }
659
660 if (sctx->db_stencil_clear) {
661 sctx->db_stencil_clear = false;
662 sctx->db_stencil_disable_expclear = false;
663 zstex->stencil_cleared = true;
664 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
665 }
666 }
667
668 static void si_clear_render_target(struct pipe_context *ctx,
669 struct pipe_surface *dst,
670 const union pipe_color_union *color,
671 unsigned dstx, unsigned dsty,
672 unsigned width, unsigned height,
673 bool render_condition_enabled)
674 {
675 struct si_context *sctx = (struct si_context *)ctx;
676
677 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
678 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
679 util_blitter_clear_render_target(sctx->blitter, dst, color,
680 dstx, dsty, width, height);
681 si_blitter_end(sctx);
682 }
683
684 static void si_clear_depth_stencil(struct pipe_context *ctx,
685 struct pipe_surface *dst,
686 unsigned clear_flags,
687 double depth,
688 unsigned stencil,
689 unsigned dstx, unsigned dsty,
690 unsigned width, unsigned height,
691 bool render_condition_enabled)
692 {
693 struct si_context *sctx = (struct si_context *)ctx;
694
695 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
696 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
697 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
698 dstx, dsty, width, height);
699 si_blitter_end(sctx);
700 }
701
702 static void si_clear_texture(struct pipe_context *pipe,
703 struct pipe_resource *tex,
704 unsigned level,
705 const struct pipe_box *box,
706 const void *data)
707 {
708 struct pipe_screen *screen = pipe->screen;
709 struct si_texture *stex = (struct si_texture*)tex;
710 struct pipe_surface tmpl = {{0}};
711 struct pipe_surface *sf;
712 const struct util_format_description *desc =
713 util_format_description(tex->format);
714
715 tmpl.format = tex->format;
716 tmpl.u.tex.first_layer = box->z;
717 tmpl.u.tex.last_layer = box->z + box->depth - 1;
718 tmpl.u.tex.level = level;
719 sf = pipe->create_surface(pipe, tex, &tmpl);
720 if (!sf)
721 return;
722
723 if (stex->is_depth) {
724 unsigned clear;
725 float depth;
726 uint8_t stencil = 0;
727
728 /* Depth is always present. */
729 clear = PIPE_CLEAR_DEPTH;
730 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
731
732 if (stex->surface.has_stencil) {
733 clear |= PIPE_CLEAR_STENCIL;
734 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
735 }
736
737 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
738 box->x, box->y,
739 box->width, box->height, false);
740 } else {
741 union pipe_color_union color;
742
743 /* pipe_color_union requires the full vec4 representation. */
744 if (util_format_is_pure_uint(tex->format))
745 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
746 else if (util_format_is_pure_sint(tex->format))
747 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
748 else
749 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
750
751 if (screen->is_format_supported(screen, tex->format,
752 tex->target, 0,
753 PIPE_BIND_RENDER_TARGET)) {
754 si_clear_render_target(pipe, sf, &color,
755 box->x, box->y,
756 box->width, box->height, false);
757 } else {
758 /* Software fallback - just for R9G9B9E5_FLOAT */
759 util_clear_render_target(pipe, sf, &color,
760 box->x, box->y,
761 box->width, box->height);
762 }
763 }
764 pipe_surface_reference(&sf, NULL);
765 }
766
767 void si_init_clear_functions(struct si_context *sctx)
768 {
769 sctx->b.clear = si_clear;
770 sctx->b.clear_render_target = si_clear_render_target;
771 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
772 sctx->b.clear_texture = si_clear_texture;
773 }