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radeonsi: use si_set_rw_shader_buffer for setting streamout buffers
[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 enum si_dcc_clear_code
38 {
39 DCC_CLEAR_COLOR_0000 = 0x00000000,
40 DCC_CLEAR_COLOR_0001 = 0x40404040,
41 DCC_CLEAR_COLOR_1110 = 0x80808080,
42 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
43 DCC_CLEAR_COLOR_REG = 0x20202020,
44 };
45
46 static void si_alloc_separate_cmask(struct si_screen *sscreen,
47 struct si_texture *tex)
48 {
49 if (tex->cmask_buffer || !tex->surface.cmask_size)
50 return;
51
52 tex->cmask_buffer =
53 si_aligned_buffer_create(&sscreen->b,
54 SI_RESOURCE_FLAG_UNMAPPABLE,
55 PIPE_USAGE_DEFAULT,
56 tex->surface.cmask_size,
57 tex->surface.cmask_alignment);
58 if (tex->cmask_buffer == NULL)
59 return;
60
61 tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
62 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
63
64 p_atomic_inc(&sscreen->compressed_colortex_counter);
65 }
66
67 static bool si_set_clear_color(struct si_texture *tex,
68 enum pipe_format surface_format,
69 const union pipe_color_union *color)
70 {
71 union util_color uc;
72
73 memset(&uc, 0, sizeof(uc));
74
75 if (tex->surface.bpe == 16) {
76 /* DCC fast clear only:
77 * CLEAR_WORD0 = R = G = B
78 * CLEAR_WORD1 = A
79 */
80 assert(color->ui[0] == color->ui[1] &&
81 color->ui[0] == color->ui[2]);
82 uc.ui[0] = color->ui[0];
83 uc.ui[1] = color->ui[3];
84 } else if (util_format_is_pure_uint(surface_format)) {
85 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
86 } else if (util_format_is_pure_sint(surface_format)) {
87 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
88 } else {
89 util_pack_color(color->f, surface_format, &uc);
90 }
91
92 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
93 return false;
94
95 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
96 return true;
97 }
98
99 /** Linearize and convert luminace/intensity to red. */
100 enum pipe_format si_simplify_cb_format(enum pipe_format format)
101 {
102 format = util_format_linear(format);
103 format = util_format_luminance_to_red(format);
104 return util_format_intensity_to_red(format);
105 }
106
107 bool vi_alpha_is_on_msb(enum pipe_format format)
108 {
109 format = si_simplify_cb_format(format);
110
111 /* Formats with 3 channels can't have alpha. */
112 if (util_format_description(format)->nr_channels == 3)
113 return true; /* same as xxxA; is any value OK here? */
114
115 return si_translate_colorswap(format, false) <= 1;
116 }
117
118 static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
119 enum pipe_format surface_format,
120 const union pipe_color_union *color,
121 uint32_t* clear_value,
122 bool *eliminate_needed)
123 {
124 /* If we want to clear without needing a fast clear eliminate step, we
125 * can set color and alpha independently to 0 or 1 (or 0/max for integer
126 * formats).
127 */
128 bool values[4] = {}; /* whether to clear to 0 or 1 */
129 bool color_value = false; /* clear color to 0 or 1 */
130 bool alpha_value = false; /* clear alpha to 0 or 1 */
131 int alpha_channel; /* index of the alpha component */
132 bool has_color = false;
133 bool has_alpha = false;
134
135 const struct util_format_description *desc =
136 util_format_description(si_simplify_cb_format(surface_format));
137
138 /* 128-bit fast clear with different R,G,B values is unsupported. */
139 if (desc->block.bits == 128 &&
140 (color->ui[0] != color->ui[1] ||
141 color->ui[0] != color->ui[2]))
142 return false;
143
144 *eliminate_needed = true;
145 *clear_value = DCC_CLEAR_COLOR_REG;
146
147 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
148 return true; /* need ELIMINATE_FAST_CLEAR */
149
150 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
151 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
152
153 /* Formats with 3 channels can't have alpha. */
154 if (desc->nr_channels == 3)
155 alpha_channel = -1;
156 else if (surf_alpha_is_on_msb)
157 alpha_channel = desc->nr_channels - 1;
158 else
159 alpha_channel = 0;
160
161 for (int i = 0; i < 4; ++i) {
162 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
163 continue;
164
165 if (desc->channel[i].pure_integer &&
166 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
167 /* Use the maximum value for clamping the clear color. */
168 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
169
170 values[i] = color->i[i] != 0;
171 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
172 return true; /* need ELIMINATE_FAST_CLEAR */
173 } else if (desc->channel[i].pure_integer &&
174 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
175 /* Use the maximum value for clamping the clear color. */
176 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
177
178 values[i] = color->ui[i] != 0U;
179 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
180 return true; /* need ELIMINATE_FAST_CLEAR */
181 } else {
182 values[i] = color->f[i] != 0.0F;
183 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
184 return true; /* need ELIMINATE_FAST_CLEAR */
185 }
186
187 if (desc->swizzle[i] == alpha_channel) {
188 alpha_value = values[i];
189 has_alpha = true;
190 } else {
191 color_value = values[i];
192 has_color = true;
193 }
194 }
195
196 /* If alpha isn't present, make it the same as color, and vice versa. */
197 if (!has_alpha)
198 alpha_value = color_value;
199 else if (!has_color)
200 color_value = alpha_value;
201
202 if (color_value != alpha_value &&
203 base_alpha_is_on_msb != surf_alpha_is_on_msb)
204 return true; /* require ELIMINATE_FAST_CLEAR */
205
206 /* Check if all color values are equal if they are present. */
207 for (int i = 0; i < 4; ++i) {
208 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
209 desc->swizzle[i] != alpha_channel &&
210 values[i] != color_value)
211 return true; /* require ELIMINATE_FAST_CLEAR */
212 }
213
214 /* This doesn't need ELIMINATE_FAST_CLEAR.
215 * On chips predating Raven2, the DCC clear codes and the CB clear
216 * color registers must match.
217 */
218 *eliminate_needed = false;
219
220 if (color_value) {
221 if (alpha_value)
222 *clear_value = DCC_CLEAR_COLOR_1111;
223 else
224 *clear_value = DCC_CLEAR_COLOR_1110;
225 } else {
226 if (alpha_value)
227 *clear_value = DCC_CLEAR_COLOR_0001;
228 else
229 *clear_value = DCC_CLEAR_COLOR_0000;
230 }
231 return true;
232 }
233
234 void vi_dcc_clear_level(struct si_context *sctx,
235 struct si_texture *tex,
236 unsigned level, unsigned clear_value)
237 {
238 struct pipe_resource *dcc_buffer;
239 uint64_t dcc_offset, clear_size;
240
241 assert(vi_dcc_enabled(tex, level));
242
243 if (tex->dcc_separate_buffer) {
244 dcc_buffer = &tex->dcc_separate_buffer->b.b;
245 dcc_offset = 0;
246 } else {
247 dcc_buffer = &tex->buffer.b.b;
248 dcc_offset = tex->dcc_offset;
249 }
250
251 if (sctx->chip_class >= GFX9) {
252 /* Mipmap level clears aren't implemented. */
253 assert(tex->buffer.b.b.last_level == 0);
254 /* 4x and 8x MSAA needs a sophisticated compute shader for
255 * the clear. See AMDVLK. */
256 assert(tex->buffer.b.b.nr_storage_samples <= 2);
257 clear_size = tex->surface.dcc_size;
258 } else {
259 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
260
261 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
262 assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
263 /* Layered 4x and 8x MSAA DCC fast clears need to clear
264 * dcc_fast_clear_size bytes for each layer. A compute shader
265 * would be more efficient than separate per-layer clear operations.
266 */
267 assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
268
269 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
270 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
271 num_layers;
272 }
273
274 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
275 &clear_value, 4, SI_COHERENCY_CB_META);
276 }
277
278 /* Set the same micro tile mode as the destination of the last MSAA resolve.
279 * This allows hitting the MSAA resolve fast path, which requires that both
280 * src and dst micro tile modes match.
281 */
282 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
283 struct si_texture *tex)
284 {
285 if (tex->buffer.b.is_shared ||
286 tex->buffer.b.b.nr_samples <= 1 ||
287 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
288 return;
289
290 assert(sscreen->info.chip_class >= GFX9 ||
291 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
292 assert(tex->buffer.b.b.last_level == 0);
293
294 if (sscreen->info.chip_class >= GFX9) {
295 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
296 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
297
298 /* If you do swizzle_mode % 4, you'll get:
299 * 0 = Depth
300 * 1 = Standard,
301 * 2 = Displayable
302 * 3 = Rotated
303 *
304 * Depth-sample order isn't allowed:
305 */
306 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
307
308 switch (tex->last_msaa_resolve_target_micro_mode) {
309 case RADEON_MICRO_MODE_DISPLAY:
310 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
311 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
312 break;
313 case RADEON_MICRO_MODE_THIN:
314 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
315 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
316 break;
317 case RADEON_MICRO_MODE_ROTATED:
318 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
319 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
320 break;
321 default: /* depth */
322 assert(!"unexpected micro mode");
323 return;
324 }
325 } else if (sscreen->info.chip_class >= CIK) {
326 /* These magic numbers were copied from addrlib. It doesn't use
327 * any definitions for them either. They are all 2D_TILED_THIN1
328 * modes with different bpp and micro tile mode.
329 */
330 switch (tex->last_msaa_resolve_target_micro_mode) {
331 case RADEON_MICRO_MODE_DISPLAY:
332 tex->surface.u.legacy.tiling_index[0] = 10;
333 break;
334 case RADEON_MICRO_MODE_THIN:
335 tex->surface.u.legacy.tiling_index[0] = 14;
336 break;
337 case RADEON_MICRO_MODE_ROTATED:
338 tex->surface.u.legacy.tiling_index[0] = 28;
339 break;
340 default: /* depth, thick */
341 assert(!"unexpected micro mode");
342 return;
343 }
344 } else { /* SI */
345 switch (tex->last_msaa_resolve_target_micro_mode) {
346 case RADEON_MICRO_MODE_DISPLAY:
347 switch (tex->surface.bpe) {
348 case 1:
349 tex->surface.u.legacy.tiling_index[0] = 10;
350 break;
351 case 2:
352 tex->surface.u.legacy.tiling_index[0] = 11;
353 break;
354 default: /* 4, 8 */
355 tex->surface.u.legacy.tiling_index[0] = 12;
356 break;
357 }
358 break;
359 case RADEON_MICRO_MODE_THIN:
360 switch (tex->surface.bpe) {
361 case 1:
362 tex->surface.u.legacy.tiling_index[0] = 14;
363 break;
364 case 2:
365 tex->surface.u.legacy.tiling_index[0] = 15;
366 break;
367 case 4:
368 tex->surface.u.legacy.tiling_index[0] = 16;
369 break;
370 default: /* 8, 16 */
371 tex->surface.u.legacy.tiling_index[0] = 17;
372 break;
373 }
374 break;
375 default: /* depth, thick */
376 assert(!"unexpected micro mode");
377 return;
378 }
379 }
380
381 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
382
383 p_atomic_inc(&sscreen->dirty_tex_counter);
384 }
385
386 static void si_do_fast_color_clear(struct si_context *sctx,
387 unsigned *buffers,
388 const union pipe_color_union *color)
389 {
390 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
391 int i;
392
393 /* This function is broken in BE, so just disable this path for now */
394 #ifdef PIPE_ARCH_BIG_ENDIAN
395 return;
396 #endif
397
398 if (sctx->render_cond)
399 return;
400
401 for (i = 0; i < fb->nr_cbufs; i++) {
402 struct si_texture *tex;
403 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
404
405 if (!fb->cbufs[i])
406 continue;
407
408 /* if this colorbuffer is not being cleared */
409 if (!(*buffers & clear_bit))
410 continue;
411
412 unsigned level = fb->cbufs[i]->u.tex.level;
413 if (level > 0)
414 continue;
415
416 tex = (struct si_texture *)fb->cbufs[i]->texture;
417
418 /* TODO: GFX9: Implement DCC fast clear for level 0 of
419 * mipmapped textures. Mipmapped DCC has to clear a rectangular
420 * area of DCC for level 0 (because the whole miptree is
421 * organized in a 2D plane).
422 */
423 if (sctx->chip_class >= GFX9 &&
424 tex->buffer.b.b.last_level > 0)
425 continue;
426
427 /* the clear is allowed if all layers are bound */
428 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
429 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
430 continue;
431 }
432
433 /* only supported on tiled surfaces */
434 if (tex->surface.is_linear) {
435 continue;
436 }
437
438 /* shared textures can't use fast clear without an explicit flush,
439 * because there is no way to communicate the clear color among
440 * all clients
441 */
442 if (tex->buffer.b.is_shared &&
443 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
444 continue;
445
446 if (sctx->chip_class <= VI &&
447 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
448 !sctx->screen->info.htile_cmask_support_1d_tiling)
449 continue;
450
451 /* Use a slow clear for small surfaces where the cost of
452 * the eliminate pass can be higher than the benefit of fast
453 * clear. The closed driver does this, but the numbers may differ.
454 *
455 * This helps on both dGPUs and APUs, even small APUs like Mullins.
456 */
457 bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
458 tex->buffer.b.b.width0 *
459 tex->buffer.b.b.height0 <= 512 * 512;
460 bool eliminate_needed = false;
461 bool fmask_decompress_needed = false;
462
463 /* Fast clear is the most appropriate place to enable DCC for
464 * displayable surfaces.
465 */
466 if (sctx->family == CHIP_STONEY && !too_small) {
467 vi_separate_dcc_try_enable(sctx, tex);
468
469 /* RB+ isn't supported with a CMASK clear only on Stoney,
470 * so all clears are considered to be hypothetically slow
471 * clears, which is weighed when determining whether to
472 * enable separate DCC.
473 */
474 if (tex->dcc_gather_statistics) /* only for Stoney */
475 tex->num_slow_clears++;
476 }
477
478 /* Try to clear DCC first, otherwise try CMASK. */
479 if (vi_dcc_enabled(tex, 0)) {
480 uint32_t reset_value;
481
482 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
483 continue;
484
485 /* This can happen with mipmapping or MSAA. */
486 if (sctx->chip_class == VI &&
487 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
488 continue;
489
490 if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
491 fb->cbufs[i]->format,
492 color, &reset_value,
493 &eliminate_needed))
494 continue;
495
496 if (eliminate_needed && too_small)
497 continue;
498
499 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
500 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
501 /* TODO: This doesn't work with MSAA. */
502 if (eliminate_needed)
503 continue;
504
505 uint32_t clear_value = 0xCCCCCCCC;
506 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
507 tex->cmask_offset, tex->surface.cmask_size,
508 &clear_value, 4, SI_COHERENCY_CB_META);
509 fmask_decompress_needed = true;
510 }
511
512 vi_dcc_clear_level(sctx, tex, 0, reset_value);
513 tex->separate_dcc_dirty = true;
514 } else {
515 if (too_small)
516 continue;
517
518 /* 128-bit formats are unusupported */
519 if (tex->surface.bpe > 8) {
520 continue;
521 }
522
523 /* RB+ doesn't work with CMASK fast clear on Stoney. */
524 if (sctx->family == CHIP_STONEY)
525 continue;
526
527 /* ensure CMASK is enabled */
528 si_alloc_separate_cmask(sctx->screen, tex);
529 if (!tex->cmask_buffer)
530 continue;
531
532 /* Do the fast clear. */
533 uint32_t clear_value = 0;
534 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
535 tex->cmask_offset, tex->surface.cmask_size,
536 &clear_value, 4, SI_COHERENCY_CB_META);
537 eliminate_needed = true;
538 }
539
540 if ((eliminate_needed || fmask_decompress_needed) &&
541 !(tex->dirty_level_mask & (1 << level))) {
542 tex->dirty_level_mask |= 1 << level;
543 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
544 }
545
546 /* We can change the micro tile mode before a full clear. */
547 si_set_optimal_micro_tile_mode(sctx->screen, tex);
548
549 *buffers &= ~clear_bit;
550
551 /* Chips with DCC constant encoding don't need to set the clear
552 * color registers for DCC clear values 0 and 1.
553 */
554 if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
555 continue;
556
557 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
558 sctx->framebuffer.dirty_cbufs |= 1 << i;
559 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
560 }
561 }
562 }
563
564 static void si_clear(struct pipe_context *ctx, unsigned buffers,
565 const union pipe_color_union *color,
566 double depth, unsigned stencil)
567 {
568 struct si_context *sctx = (struct si_context *)ctx;
569 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
570 struct pipe_surface *zsbuf = fb->zsbuf;
571 struct si_texture *zstex =
572 zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
573
574 if (buffers & PIPE_CLEAR_COLOR) {
575 si_do_fast_color_clear(sctx, &buffers, color);
576 if (!buffers)
577 return; /* all buffers have been fast cleared */
578
579 /* These buffers cannot use fast clear, make sure to disable expansion. */
580 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
581 struct si_texture *tex;
582
583 /* If not clearing this buffer, skip. */
584 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
585 continue;
586
587 tex = (struct si_texture *)fb->cbufs[i]->texture;
588 if (tex->surface.fmask_size == 0)
589 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
590 }
591 }
592
593 if (zstex &&
594 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
595 zsbuf->u.tex.first_layer == 0 &&
596 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
597 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
598 if (buffers & PIPE_CLEAR_DEPTH &&
599 (!zstex->tc_compatible_htile ||
600 depth == 0 || depth == 1)) {
601 /* Need to disable EXPCLEAR temporarily if clearing
602 * to a new value. */
603 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
604 sctx->db_depth_disable_expclear = true;
605 }
606
607 if (zstex->depth_clear_value != (float)depth) {
608 /* Update DB_DEPTH_CLEAR. */
609 zstex->depth_clear_value = depth;
610 sctx->framebuffer.dirty_zsbuf = true;
611 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
612 }
613 sctx->db_depth_clear = true;
614 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
615 }
616
617 /* TC-compatible HTILE only supports stencil clears to 0. */
618 if (buffers & PIPE_CLEAR_STENCIL &&
619 (!zstex->tc_compatible_htile || stencil == 0)) {
620 stencil &= 0xff;
621
622 /* Need to disable EXPCLEAR temporarily if clearing
623 * to a new value. */
624 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
625 sctx->db_stencil_disable_expclear = true;
626 }
627
628 if (zstex->stencil_clear_value != (uint8_t)stencil) {
629 /* Update DB_STENCIL_CLEAR. */
630 zstex->stencil_clear_value = stencil;
631 sctx->framebuffer.dirty_zsbuf = true;
632 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
633 }
634 sctx->db_stencil_clear = true;
635 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
636 }
637
638 /* TODO: Find out what's wrong here. Fast depth clear leads to
639 * corruption in ARK: Survival Evolved, but that may just be
640 * a coincidence and the root cause is elsewhere.
641 *
642 * The corruption can be fixed by putting the DB flush before
643 * or after the depth clear. (surprisingly)
644 *
645 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
646 *
647 * This hack decreases back-to-back ClearDepth performance.
648 */
649 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
650 sctx->screen->clear_db_cache_before_clear)
651 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
652 }
653
654 si_blitter_begin(sctx, SI_CLEAR);
655 util_blitter_clear(sctx->blitter, fb->width, fb->height,
656 util_framebuffer_get_num_layers(fb),
657 buffers, color, depth, stencil);
658 si_blitter_end(sctx);
659
660 if (sctx->db_depth_clear) {
661 sctx->db_depth_clear = false;
662 sctx->db_depth_disable_expclear = false;
663 zstex->depth_cleared = true;
664 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
665 }
666
667 if (sctx->db_stencil_clear) {
668 sctx->db_stencil_clear = false;
669 sctx->db_stencil_disable_expclear = false;
670 zstex->stencil_cleared = true;
671 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
672 }
673 }
674
675 static void si_clear_render_target(struct pipe_context *ctx,
676 struct pipe_surface *dst,
677 const union pipe_color_union *color,
678 unsigned dstx, unsigned dsty,
679 unsigned width, unsigned height,
680 bool render_condition_enabled)
681 {
682 struct si_context *sctx = (struct si_context *)ctx;
683
684 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
685 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
686 util_blitter_clear_render_target(sctx->blitter, dst, color,
687 dstx, dsty, width, height);
688 si_blitter_end(sctx);
689 }
690
691 static void si_clear_depth_stencil(struct pipe_context *ctx,
692 struct pipe_surface *dst,
693 unsigned clear_flags,
694 double depth,
695 unsigned stencil,
696 unsigned dstx, unsigned dsty,
697 unsigned width, unsigned height,
698 bool render_condition_enabled)
699 {
700 struct si_context *sctx = (struct si_context *)ctx;
701
702 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
703 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
704 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
705 dstx, dsty, width, height);
706 si_blitter_end(sctx);
707 }
708
709 static void si_clear_texture(struct pipe_context *pipe,
710 struct pipe_resource *tex,
711 unsigned level,
712 const struct pipe_box *box,
713 const void *data)
714 {
715 struct pipe_screen *screen = pipe->screen;
716 struct si_texture *stex = (struct si_texture*)tex;
717 struct pipe_surface tmpl = {{0}};
718 struct pipe_surface *sf;
719 const struct util_format_description *desc =
720 util_format_description(tex->format);
721
722 tmpl.format = tex->format;
723 tmpl.u.tex.first_layer = box->z;
724 tmpl.u.tex.last_layer = box->z + box->depth - 1;
725 tmpl.u.tex.level = level;
726 sf = pipe->create_surface(pipe, tex, &tmpl);
727 if (!sf)
728 return;
729
730 if (stex->is_depth) {
731 unsigned clear;
732 float depth;
733 uint8_t stencil = 0;
734
735 /* Depth is always present. */
736 clear = PIPE_CLEAR_DEPTH;
737 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
738
739 if (stex->surface.has_stencil) {
740 clear |= PIPE_CLEAR_STENCIL;
741 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
742 }
743
744 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
745 box->x, box->y,
746 box->width, box->height, false);
747 } else {
748 union pipe_color_union color;
749
750 /* pipe_color_union requires the full vec4 representation. */
751 if (util_format_is_pure_uint(tex->format))
752 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
753 else if (util_format_is_pure_sint(tex->format))
754 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
755 else
756 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
757
758 if (screen->is_format_supported(screen, tex->format,
759 tex->target, 0, 0,
760 PIPE_BIND_RENDER_TARGET)) {
761 si_clear_render_target(pipe, sf, &color,
762 box->x, box->y,
763 box->width, box->height, false);
764 } else {
765 /* Software fallback - just for R9G9B9E5_FLOAT */
766 util_clear_render_target(pipe, sf, &color,
767 box->x, box->y,
768 box->width, box->height);
769 }
770 }
771 pipe_surface_reference(&sf, NULL);
772 }
773
774 void si_init_clear_functions(struct si_context *sctx)
775 {
776 sctx->b.clear = si_clear;
777 sctx->b.clear_render_target = si_clear_render_target;
778 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
779 sctx->b.clear_texture = si_clear_texture;
780 }