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[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct r600_texture *rtex)
39 {
40 if (rtex->cmask_buffer)
41 return;
42
43 assert(rtex->cmask.size == 0);
44
45 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
46 if (!rtex->cmask.size)
47 return;
48
49 rtex->cmask_buffer = (struct r600_resource *)
50 si_aligned_buffer_create(&sscreen->b,
51 SI_RESOURCE_FLAG_UNMAPPABLE,
52 PIPE_USAGE_DEFAULT,
53 rtex->cmask.size,
54 rtex->cmask.alignment);
55 if (rtex->cmask_buffer == NULL) {
56 rtex->cmask.size = 0;
57 return;
58 }
59
60 /* update colorbuffer state bits */
61 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
62
63 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
64
65 p_atomic_inc(&sscreen->compressed_colortex_counter);
66 }
67
68 static void si_set_clear_color(struct r600_texture *rtex,
69 enum pipe_format surface_format,
70 const union pipe_color_union *color)
71 {
72 union util_color uc;
73
74 memset(&uc, 0, sizeof(uc));
75
76 if (rtex->surface.bpe == 16) {
77 /* DCC fast clear only:
78 * CLEAR_WORD0 = R = G = B
79 * CLEAR_WORD1 = A
80 */
81 assert(color->ui[0] == color->ui[1] &&
82 color->ui[0] == color->ui[2]);
83 uc.ui[0] = color->ui[0];
84 uc.ui[1] = color->ui[3];
85 } else if (util_format_is_pure_uint(surface_format)) {
86 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
87 } else if (util_format_is_pure_sint(surface_format)) {
88 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
89 } else {
90 util_pack_color(color->f, surface_format, &uc);
91 }
92
93 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
94 }
95
96 /** Linearize and convert luminace/intensity to red. */
97 enum pipe_format si_simplify_cb_format(enum pipe_format format)
98 {
99 format = util_format_linear(format);
100 format = util_format_luminance_to_red(format);
101 return util_format_intensity_to_red(format);
102 }
103
104 bool vi_alpha_is_on_msb(enum pipe_format format)
105 {
106 format = si_simplify_cb_format(format);
107
108 /* Formats with 3 channels can't have alpha. */
109 if (util_format_description(format)->nr_channels == 3)
110 return true; /* same as xxxA; is any value OK here? */
111
112 return si_translate_colorswap(format, false) <= 1;
113 }
114
115 static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
116 enum pipe_format surface_format,
117 const union pipe_color_union *color,
118 uint32_t* clear_value,
119 bool *eliminate_needed)
120 {
121 /* If we want to clear without needing a fast clear eliminate step, we
122 * can set color and alpha independently to 0 or 1 (or 0/max for integer
123 * formats).
124 */
125 bool values[4] = {}; /* whether to clear to 0 or 1 */
126 bool color_value = false; /* clear color to 0 or 1 */
127 bool alpha_value = false; /* clear alpha to 0 or 1 */
128 int alpha_channel; /* index of the alpha component */
129 bool has_color = false;
130 bool has_alpha = false;
131
132 const struct util_format_description *desc =
133 util_format_description(si_simplify_cb_format(surface_format));
134
135 /* 128-bit fast clear with different R,G,B values is unsupported. */
136 if (desc->block.bits == 128 &&
137 (color->ui[0] != color->ui[1] ||
138 color->ui[0] != color->ui[2]))
139 return false;
140
141 *eliminate_needed = true;
142 *clear_value = 0x20202020U; /* use CB clear color registers */
143
144 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
145 return true; /* need ELIMINATE_FAST_CLEAR */
146
147 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
148 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
149
150 /* Formats with 3 channels can't have alpha. */
151 if (desc->nr_channels == 3)
152 alpha_channel = -1;
153 else if (surf_alpha_is_on_msb)
154 alpha_channel = desc->nr_channels - 1;
155 else
156 alpha_channel = 0;
157
158 for (int i = 0; i < 4; ++i) {
159 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
160 continue;
161
162 if (desc->channel[i].pure_integer &&
163 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
164 /* Use the maximum value for clamping the clear color. */
165 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
166
167 values[i] = color->i[i] != 0;
168 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
169 return true; /* need ELIMINATE_FAST_CLEAR */
170 } else if (desc->channel[i].pure_integer &&
171 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
172 /* Use the maximum value for clamping the clear color. */
173 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
174
175 values[i] = color->ui[i] != 0U;
176 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
177 return true; /* need ELIMINATE_FAST_CLEAR */
178 } else {
179 values[i] = color->f[i] != 0.0F;
180 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
181 return true; /* need ELIMINATE_FAST_CLEAR */
182 }
183
184 if (desc->swizzle[i] == alpha_channel) {
185 alpha_value = values[i];
186 has_alpha = true;
187 } else {
188 color_value = values[i];
189 has_color = true;
190 }
191 }
192
193 /* If alpha isn't present, make it the same as color, and vice versa. */
194 if (!has_alpha)
195 alpha_value = color_value;
196 else if (!has_color)
197 color_value = alpha_value;
198
199 if (color_value != alpha_value &&
200 base_alpha_is_on_msb != surf_alpha_is_on_msb)
201 return true; /* require ELIMINATE_FAST_CLEAR */
202
203 /* Check if all color values are equal if they are present. */
204 for (int i = 0; i < 4; ++i) {
205 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
206 desc->swizzle[i] != alpha_channel &&
207 values[i] != color_value)
208 return true; /* require ELIMINATE_FAST_CLEAR */
209 }
210
211 /* This doesn't need ELIMINATE_FAST_CLEAR.
212 * CB uses both the DCC clear codes and the CB clear color registers,
213 * so they must match.
214 */
215 *eliminate_needed = false;
216
217 if (color_value)
218 *clear_value |= 0x80808080U;
219 if (alpha_value)
220 *clear_value |= 0x40404040U;
221 return true;
222 }
223
224 void vi_dcc_clear_level(struct si_context *sctx,
225 struct r600_texture *rtex,
226 unsigned level, unsigned clear_value)
227 {
228 struct pipe_resource *dcc_buffer;
229 uint64_t dcc_offset, clear_size;
230
231 assert(vi_dcc_enabled(rtex, level));
232
233 if (rtex->dcc_separate_buffer) {
234 dcc_buffer = &rtex->dcc_separate_buffer->b.b;
235 dcc_offset = 0;
236 } else {
237 dcc_buffer = &rtex->resource.b.b;
238 dcc_offset = rtex->dcc_offset;
239 }
240
241 if (sctx->chip_class >= GFX9) {
242 /* Mipmap level clears aren't implemented. */
243 assert(rtex->resource.b.b.last_level == 0);
244 /* 4x and 8x MSAA needs a sophisticated compute shader for
245 * the clear. See AMDVLK. */
246 assert(rtex->resource.b.b.nr_samples <= 2);
247 clear_size = rtex->surface.dcc_size;
248 } else {
249 unsigned num_layers = util_num_layers(&rtex->resource.b.b, level);
250
251 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
252 assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
253 /* Layered 4x and 8x MSAA DCC fast clears need to clear
254 * dcc_fast_clear_size bytes for each layer. A compute shader
255 * would be more efficient than separate per-layer clear operations.
256 */
257 assert(rtex->resource.b.b.nr_samples <= 2 || num_layers == 1);
258
259 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
260 clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
261 num_layers;
262 }
263
264 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
265 clear_value, SI_COHERENCY_CB_META);
266 }
267
268 /* Set the same micro tile mode as the destination of the last MSAA resolve.
269 * This allows hitting the MSAA resolve fast path, which requires that both
270 * src and dst micro tile modes match.
271 */
272 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
273 struct r600_texture *rtex)
274 {
275 if (rtex->resource.b.is_shared ||
276 rtex->resource.b.b.nr_samples <= 1 ||
277 rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
278 return;
279
280 assert(sscreen->info.chip_class >= GFX9 ||
281 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
282 assert(rtex->resource.b.b.last_level == 0);
283
284 if (sscreen->info.chip_class >= GFX9) {
285 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
286 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
287
288 /* If you do swizzle_mode % 4, you'll get:
289 * 0 = Depth
290 * 1 = Standard,
291 * 2 = Displayable
292 * 3 = Rotated
293 *
294 * Depth-sample order isn't allowed:
295 */
296 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
297
298 switch (rtex->last_msaa_resolve_target_micro_mode) {
299 case RADEON_MICRO_MODE_DISPLAY:
300 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
301 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
302 break;
303 case RADEON_MICRO_MODE_THIN:
304 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
305 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
306 break;
307 case RADEON_MICRO_MODE_ROTATED:
308 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
309 rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
310 break;
311 default: /* depth */
312 assert(!"unexpected micro mode");
313 return;
314 }
315 } else if (sscreen->info.chip_class >= CIK) {
316 /* These magic numbers were copied from addrlib. It doesn't use
317 * any definitions for them either. They are all 2D_TILED_THIN1
318 * modes with different bpp and micro tile mode.
319 */
320 switch (rtex->last_msaa_resolve_target_micro_mode) {
321 case RADEON_MICRO_MODE_DISPLAY:
322 rtex->surface.u.legacy.tiling_index[0] = 10;
323 break;
324 case RADEON_MICRO_MODE_THIN:
325 rtex->surface.u.legacy.tiling_index[0] = 14;
326 break;
327 case RADEON_MICRO_MODE_ROTATED:
328 rtex->surface.u.legacy.tiling_index[0] = 28;
329 break;
330 default: /* depth, thick */
331 assert(!"unexpected micro mode");
332 return;
333 }
334 } else { /* SI */
335 switch (rtex->last_msaa_resolve_target_micro_mode) {
336 case RADEON_MICRO_MODE_DISPLAY:
337 switch (rtex->surface.bpe) {
338 case 1:
339 rtex->surface.u.legacy.tiling_index[0] = 10;
340 break;
341 case 2:
342 rtex->surface.u.legacy.tiling_index[0] = 11;
343 break;
344 default: /* 4, 8 */
345 rtex->surface.u.legacy.tiling_index[0] = 12;
346 break;
347 }
348 break;
349 case RADEON_MICRO_MODE_THIN:
350 switch (rtex->surface.bpe) {
351 case 1:
352 rtex->surface.u.legacy.tiling_index[0] = 14;
353 break;
354 case 2:
355 rtex->surface.u.legacy.tiling_index[0] = 15;
356 break;
357 case 4:
358 rtex->surface.u.legacy.tiling_index[0] = 16;
359 break;
360 default: /* 8, 16 */
361 rtex->surface.u.legacy.tiling_index[0] = 17;
362 break;
363 }
364 break;
365 default: /* depth, thick */
366 assert(!"unexpected micro mode");
367 return;
368 }
369 }
370
371 rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
372
373 p_atomic_inc(&sscreen->dirty_tex_counter);
374 }
375
376 static void si_do_fast_color_clear(struct si_context *sctx,
377 unsigned *buffers,
378 const union pipe_color_union *color)
379 {
380 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
381 int i;
382
383 /* This function is broken in BE, so just disable this path for now */
384 #ifdef PIPE_ARCH_BIG_ENDIAN
385 return;
386 #endif
387
388 if (sctx->render_cond)
389 return;
390
391 for (i = 0; i < fb->nr_cbufs; i++) {
392 struct r600_texture *tex;
393 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
394
395 if (!fb->cbufs[i])
396 continue;
397
398 /* if this colorbuffer is not being cleared */
399 if (!(*buffers & clear_bit))
400 continue;
401
402 unsigned level = fb->cbufs[i]->u.tex.level;
403 if (level > 0)
404 continue;
405
406 tex = (struct r600_texture *)fb->cbufs[i]->texture;
407
408 /* TODO: GFX9: Implement DCC fast clear for level 0 of
409 * mipmapped textures. Mipmapped DCC has to clear a rectangular
410 * area of DCC for level 0 (because the whole miptree is
411 * organized in a 2D plane).
412 */
413 if (sctx->chip_class >= GFX9 &&
414 tex->resource.b.b.last_level > 0)
415 continue;
416
417 /* the clear is allowed if all layers are bound */
418 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
419 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
420 continue;
421 }
422
423 /* only supported on tiled surfaces */
424 if (tex->surface.is_linear) {
425 continue;
426 }
427
428 /* shared textures can't use fast clear without an explicit flush,
429 * because there is no way to communicate the clear color among
430 * all clients
431 */
432 if (tex->resource.b.is_shared &&
433 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
434 continue;
435
436 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
437 if (sctx->chip_class == CIK &&
438 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
439 sctx->screen->info.drm_major == 2 &&
440 sctx->screen->info.drm_minor < 38) {
441 continue;
442 }
443
444 /* Fast clear is the most appropriate place to enable DCC for
445 * displayable surfaces.
446 */
447 if (sctx->chip_class >= VI &&
448 !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
449 vi_separate_dcc_try_enable(sctx, tex);
450
451 /* RB+ isn't supported with a CMASK clear only on Stoney,
452 * so all clears are considered to be hypothetically slow
453 * clears, which is weighed when determining whether to
454 * enable separate DCC.
455 */
456 if (tex->dcc_gather_statistics &&
457 sctx->family == CHIP_STONEY)
458 tex->num_slow_clears++;
459 }
460
461 bool need_decompress_pass = false;
462
463 /* Use a slow clear for small surfaces where the cost of
464 * the eliminate pass can be higher than the benefit of fast
465 * clear. The closed driver does this, but the numbers may differ.
466 *
467 * This helps on both dGPUs and APUs, even small APUs like Mullins.
468 */
469 bool too_small = tex->resource.b.b.nr_samples <= 1 &&
470 tex->resource.b.b.width0 *
471 tex->resource.b.b.height0 <= 512 * 512;
472
473 /* Try to clear DCC first, otherwise try CMASK. */
474 if (vi_dcc_enabled(tex, 0)) {
475 uint32_t reset_value;
476 bool eliminate_needed;
477
478 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
479 continue;
480
481 /* This can only occur with MSAA. */
482 if (sctx->chip_class == VI &&
483 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
484 continue;
485
486 if (!vi_get_fast_clear_parameters(tex->resource.b.b.format,
487 fb->cbufs[i]->format,
488 color, &reset_value,
489 &eliminate_needed))
490 continue;
491
492 if (eliminate_needed && too_small)
493 continue;
494
495 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
496 if (tex->resource.b.b.nr_samples >= 2 && tex->cmask.size) {
497 /* TODO: This doesn't work with MSAA. */
498 if (eliminate_needed)
499 continue;
500
501 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
502 tex->cmask.offset, tex->cmask.size,
503 0xCCCCCCCC, SI_COHERENCY_CB_META);
504 need_decompress_pass = true;
505 }
506
507 vi_dcc_clear_level(sctx, tex, 0, reset_value);
508
509 if (eliminate_needed)
510 need_decompress_pass = true;
511
512 tex->separate_dcc_dirty = true;
513 } else {
514 if (too_small)
515 continue;
516
517 /* 128-bit formats are unusupported */
518 if (tex->surface.bpe > 8) {
519 continue;
520 }
521
522 /* RB+ doesn't work with CMASK fast clear on Stoney. */
523 if (sctx->family == CHIP_STONEY)
524 continue;
525
526 /* ensure CMASK is enabled */
527 si_alloc_separate_cmask(sctx->screen, tex);
528 if (tex->cmask.size == 0) {
529 continue;
530 }
531
532 /* Do the fast clear. */
533 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
534 tex->cmask.offset, tex->cmask.size, 0,
535 SI_COHERENCY_CB_META);
536 need_decompress_pass = true;
537 }
538
539 if (need_decompress_pass &&
540 !(tex->dirty_level_mask & (1 << level))) {
541 tex->dirty_level_mask |= 1 << level;
542 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
543 }
544
545 /* We can change the micro tile mode before a full clear. */
546 si_set_optimal_micro_tile_mode(sctx->screen, tex);
547
548 si_set_clear_color(tex, fb->cbufs[i]->format, color);
549
550 sctx->framebuffer.dirty_cbufs |= 1 << i;
551 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
552 *buffers &= ~clear_bit;
553 }
554 }
555
556 static void si_clear(struct pipe_context *ctx, unsigned buffers,
557 const union pipe_color_union *color,
558 double depth, unsigned stencil)
559 {
560 struct si_context *sctx = (struct si_context *)ctx;
561 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
562 struct pipe_surface *zsbuf = fb->zsbuf;
563 struct r600_texture *zstex =
564 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
565
566 if (buffers & PIPE_CLEAR_COLOR) {
567 si_do_fast_color_clear(sctx, &buffers, color);
568 if (!buffers)
569 return; /* all buffers have been fast cleared */
570
571 /* These buffers cannot use fast clear, make sure to disable expansion. */
572 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
573 struct r600_texture *tex;
574
575 /* If not clearing this buffer, skip. */
576 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
577 continue;
578
579 tex = (struct r600_texture *)fb->cbufs[i]->texture;
580 if (tex->fmask.size == 0)
581 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
582 }
583 }
584
585 if (zstex &&
586 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
587 zsbuf->u.tex.first_layer == 0 &&
588 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
589 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
590 if (buffers & PIPE_CLEAR_DEPTH &&
591 (!zstex->tc_compatible_htile ||
592 depth == 0 || depth == 1)) {
593 /* Need to disable EXPCLEAR temporarily if clearing
594 * to a new value. */
595 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
596 sctx->db_depth_disable_expclear = true;
597 }
598
599 zstex->depth_clear_value = depth;
600 sctx->framebuffer.dirty_zsbuf = true;
601 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); /* updates DB_DEPTH_CLEAR */
602 sctx->db_depth_clear = true;
603 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
604 }
605
606 /* TC-compatible HTILE only supports stencil clears to 0. */
607 if (buffers & PIPE_CLEAR_STENCIL &&
608 (!zstex->tc_compatible_htile || stencil == 0)) {
609 stencil &= 0xff;
610
611 /* Need to disable EXPCLEAR temporarily if clearing
612 * to a new value. */
613 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
614 sctx->db_stencil_disable_expclear = true;
615 }
616
617 zstex->stencil_clear_value = stencil;
618 sctx->framebuffer.dirty_zsbuf = true;
619 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); /* updates DB_STENCIL_CLEAR */
620 sctx->db_stencil_clear = true;
621 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
622 }
623
624 /* TODO: Find out what's wrong here. Fast depth clear leads to
625 * corruption in ARK: Survival Evolved, but that may just be
626 * a coincidence and the root cause is elsewhere.
627 *
628 * The corruption can be fixed by putting the DB flush before
629 * or after the depth clear. (surprisingly)
630 *
631 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
632 *
633 * This hack decreases back-to-back ClearDepth performance.
634 */
635 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
636 sctx->screen->clear_db_cache_before_clear)
637 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
638 }
639
640 si_blitter_begin(sctx, SI_CLEAR);
641 util_blitter_clear(sctx->blitter, fb->width, fb->height,
642 util_framebuffer_get_num_layers(fb),
643 buffers, color, depth, stencil);
644 si_blitter_end(sctx);
645
646 if (sctx->db_depth_clear) {
647 sctx->db_depth_clear = false;
648 sctx->db_depth_disable_expclear = false;
649 zstex->depth_cleared = true;
650 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
651 }
652
653 if (sctx->db_stencil_clear) {
654 sctx->db_stencil_clear = false;
655 sctx->db_stencil_disable_expclear = false;
656 zstex->stencil_cleared = true;
657 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
658 }
659 }
660
661 static void si_clear_render_target(struct pipe_context *ctx,
662 struct pipe_surface *dst,
663 const union pipe_color_union *color,
664 unsigned dstx, unsigned dsty,
665 unsigned width, unsigned height,
666 bool render_condition_enabled)
667 {
668 struct si_context *sctx = (struct si_context *)ctx;
669
670 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
671 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
672 util_blitter_clear_render_target(sctx->blitter, dst, color,
673 dstx, dsty, width, height);
674 si_blitter_end(sctx);
675 }
676
677 static void si_clear_depth_stencil(struct pipe_context *ctx,
678 struct pipe_surface *dst,
679 unsigned clear_flags,
680 double depth,
681 unsigned stencil,
682 unsigned dstx, unsigned dsty,
683 unsigned width, unsigned height,
684 bool render_condition_enabled)
685 {
686 struct si_context *sctx = (struct si_context *)ctx;
687
688 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
689 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
690 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
691 dstx, dsty, width, height);
692 si_blitter_end(sctx);
693 }
694
695 static void si_clear_texture(struct pipe_context *pipe,
696 struct pipe_resource *tex,
697 unsigned level,
698 const struct pipe_box *box,
699 const void *data)
700 {
701 struct pipe_screen *screen = pipe->screen;
702 struct r600_texture *rtex = (struct r600_texture*)tex;
703 struct pipe_surface tmpl = {{0}};
704 struct pipe_surface *sf;
705 const struct util_format_description *desc =
706 util_format_description(tex->format);
707
708 tmpl.format = tex->format;
709 tmpl.u.tex.first_layer = box->z;
710 tmpl.u.tex.last_layer = box->z + box->depth - 1;
711 tmpl.u.tex.level = level;
712 sf = pipe->create_surface(pipe, tex, &tmpl);
713 if (!sf)
714 return;
715
716 if (rtex->is_depth) {
717 unsigned clear;
718 float depth;
719 uint8_t stencil = 0;
720
721 /* Depth is always present. */
722 clear = PIPE_CLEAR_DEPTH;
723 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
724
725 if (rtex->surface.has_stencil) {
726 clear |= PIPE_CLEAR_STENCIL;
727 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
728 }
729
730 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
731 box->x, box->y,
732 box->width, box->height, false);
733 } else {
734 union pipe_color_union color;
735
736 /* pipe_color_union requires the full vec4 representation. */
737 if (util_format_is_pure_uint(tex->format))
738 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
739 else if (util_format_is_pure_sint(tex->format))
740 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
741 else
742 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
743
744 if (screen->is_format_supported(screen, tex->format,
745 tex->target, 0,
746 PIPE_BIND_RENDER_TARGET)) {
747 si_clear_render_target(pipe, sf, &color,
748 box->x, box->y,
749 box->width, box->height, false);
750 } else {
751 /* Software fallback - just for R9G9B9E5_FLOAT */
752 util_clear_render_target(pipe, sf, &color,
753 box->x, box->y,
754 box->width, box->height);
755 }
756 }
757 pipe_surface_reference(&sf, NULL);
758 }
759
760 void si_init_clear_functions(struct si_context *sctx)
761 {
762 sctx->b.clear = si_clear;
763 sctx->b.clear_render_target = si_clear_render_target;
764 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
765 sctx->b.clear_texture = si_clear_texture;
766 }