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[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct r600_texture *rtex)
39 {
40 if (rtex->cmask_buffer)
41 return;
42
43 assert(rtex->cmask.size == 0);
44
45 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
46 if (!rtex->cmask.size)
47 return;
48
49 rtex->cmask_buffer = (struct r600_resource *)
50 si_aligned_buffer_create(&sscreen->b,
51 SI_RESOURCE_FLAG_UNMAPPABLE,
52 PIPE_USAGE_DEFAULT,
53 rtex->cmask.size,
54 rtex->cmask.alignment);
55 if (rtex->cmask_buffer == NULL) {
56 rtex->cmask.size = 0;
57 return;
58 }
59
60 /* update colorbuffer state bits */
61 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
62
63 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
64
65 p_atomic_inc(&sscreen->compressed_colortex_counter);
66 }
67
68 static void si_set_clear_color(struct r600_texture *rtex,
69 enum pipe_format surface_format,
70 const union pipe_color_union *color)
71 {
72 union util_color uc;
73
74 memset(&uc, 0, sizeof(uc));
75
76 if (rtex->surface.bpe == 16) {
77 /* DCC fast clear only:
78 * CLEAR_WORD0 = R = G = B
79 * CLEAR_WORD1 = A
80 */
81 assert(color->ui[0] == color->ui[1] &&
82 color->ui[0] == color->ui[2]);
83 uc.ui[0] = color->ui[0];
84 uc.ui[1] = color->ui[3];
85 } else if (util_format_is_pure_uint(surface_format)) {
86 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
87 } else if (util_format_is_pure_sint(surface_format)) {
88 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
89 } else {
90 util_pack_color(color->f, surface_format, &uc);
91 }
92
93 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
94 }
95
96 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format,
97 const union pipe_color_union *color,
98 uint32_t* reset_value,
99 bool* clear_words_needed)
100 {
101 bool values[4] = {};
102 int i;
103 bool main_value = false;
104 bool extra_value = false;
105 int extra_channel;
106
107 /* This is needed to get the correct DCC clear value for luminance formats.
108 * 1) Get the linear format (because the next step can't handle L8_SRGB).
109 * 2) Convert luminance to red. (the real hw format for luminance)
110 */
111 surface_format = util_format_linear(surface_format);
112 surface_format = util_format_luminance_to_red(surface_format);
113
114 const struct util_format_description *desc = util_format_description(surface_format);
115
116 if (desc->block.bits == 128 &&
117 (color->ui[0] != color->ui[1] ||
118 color->ui[0] != color->ui[2]))
119 return false;
120
121 *clear_words_needed = true;
122 *reset_value = 0x20202020U;
123
124 /* If we want to clear without needing a fast clear eliminate step, we
125 * can set each channel to 0 or 1 (or 0/max for integer formats). We
126 * have two sets of flags, one for the last or first channel(extra) and
127 * one for the other channels(main).
128 */
129
130 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
131 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
132 surface_format == PIPE_FORMAT_B5G6R5_SRGB ||
133 util_format_is_alpha(surface_format)) {
134 extra_channel = -1;
135 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
136 if (si_translate_colorswap(surface_format, false) <= 1)
137 extra_channel = desc->nr_channels - 1;
138 else
139 extra_channel = 0;
140 } else
141 return true;
142
143 for (i = 0; i < 4; ++i) {
144 int index = desc->swizzle[i] - PIPE_SWIZZLE_X;
145
146 if (desc->swizzle[i] < PIPE_SWIZZLE_X ||
147 desc->swizzle[i] > PIPE_SWIZZLE_W)
148 continue;
149
150 if (desc->channel[i].pure_integer &&
151 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
152 /* Use the maximum value for clamping the clear color. */
153 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
154
155 values[i] = color->i[i] != 0;
156 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
157 return true;
158 } else if (desc->channel[i].pure_integer &&
159 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
160 /* Use the maximum value for clamping the clear color. */
161 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
162
163 values[i] = color->ui[i] != 0U;
164 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
165 return true;
166 } else {
167 values[i] = color->f[i] != 0.0F;
168 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
169 return true;
170 }
171
172 if (index == extra_channel)
173 extra_value = values[i];
174 else
175 main_value = values[i];
176 }
177
178 for (int i = 0; i < 4; ++i)
179 if (values[i] != main_value &&
180 desc->swizzle[i] - PIPE_SWIZZLE_X != extra_channel &&
181 desc->swizzle[i] >= PIPE_SWIZZLE_X &&
182 desc->swizzle[i] <= PIPE_SWIZZLE_W)
183 return true;
184
185 *clear_words_needed = false;
186 if (main_value)
187 *reset_value |= 0x80808080U;
188
189 if (extra_value)
190 *reset_value |= 0x40404040U;
191 return true;
192 }
193
194 void vi_dcc_clear_level(struct si_context *sctx,
195 struct r600_texture *rtex,
196 unsigned level, unsigned clear_value)
197 {
198 struct pipe_resource *dcc_buffer;
199 uint64_t dcc_offset, clear_size;
200
201 assert(vi_dcc_enabled(rtex, level));
202
203 if (rtex->dcc_separate_buffer) {
204 dcc_buffer = &rtex->dcc_separate_buffer->b.b;
205 dcc_offset = 0;
206 } else {
207 dcc_buffer = &rtex->resource.b.b;
208 dcc_offset = rtex->dcc_offset;
209 }
210
211 if (sctx->chip_class >= GFX9) {
212 /* Mipmap level clears aren't implemented. */
213 assert(rtex->resource.b.b.last_level == 0);
214 /* MSAA needs a different clear size. */
215 assert(rtex->resource.b.b.nr_samples <= 1);
216 clear_size = rtex->surface.dcc_size;
217 } else {
218 unsigned num_layers = util_num_layers(&rtex->resource.b.b, level);
219
220 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
221 assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
222 /* Layered MSAA DCC fast clears need to clear dcc_fast_clear_size
223 * bytes for each layer. This is not currently implemented, and
224 * therefore MSAA DCC isn't even enabled with multiple layers.
225 */
226 assert(rtex->resource.b.b.nr_samples <= 1 || num_layers == 1);
227
228 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
229 clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
230 num_layers;
231 }
232
233 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
234 clear_value, SI_COHERENCY_CB_META);
235 }
236
237 /* Set the same micro tile mode as the destination of the last MSAA resolve.
238 * This allows hitting the MSAA resolve fast path, which requires that both
239 * src and dst micro tile modes match.
240 */
241 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
242 struct r600_texture *rtex)
243 {
244 if (rtex->resource.b.is_shared ||
245 rtex->resource.b.b.nr_samples <= 1 ||
246 rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
247 return;
248
249 assert(sscreen->info.chip_class >= GFX9 ||
250 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
251 assert(rtex->resource.b.b.last_level == 0);
252
253 if (sscreen->info.chip_class >= GFX9) {
254 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
255 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
256
257 /* If you do swizzle_mode % 4, you'll get:
258 * 0 = Depth
259 * 1 = Standard,
260 * 2 = Displayable
261 * 3 = Rotated
262 *
263 * Depth-sample order isn't allowed:
264 */
265 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
266
267 switch (rtex->last_msaa_resolve_target_micro_mode) {
268 case RADEON_MICRO_MODE_DISPLAY:
269 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
270 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
271 break;
272 case RADEON_MICRO_MODE_THIN:
273 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
274 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
275 break;
276 case RADEON_MICRO_MODE_ROTATED:
277 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
278 rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
279 break;
280 default: /* depth */
281 assert(!"unexpected micro mode");
282 return;
283 }
284 } else if (sscreen->info.chip_class >= CIK) {
285 /* These magic numbers were copied from addrlib. It doesn't use
286 * any definitions for them either. They are all 2D_TILED_THIN1
287 * modes with different bpp and micro tile mode.
288 */
289 switch (rtex->last_msaa_resolve_target_micro_mode) {
290 case RADEON_MICRO_MODE_DISPLAY:
291 rtex->surface.u.legacy.tiling_index[0] = 10;
292 break;
293 case RADEON_MICRO_MODE_THIN:
294 rtex->surface.u.legacy.tiling_index[0] = 14;
295 break;
296 case RADEON_MICRO_MODE_ROTATED:
297 rtex->surface.u.legacy.tiling_index[0] = 28;
298 break;
299 default: /* depth, thick */
300 assert(!"unexpected micro mode");
301 return;
302 }
303 } else { /* SI */
304 switch (rtex->last_msaa_resolve_target_micro_mode) {
305 case RADEON_MICRO_MODE_DISPLAY:
306 switch (rtex->surface.bpe) {
307 case 1:
308 rtex->surface.u.legacy.tiling_index[0] = 10;
309 break;
310 case 2:
311 rtex->surface.u.legacy.tiling_index[0] = 11;
312 break;
313 default: /* 4, 8 */
314 rtex->surface.u.legacy.tiling_index[0] = 12;
315 break;
316 }
317 break;
318 case RADEON_MICRO_MODE_THIN:
319 switch (rtex->surface.bpe) {
320 case 1:
321 rtex->surface.u.legacy.tiling_index[0] = 14;
322 break;
323 case 2:
324 rtex->surface.u.legacy.tiling_index[0] = 15;
325 break;
326 case 4:
327 rtex->surface.u.legacy.tiling_index[0] = 16;
328 break;
329 default: /* 8, 16 */
330 rtex->surface.u.legacy.tiling_index[0] = 17;
331 break;
332 }
333 break;
334 default: /* depth, thick */
335 assert(!"unexpected micro mode");
336 return;
337 }
338 }
339
340 rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
341
342 p_atomic_inc(&sscreen->dirty_tex_counter);
343 }
344
345 static void si_do_fast_color_clear(struct si_context *sctx,
346 unsigned *buffers,
347 const union pipe_color_union *color)
348 {
349 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
350 int i;
351
352 /* This function is broken in BE, so just disable this path for now */
353 #ifdef PIPE_ARCH_BIG_ENDIAN
354 return;
355 #endif
356
357 if (sctx->render_cond)
358 return;
359
360 for (i = 0; i < fb->nr_cbufs; i++) {
361 struct r600_texture *tex;
362 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
363
364 if (!fb->cbufs[i])
365 continue;
366
367 /* if this colorbuffer is not being cleared */
368 if (!(*buffers & clear_bit))
369 continue;
370
371 unsigned level = fb->cbufs[i]->u.tex.level;
372 tex = (struct r600_texture *)fb->cbufs[i]->texture;
373
374 /* the clear is allowed if all layers are bound */
375 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
376 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
377 continue;
378 }
379
380 /* cannot clear mipmapped textures */
381 if (fb->cbufs[i]->texture->last_level != 0) {
382 continue;
383 }
384
385 /* only supported on tiled surfaces */
386 if (tex->surface.is_linear) {
387 continue;
388 }
389
390 /* shared textures can't use fast clear without an explicit flush,
391 * because there is no way to communicate the clear color among
392 * all clients
393 */
394 if (tex->resource.b.is_shared &&
395 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
396 continue;
397
398 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
399 if (sctx->chip_class == CIK &&
400 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
401 sctx->screen->info.drm_major == 2 &&
402 sctx->screen->info.drm_minor < 38) {
403 continue;
404 }
405
406 /* Fast clear is the most appropriate place to enable DCC for
407 * displayable surfaces.
408 */
409 if (sctx->chip_class >= VI &&
410 !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
411 vi_separate_dcc_try_enable(sctx, tex);
412
413 /* RB+ isn't supported with a CMASK clear only on Stoney,
414 * so all clears are considered to be hypothetically slow
415 * clears, which is weighed when determining whether to
416 * enable separate DCC.
417 */
418 if (tex->dcc_gather_statistics &&
419 sctx->family == CHIP_STONEY)
420 tex->num_slow_clears++;
421 }
422
423 bool need_decompress_pass = false;
424
425 /* Use a slow clear for small surfaces where the cost of
426 * the eliminate pass can be higher than the benefit of fast
427 * clear. The closed driver does this, but the numbers may differ.
428 *
429 * This helps on both dGPUs and APUs, even small APUs like Mullins.
430 */
431 bool too_small = tex->resource.b.b.nr_samples <= 1 &&
432 tex->resource.b.b.width0 *
433 tex->resource.b.b.height0 <= 512 * 512;
434
435 /* Try to clear DCC first, otherwise try CMASK. */
436 if (vi_dcc_enabled(tex, 0)) {
437 uint32_t reset_value;
438 bool clear_words_needed;
439
440 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
441 continue;
442
443 /* This can only occur with MSAA. */
444 if (sctx->chip_class == VI &&
445 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
446 continue;
447
448 if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
449 color, &reset_value,
450 &clear_words_needed))
451 continue;
452
453 if (clear_words_needed && too_small)
454 continue;
455
456 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
457 if (tex->resource.b.b.nr_samples >= 2 && tex->cmask.size) {
458 /* TODO: This doesn't work with MSAA. */
459 if (clear_words_needed)
460 continue;
461
462 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
463 tex->cmask.offset, tex->cmask.size,
464 0xCCCCCCCC, SI_COHERENCY_CB_META);
465 need_decompress_pass = true;
466 }
467
468 vi_dcc_clear_level(sctx, tex, 0, reset_value);
469
470 if (clear_words_needed)
471 need_decompress_pass = true;
472
473 tex->separate_dcc_dirty = true;
474 } else {
475 if (too_small)
476 continue;
477
478 /* 128-bit formats are unusupported */
479 if (tex->surface.bpe > 8) {
480 continue;
481 }
482
483 /* RB+ doesn't work with CMASK fast clear on Stoney. */
484 if (sctx->family == CHIP_STONEY)
485 continue;
486
487 /* ensure CMASK is enabled */
488 si_alloc_separate_cmask(sctx->screen, tex);
489 if (tex->cmask.size == 0) {
490 continue;
491 }
492
493 /* Do the fast clear. */
494 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
495 tex->cmask.offset, tex->cmask.size, 0,
496 SI_COHERENCY_CB_META);
497 need_decompress_pass = true;
498 }
499
500 if (need_decompress_pass &&
501 !(tex->dirty_level_mask & (1 << level))) {
502 tex->dirty_level_mask |= 1 << level;
503 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
504 }
505
506 /* We can change the micro tile mode before a full clear. */
507 si_set_optimal_micro_tile_mode(sctx->screen, tex);
508
509 si_set_clear_color(tex, fb->cbufs[i]->format, color);
510
511 sctx->framebuffer.dirty_cbufs |= 1 << i;
512 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
513 *buffers &= ~clear_bit;
514 }
515 }
516
517 static void si_clear(struct pipe_context *ctx, unsigned buffers,
518 const union pipe_color_union *color,
519 double depth, unsigned stencil)
520 {
521 struct si_context *sctx = (struct si_context *)ctx;
522 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
523 struct pipe_surface *zsbuf = fb->zsbuf;
524 struct r600_texture *zstex =
525 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
526
527 if (buffers & PIPE_CLEAR_COLOR) {
528 si_do_fast_color_clear(sctx, &buffers, color);
529 if (!buffers)
530 return; /* all buffers have been fast cleared */
531
532 /* These buffers cannot use fast clear, make sure to disable expansion. */
533 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
534 struct r600_texture *tex;
535
536 /* If not clearing this buffer, skip. */
537 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
538 continue;
539
540 tex = (struct r600_texture *)fb->cbufs[i]->texture;
541 if (tex->fmask.size == 0)
542 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
543 }
544 }
545
546 if (zstex &&
547 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
548 zsbuf->u.tex.first_layer == 0 &&
549 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
550 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
551 if (buffers & PIPE_CLEAR_DEPTH &&
552 (!zstex->tc_compatible_htile ||
553 depth == 0 || depth == 1)) {
554 /* Need to disable EXPCLEAR temporarily if clearing
555 * to a new value. */
556 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
557 sctx->db_depth_disable_expclear = true;
558 }
559
560 zstex->depth_clear_value = depth;
561 sctx->framebuffer.dirty_zsbuf = true;
562 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
563 sctx->db_depth_clear = true;
564 si_mark_atom_dirty(sctx, &sctx->db_render_state);
565 }
566
567 /* TC-compatible HTILE only supports stencil clears to 0. */
568 if (buffers & PIPE_CLEAR_STENCIL &&
569 (!zstex->tc_compatible_htile || stencil == 0)) {
570 stencil &= 0xff;
571
572 /* Need to disable EXPCLEAR temporarily if clearing
573 * to a new value. */
574 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
575 sctx->db_stencil_disable_expclear = true;
576 }
577
578 zstex->stencil_clear_value = stencil;
579 sctx->framebuffer.dirty_zsbuf = true;
580 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
581 sctx->db_stencil_clear = true;
582 si_mark_atom_dirty(sctx, &sctx->db_render_state);
583 }
584
585 /* TODO: Find out what's wrong here. Fast depth clear leads to
586 * corruption in ARK: Survival Evolved, but that may just be
587 * a coincidence and the root cause is elsewhere.
588 *
589 * The corruption can be fixed by putting the DB flush before
590 * or after the depth clear. (surprisingly)
591 *
592 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
593 *
594 * This hack decreases back-to-back ClearDepth performance.
595 */
596 if (sctx->screen->clear_db_cache_before_clear) {
597 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
598 }
599 }
600
601 si_blitter_begin(sctx, SI_CLEAR);
602 util_blitter_clear(sctx->blitter, fb->width, fb->height,
603 util_framebuffer_get_num_layers(fb),
604 buffers, color, depth, stencil);
605 si_blitter_end(sctx);
606
607 if (sctx->db_depth_clear) {
608 sctx->db_depth_clear = false;
609 sctx->db_depth_disable_expclear = false;
610 zstex->depth_cleared = true;
611 si_mark_atom_dirty(sctx, &sctx->db_render_state);
612 }
613
614 if (sctx->db_stencil_clear) {
615 sctx->db_stencil_clear = false;
616 sctx->db_stencil_disable_expclear = false;
617 zstex->stencil_cleared = true;
618 si_mark_atom_dirty(sctx, &sctx->db_render_state);
619 }
620 }
621
622 static void si_clear_render_target(struct pipe_context *ctx,
623 struct pipe_surface *dst,
624 const union pipe_color_union *color,
625 unsigned dstx, unsigned dsty,
626 unsigned width, unsigned height,
627 bool render_condition_enabled)
628 {
629 struct si_context *sctx = (struct si_context *)ctx;
630
631 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
632 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
633 util_blitter_clear_render_target(sctx->blitter, dst, color,
634 dstx, dsty, width, height);
635 si_blitter_end(sctx);
636 }
637
638 static void si_clear_depth_stencil(struct pipe_context *ctx,
639 struct pipe_surface *dst,
640 unsigned clear_flags,
641 double depth,
642 unsigned stencil,
643 unsigned dstx, unsigned dsty,
644 unsigned width, unsigned height,
645 bool render_condition_enabled)
646 {
647 struct si_context *sctx = (struct si_context *)ctx;
648
649 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
650 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
651 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
652 dstx, dsty, width, height);
653 si_blitter_end(sctx);
654 }
655
656 static void si_clear_texture(struct pipe_context *pipe,
657 struct pipe_resource *tex,
658 unsigned level,
659 const struct pipe_box *box,
660 const void *data)
661 {
662 struct pipe_screen *screen = pipe->screen;
663 struct r600_texture *rtex = (struct r600_texture*)tex;
664 struct pipe_surface tmpl = {{0}};
665 struct pipe_surface *sf;
666 const struct util_format_description *desc =
667 util_format_description(tex->format);
668
669 tmpl.format = tex->format;
670 tmpl.u.tex.first_layer = box->z;
671 tmpl.u.tex.last_layer = box->z + box->depth - 1;
672 tmpl.u.tex.level = level;
673 sf = pipe->create_surface(pipe, tex, &tmpl);
674 if (!sf)
675 return;
676
677 if (rtex->is_depth) {
678 unsigned clear;
679 float depth;
680 uint8_t stencil = 0;
681
682 /* Depth is always present. */
683 clear = PIPE_CLEAR_DEPTH;
684 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
685
686 if (rtex->surface.has_stencil) {
687 clear |= PIPE_CLEAR_STENCIL;
688 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
689 }
690
691 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
692 box->x, box->y,
693 box->width, box->height, false);
694 } else {
695 union pipe_color_union color;
696
697 /* pipe_color_union requires the full vec4 representation. */
698 if (util_format_is_pure_uint(tex->format))
699 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
700 else if (util_format_is_pure_sint(tex->format))
701 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
702 else
703 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
704
705 if (screen->is_format_supported(screen, tex->format,
706 tex->target, 0,
707 PIPE_BIND_RENDER_TARGET)) {
708 si_clear_render_target(pipe, sf, &color,
709 box->x, box->y,
710 box->width, box->height, false);
711 } else {
712 /* Software fallback - just for R9G9B9E5_FLOAT */
713 util_clear_render_target(pipe, sf, &color,
714 box->x, box->y,
715 box->width, box->height);
716 }
717 }
718 pipe_surface_reference(&sf, NULL);
719 }
720
721 void si_init_clear_functions(struct si_context *sctx)
722 {
723 sctx->b.clear = si_clear;
724 sctx->b.clear_render_target = si_clear_render_target;
725 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
726 sctx->b.clear_texture = si_clear_texture;
727 }