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[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct si_texture *tex)
39 {
40 /* CMASK for MSAA is allocated in advance or always disabled
41 * by "nofmask" option.
42 */
43 if (tex->cmask_buffer || !tex->surface.cmask_size ||
44 tex->buffer.b.b.nr_samples >= 2)
45 return;
46
47 tex->cmask_buffer =
48 si_aligned_buffer_create(&sscreen->b,
49 SI_RESOURCE_FLAG_UNMAPPABLE,
50 PIPE_USAGE_DEFAULT,
51 tex->surface.cmask_size,
52 tex->surface.cmask_alignment);
53 if (tex->cmask_buffer == NULL)
54 return;
55
56 tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
57 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
58
59 p_atomic_inc(&sscreen->compressed_colortex_counter);
60 }
61
62 static bool si_set_clear_color(struct si_texture *tex,
63 enum pipe_format surface_format,
64 const union pipe_color_union *color)
65 {
66 union util_color uc;
67
68 memset(&uc, 0, sizeof(uc));
69
70 if (tex->surface.bpe == 16) {
71 /* DCC fast clear only:
72 * CLEAR_WORD0 = R = G = B
73 * CLEAR_WORD1 = A
74 */
75 assert(color->ui[0] == color->ui[1] &&
76 color->ui[0] == color->ui[2]);
77 uc.ui[0] = color->ui[0];
78 uc.ui[1] = color->ui[3];
79 } else if (util_format_is_pure_uint(surface_format)) {
80 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
81 } else if (util_format_is_pure_sint(surface_format)) {
82 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
83 } else {
84 util_pack_color(color->f, surface_format, &uc);
85 }
86
87 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
88 return false;
89
90 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
91 return true;
92 }
93
94 /** Linearize and convert luminace/intensity to red. */
95 enum pipe_format si_simplify_cb_format(enum pipe_format format)
96 {
97 format = util_format_linear(format);
98 format = util_format_luminance_to_red(format);
99 return util_format_intensity_to_red(format);
100 }
101
102 bool vi_alpha_is_on_msb(enum pipe_format format)
103 {
104 format = si_simplify_cb_format(format);
105
106 /* Formats with 3 channels can't have alpha. */
107 if (util_format_description(format)->nr_channels == 3)
108 return true; /* same as xxxA; is any value OK here? */
109
110 return si_translate_colorswap(format, false) <= 1;
111 }
112
113 static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
114 enum pipe_format surface_format,
115 const union pipe_color_union *color,
116 uint32_t* clear_value,
117 bool *eliminate_needed)
118 {
119 /* If we want to clear without needing a fast clear eliminate step, we
120 * can set color and alpha independently to 0 or 1 (or 0/max for integer
121 * formats).
122 */
123 bool values[4] = {}; /* whether to clear to 0 or 1 */
124 bool color_value = false; /* clear color to 0 or 1 */
125 bool alpha_value = false; /* clear alpha to 0 or 1 */
126 int alpha_channel; /* index of the alpha component */
127 bool has_color = false;
128 bool has_alpha = false;
129
130 const struct util_format_description *desc =
131 util_format_description(si_simplify_cb_format(surface_format));
132
133 /* 128-bit fast clear with different R,G,B values is unsupported. */
134 if (desc->block.bits == 128 &&
135 (color->ui[0] != color->ui[1] ||
136 color->ui[0] != color->ui[2]))
137 return false;
138
139 *eliminate_needed = true;
140 *clear_value = DCC_CLEAR_COLOR_REG;
141
142 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
143 return true; /* need ELIMINATE_FAST_CLEAR */
144
145 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
146 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
147
148 /* Formats with 3 channels can't have alpha. */
149 if (desc->nr_channels == 3)
150 alpha_channel = -1;
151 else if (surf_alpha_is_on_msb)
152 alpha_channel = desc->nr_channels - 1;
153 else
154 alpha_channel = 0;
155
156 for (int i = 0; i < 4; ++i) {
157 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
158 continue;
159
160 if (desc->channel[i].pure_integer &&
161 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
162 /* Use the maximum value for clamping the clear color. */
163 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
164
165 values[i] = color->i[i] != 0;
166 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
167 return true; /* need ELIMINATE_FAST_CLEAR */
168 } else if (desc->channel[i].pure_integer &&
169 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
170 /* Use the maximum value for clamping the clear color. */
171 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
172
173 values[i] = color->ui[i] != 0U;
174 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
175 return true; /* need ELIMINATE_FAST_CLEAR */
176 } else {
177 values[i] = color->f[i] != 0.0F;
178 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
179 return true; /* need ELIMINATE_FAST_CLEAR */
180 }
181
182 if (desc->swizzle[i] == alpha_channel) {
183 alpha_value = values[i];
184 has_alpha = true;
185 } else {
186 color_value = values[i];
187 has_color = true;
188 }
189 }
190
191 /* If alpha isn't present, make it the same as color, and vice versa. */
192 if (!has_alpha)
193 alpha_value = color_value;
194 else if (!has_color)
195 color_value = alpha_value;
196
197 if (color_value != alpha_value &&
198 base_alpha_is_on_msb != surf_alpha_is_on_msb)
199 return true; /* require ELIMINATE_FAST_CLEAR */
200
201 /* Check if all color values are equal if they are present. */
202 for (int i = 0; i < 4; ++i) {
203 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
204 desc->swizzle[i] != alpha_channel &&
205 values[i] != color_value)
206 return true; /* require ELIMINATE_FAST_CLEAR */
207 }
208
209 /* This doesn't need ELIMINATE_FAST_CLEAR.
210 * On chips predating Raven2, the DCC clear codes and the CB clear
211 * color registers must match.
212 */
213 *eliminate_needed = false;
214
215 if (color_value) {
216 if (alpha_value)
217 *clear_value = DCC_CLEAR_COLOR_1111;
218 else
219 *clear_value = DCC_CLEAR_COLOR_1110;
220 } else {
221 if (alpha_value)
222 *clear_value = DCC_CLEAR_COLOR_0001;
223 else
224 *clear_value = DCC_CLEAR_COLOR_0000;
225 }
226 return true;
227 }
228
229 void vi_dcc_clear_level(struct si_context *sctx,
230 struct si_texture *tex,
231 unsigned level, unsigned clear_value)
232 {
233 struct pipe_resource *dcc_buffer;
234 uint64_t dcc_offset, clear_size;
235
236 assert(vi_dcc_enabled(tex, level));
237
238 if (tex->dcc_separate_buffer) {
239 dcc_buffer = &tex->dcc_separate_buffer->b.b;
240 dcc_offset = 0;
241 } else {
242 dcc_buffer = &tex->buffer.b.b;
243 dcc_offset = tex->dcc_offset;
244 }
245
246 if (sctx->chip_class >= GFX9) {
247 /* Mipmap level clears aren't implemented. */
248 assert(tex->buffer.b.b.last_level == 0);
249 /* 4x and 8x MSAA needs a sophisticated compute shader for
250 * the clear. See AMDVLK. */
251 assert(tex->buffer.b.b.nr_storage_samples <= 2);
252 clear_size = tex->surface.dcc_size;
253 } else {
254 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
255
256 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
257 assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
258 /* Layered 4x and 8x MSAA DCC fast clears need to clear
259 * dcc_fast_clear_size bytes for each layer. A compute shader
260 * would be more efficient than separate per-layer clear operations.
261 */
262 assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
263
264 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
265 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
266 num_layers;
267 }
268
269 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
270 &clear_value, 4, SI_COHERENCY_CB_META, false);
271 }
272
273 /* Set the same micro tile mode as the destination of the last MSAA resolve.
274 * This allows hitting the MSAA resolve fast path, which requires that both
275 * src and dst micro tile modes match.
276 */
277 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
278 struct si_texture *tex)
279 {
280 if (sscreen->info.chip_class >= GFX10 ||
281 tex->buffer.b.is_shared ||
282 tex->buffer.b.b.nr_samples <= 1 ||
283 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
284 return;
285
286 assert(sscreen->info.chip_class >= GFX9 ||
287 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
288 assert(tex->buffer.b.b.last_level == 0);
289
290 if (sscreen->info.chip_class >= GFX9) {
291 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
292 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
293
294 /* If you do swizzle_mode % 4, you'll get:
295 * 0 = Depth
296 * 1 = Standard,
297 * 2 = Displayable
298 * 3 = Rotated
299 *
300 * Depth-sample order isn't allowed:
301 */
302 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
303
304 switch (tex->last_msaa_resolve_target_micro_mode) {
305 case RADEON_MICRO_MODE_DISPLAY:
306 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
307 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
308 break;
309 case RADEON_MICRO_MODE_THIN:
310 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
311 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
312 break;
313 case RADEON_MICRO_MODE_ROTATED:
314 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
315 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
316 break;
317 default: /* depth */
318 assert(!"unexpected micro mode");
319 return;
320 }
321 } else if (sscreen->info.chip_class >= GFX7) {
322 /* These magic numbers were copied from addrlib. It doesn't use
323 * any definitions for them either. They are all 2D_TILED_THIN1
324 * modes with different bpp and micro tile mode.
325 */
326 switch (tex->last_msaa_resolve_target_micro_mode) {
327 case RADEON_MICRO_MODE_DISPLAY:
328 tex->surface.u.legacy.tiling_index[0] = 10;
329 break;
330 case RADEON_MICRO_MODE_THIN:
331 tex->surface.u.legacy.tiling_index[0] = 14;
332 break;
333 case RADEON_MICRO_MODE_ROTATED:
334 tex->surface.u.legacy.tiling_index[0] = 28;
335 break;
336 default: /* depth, thick */
337 assert(!"unexpected micro mode");
338 return;
339 }
340 } else { /* GFX6 */
341 switch (tex->last_msaa_resolve_target_micro_mode) {
342 case RADEON_MICRO_MODE_DISPLAY:
343 switch (tex->surface.bpe) {
344 case 1:
345 tex->surface.u.legacy.tiling_index[0] = 10;
346 break;
347 case 2:
348 tex->surface.u.legacy.tiling_index[0] = 11;
349 break;
350 default: /* 4, 8 */
351 tex->surface.u.legacy.tiling_index[0] = 12;
352 break;
353 }
354 break;
355 case RADEON_MICRO_MODE_THIN:
356 switch (tex->surface.bpe) {
357 case 1:
358 tex->surface.u.legacy.tiling_index[0] = 14;
359 break;
360 case 2:
361 tex->surface.u.legacy.tiling_index[0] = 15;
362 break;
363 case 4:
364 tex->surface.u.legacy.tiling_index[0] = 16;
365 break;
366 default: /* 8, 16 */
367 tex->surface.u.legacy.tiling_index[0] = 17;
368 break;
369 }
370 break;
371 default: /* depth, thick */
372 assert(!"unexpected micro mode");
373 return;
374 }
375 }
376
377 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
378
379 p_atomic_inc(&sscreen->dirty_tex_counter);
380 }
381
382 static void si_do_fast_color_clear(struct si_context *sctx,
383 unsigned *buffers,
384 const union pipe_color_union *color)
385 {
386 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
387 int i;
388
389 /* This function is broken in BE, so just disable this path for now */
390 #ifdef PIPE_ARCH_BIG_ENDIAN
391 return;
392 #endif
393
394 if (sctx->render_cond)
395 return;
396
397 for (i = 0; i < fb->nr_cbufs; i++) {
398 struct si_texture *tex;
399 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
400
401 if (!fb->cbufs[i])
402 continue;
403
404 /* if this colorbuffer is not being cleared */
405 if (!(*buffers & clear_bit))
406 continue;
407
408 unsigned level = fb->cbufs[i]->u.tex.level;
409 if (level > 0)
410 continue;
411
412 tex = (struct si_texture *)fb->cbufs[i]->texture;
413
414 /* TODO: GFX9: Implement DCC fast clear for level 0 of
415 * mipmapped textures. Mipmapped DCC has to clear a rectangular
416 * area of DCC for level 0 (because the whole miptree is
417 * organized in a 2D plane).
418 */
419 if (sctx->chip_class >= GFX9 &&
420 tex->buffer.b.b.last_level > 0)
421 continue;
422
423 /* the clear is allowed if all layers are bound */
424 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
425 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
426 continue;
427 }
428
429 /* only supported on tiled surfaces */
430 if (tex->surface.is_linear) {
431 continue;
432 }
433
434 /* shared textures can't use fast clear without an explicit flush,
435 * because there is no way to communicate the clear color among
436 * all clients
437 */
438 if (tex->buffer.b.is_shared &&
439 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
440 continue;
441
442 if (sctx->chip_class <= GFX8 &&
443 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
444 !sctx->screen->info.htile_cmask_support_1d_tiling)
445 continue;
446
447 /* Use a slow clear for small surfaces where the cost of
448 * the eliminate pass can be higher than the benefit of fast
449 * clear. The closed driver does this, but the numbers may differ.
450 *
451 * This helps on both dGPUs and APUs, even small APUs like Mullins.
452 */
453 bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
454 tex->buffer.b.b.width0 *
455 tex->buffer.b.b.height0 <= 512 * 512;
456 bool eliminate_needed = false;
457 bool fmask_decompress_needed = false;
458
459 /* Fast clear is the most appropriate place to enable DCC for
460 * displayable surfaces.
461 */
462 if (sctx->family == CHIP_STONEY && !too_small) {
463 vi_separate_dcc_try_enable(sctx, tex);
464
465 /* RB+ isn't supported with a CMASK clear only on Stoney,
466 * so all clears are considered to be hypothetically slow
467 * clears, which is weighed when determining whether to
468 * enable separate DCC.
469 */
470 if (tex->dcc_gather_statistics) /* only for Stoney */
471 tex->num_slow_clears++;
472 }
473
474 /* Try to clear DCC first, otherwise try CMASK. */
475 if (vi_dcc_enabled(tex, 0)) {
476 uint32_t reset_value;
477
478 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
479 continue;
480
481 /* This can happen with mipmapping or MSAA. */
482 if (sctx->chip_class == GFX8 &&
483 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
484 continue;
485
486 if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
487 fb->cbufs[i]->format,
488 color, &reset_value,
489 &eliminate_needed))
490 continue;
491
492 if (eliminate_needed && too_small)
493 continue;
494
495 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
496 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
497 /* TODO: This doesn't work with MSAA. */
498 if (eliminate_needed)
499 continue;
500
501 uint32_t clear_value = 0xCCCCCCCC;
502 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
503 tex->cmask_offset, tex->surface.cmask_size,
504 &clear_value, 4, SI_COHERENCY_CB_META, false);
505 fmask_decompress_needed = true;
506 }
507
508 vi_dcc_clear_level(sctx, tex, 0, reset_value);
509 tex->separate_dcc_dirty = true;
510 } else {
511 if (too_small)
512 continue;
513
514 /* 128-bit formats are unusupported */
515 if (tex->surface.bpe > 8) {
516 continue;
517 }
518
519 /* RB+ doesn't work with CMASK fast clear on Stoney. */
520 if (sctx->family == CHIP_STONEY)
521 continue;
522
523 /* ensure CMASK is enabled */
524 si_alloc_separate_cmask(sctx->screen, tex);
525 if (!tex->cmask_buffer)
526 continue;
527
528 /* Do the fast clear. */
529 uint32_t clear_value = 0;
530 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
531 tex->cmask_offset, tex->surface.cmask_size,
532 &clear_value, 4, SI_COHERENCY_CB_META, false);
533 eliminate_needed = true;
534 }
535
536 if ((eliminate_needed || fmask_decompress_needed) &&
537 !(tex->dirty_level_mask & (1 << level))) {
538 tex->dirty_level_mask |= 1 << level;
539 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
540 }
541
542 /* We can change the micro tile mode before a full clear. */
543 si_set_optimal_micro_tile_mode(sctx->screen, tex);
544
545 *buffers &= ~clear_bit;
546
547 /* Chips with DCC constant encoding don't need to set the clear
548 * color registers for DCC clear values 0 and 1.
549 */
550 if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
551 continue;
552
553 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
554 sctx->framebuffer.dirty_cbufs |= 1 << i;
555 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
556 }
557 }
558 }
559
560 static void si_clear(struct pipe_context *ctx, unsigned buffers,
561 const union pipe_color_union *color,
562 double depth, unsigned stencil)
563 {
564 struct si_context *sctx = (struct si_context *)ctx;
565 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
566 struct pipe_surface *zsbuf = fb->zsbuf;
567 struct si_texture *zstex =
568 zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
569
570 if (buffers & PIPE_CLEAR_COLOR) {
571 si_do_fast_color_clear(sctx, &buffers, color);
572 if (!buffers)
573 return; /* all buffers have been fast cleared */
574
575 /* These buffers cannot use fast clear, make sure to disable expansion. */
576 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
577 struct si_texture *tex;
578
579 /* If not clearing this buffer, skip. */
580 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
581 continue;
582
583 tex = (struct si_texture *)fb->cbufs[i]->texture;
584 if (tex->surface.fmask_size == 0)
585 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
586 }
587 }
588
589 if (zstex &&
590 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
591 zsbuf->u.tex.first_layer == 0 &&
592 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
593 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
594 if (buffers & PIPE_CLEAR_DEPTH &&
595 (!zstex->tc_compatible_htile ||
596 depth == 0 || depth == 1)) {
597 /* Need to disable EXPCLEAR temporarily if clearing
598 * to a new value. */
599 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
600 sctx->db_depth_disable_expclear = true;
601 }
602
603 if (zstex->depth_clear_value != (float)depth) {
604 /* Update DB_DEPTH_CLEAR. */
605 zstex->depth_clear_value = depth;
606 sctx->framebuffer.dirty_zsbuf = true;
607 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
608 }
609 sctx->db_depth_clear = true;
610 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
611 }
612
613 /* TC-compatible HTILE only supports stencil clears to 0. */
614 if (buffers & PIPE_CLEAR_STENCIL &&
615 (!zstex->tc_compatible_htile || stencil == 0)) {
616 stencil &= 0xff;
617
618 /* Need to disable EXPCLEAR temporarily if clearing
619 * to a new value. */
620 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
621 sctx->db_stencil_disable_expclear = true;
622 }
623
624 if (zstex->stencil_clear_value != (uint8_t)stencil) {
625 /* Update DB_STENCIL_CLEAR. */
626 zstex->stencil_clear_value = stencil;
627 sctx->framebuffer.dirty_zsbuf = true;
628 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
629 }
630 sctx->db_stencil_clear = true;
631 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
632 }
633
634 /* TODO: Find out what's wrong here. Fast depth clear leads to
635 * corruption in ARK: Survival Evolved, but that may just be
636 * a coincidence and the root cause is elsewhere.
637 *
638 * The corruption can be fixed by putting the DB flush before
639 * or after the depth clear. (surprisingly)
640 *
641 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
642 *
643 * This hack decreases back-to-back ClearDepth performance.
644 */
645 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
646 sctx->screen->options.clear_db_cache_before_clear)
647 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
648 }
649
650 si_blitter_begin(sctx, SI_CLEAR);
651 util_blitter_clear(sctx->blitter, fb->width, fb->height,
652 util_framebuffer_get_num_layers(fb),
653 buffers, color, depth, stencil);
654 si_blitter_end(sctx);
655
656 if (sctx->db_depth_clear) {
657 sctx->db_depth_clear = false;
658 sctx->db_depth_disable_expclear = false;
659 zstex->depth_cleared = true;
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
661 }
662
663 if (sctx->db_stencil_clear) {
664 sctx->db_stencil_clear = false;
665 sctx->db_stencil_disable_expclear = false;
666 zstex->stencil_cleared = true;
667 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
668 }
669 }
670
671 static void si_clear_render_target(struct pipe_context *ctx,
672 struct pipe_surface *dst,
673 const union pipe_color_union *color,
674 unsigned dstx, unsigned dsty,
675 unsigned width, unsigned height,
676 bool render_condition_enabled)
677 {
678 struct si_context *sctx = (struct si_context *)ctx;
679 struct si_texture *sdst = (struct si_texture*)dst->texture;
680
681 if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
682 si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width,
683 height, render_condition_enabled);
684 return;
685 }
686
687 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
688 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
689 util_blitter_clear_render_target(sctx->blitter, dst, color,
690 dstx, dsty, width, height);
691 si_blitter_end(sctx);
692 }
693
694 static void si_clear_depth_stencil(struct pipe_context *ctx,
695 struct pipe_surface *dst,
696 unsigned clear_flags,
697 double depth,
698 unsigned stencil,
699 unsigned dstx, unsigned dsty,
700 unsigned width, unsigned height,
701 bool render_condition_enabled)
702 {
703 struct si_context *sctx = (struct si_context *)ctx;
704
705 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
706 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
707 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
708 dstx, dsty, width, height);
709 si_blitter_end(sctx);
710 }
711
712 static void si_clear_texture(struct pipe_context *pipe,
713 struct pipe_resource *tex,
714 unsigned level,
715 const struct pipe_box *box,
716 const void *data)
717 {
718 struct pipe_screen *screen = pipe->screen;
719 struct si_texture *stex = (struct si_texture*)tex;
720 struct pipe_surface tmpl = {{0}};
721 struct pipe_surface *sf;
722 const struct util_format_description *desc =
723 util_format_description(tex->format);
724
725 tmpl.format = tex->format;
726 tmpl.u.tex.first_layer = box->z;
727 tmpl.u.tex.last_layer = box->z + box->depth - 1;
728 tmpl.u.tex.level = level;
729 sf = pipe->create_surface(pipe, tex, &tmpl);
730 if (!sf)
731 return;
732
733 if (stex->is_depth) {
734 unsigned clear;
735 float depth;
736 uint8_t stencil = 0;
737
738 /* Depth is always present. */
739 clear = PIPE_CLEAR_DEPTH;
740 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
741
742 if (stex->surface.has_stencil) {
743 clear |= PIPE_CLEAR_STENCIL;
744 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
745 }
746
747 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
748 box->x, box->y,
749 box->width, box->height, false);
750 } else {
751 union pipe_color_union color;
752
753 /* pipe_color_union requires the full vec4 representation. */
754 if (util_format_is_pure_uint(tex->format))
755 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
756 else if (util_format_is_pure_sint(tex->format))
757 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
758 else
759 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
760
761 if (screen->is_format_supported(screen, tex->format,
762 tex->target, 0, 0,
763 PIPE_BIND_RENDER_TARGET)) {
764 si_clear_render_target(pipe, sf, &color,
765 box->x, box->y,
766 box->width, box->height, false);
767 } else {
768 /* Software fallback - just for R9G9B9E5_FLOAT */
769 util_clear_render_target(pipe, sf, &color,
770 box->x, box->y,
771 box->width, box->height);
772 }
773 }
774 pipe_surface_reference(&sf, NULL);
775 }
776
777 void si_init_clear_functions(struct si_context *sctx)
778 {
779 sctx->b.clear_render_target = si_clear_render_target;
780 sctx->b.clear_texture = si_clear_texture;
781
782 if (sctx->has_graphics) {
783 sctx->b.clear = si_clear;
784 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
785 }
786 }