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radeonsi: move CMASK size computation into ac_surface
[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct si_texture *tex)
39 {
40 if (tex->cmask_buffer)
41 return;
42
43 assert(tex->cmask.size == 0);
44
45 if (!tex->surface.cmask_size)
46 return;
47
48 tex->cmask_buffer =
49 si_aligned_buffer_create(&sscreen->b,
50 SI_RESOURCE_FLAG_UNMAPPABLE,
51 PIPE_USAGE_DEFAULT,
52 tex->surface.cmask_size,
53 tex->surface.cmask_alignment);
54 if (tex->cmask_buffer == NULL)
55 return;
56
57 tex->cmask.size = tex->surface.cmask_size;
58 tex->cmask.base_address_reg = tex->cmask_buffer->gpu_address >> 8;
59 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
60
61 p_atomic_inc(&sscreen->compressed_colortex_counter);
62 }
63
64 static bool si_set_clear_color(struct si_texture *tex,
65 enum pipe_format surface_format,
66 const union pipe_color_union *color)
67 {
68 union util_color uc;
69
70 memset(&uc, 0, sizeof(uc));
71
72 if (tex->surface.bpe == 16) {
73 /* DCC fast clear only:
74 * CLEAR_WORD0 = R = G = B
75 * CLEAR_WORD1 = A
76 */
77 assert(color->ui[0] == color->ui[1] &&
78 color->ui[0] == color->ui[2]);
79 uc.ui[0] = color->ui[0];
80 uc.ui[1] = color->ui[3];
81 } else if (util_format_is_pure_uint(surface_format)) {
82 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
83 } else if (util_format_is_pure_sint(surface_format)) {
84 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
85 } else {
86 util_pack_color(color->f, surface_format, &uc);
87 }
88
89 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
90 return false;
91
92 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
93 return true;
94 }
95
96 /** Linearize and convert luminace/intensity to red. */
97 enum pipe_format si_simplify_cb_format(enum pipe_format format)
98 {
99 format = util_format_linear(format);
100 format = util_format_luminance_to_red(format);
101 return util_format_intensity_to_red(format);
102 }
103
104 bool vi_alpha_is_on_msb(enum pipe_format format)
105 {
106 format = si_simplify_cb_format(format);
107
108 /* Formats with 3 channels can't have alpha. */
109 if (util_format_description(format)->nr_channels == 3)
110 return true; /* same as xxxA; is any value OK here? */
111
112 return si_translate_colorswap(format, false) <= 1;
113 }
114
115 static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
116 enum pipe_format surface_format,
117 const union pipe_color_union *color,
118 uint32_t* clear_value,
119 bool *eliminate_needed)
120 {
121 /* If we want to clear without needing a fast clear eliminate step, we
122 * can set color and alpha independently to 0 or 1 (or 0/max for integer
123 * formats).
124 */
125 bool values[4] = {}; /* whether to clear to 0 or 1 */
126 bool color_value = false; /* clear color to 0 or 1 */
127 bool alpha_value = false; /* clear alpha to 0 or 1 */
128 int alpha_channel; /* index of the alpha component */
129 bool has_color = false;
130 bool has_alpha = false;
131
132 const struct util_format_description *desc =
133 util_format_description(si_simplify_cb_format(surface_format));
134
135 /* 128-bit fast clear with different R,G,B values is unsupported. */
136 if (desc->block.bits == 128 &&
137 (color->ui[0] != color->ui[1] ||
138 color->ui[0] != color->ui[2]))
139 return false;
140
141 *eliminate_needed = true;
142 *clear_value = 0x20202020U; /* use CB clear color registers */
143
144 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
145 return true; /* need ELIMINATE_FAST_CLEAR */
146
147 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
148 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
149
150 /* Formats with 3 channels can't have alpha. */
151 if (desc->nr_channels == 3)
152 alpha_channel = -1;
153 else if (surf_alpha_is_on_msb)
154 alpha_channel = desc->nr_channels - 1;
155 else
156 alpha_channel = 0;
157
158 for (int i = 0; i < 4; ++i) {
159 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
160 continue;
161
162 if (desc->channel[i].pure_integer &&
163 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
164 /* Use the maximum value for clamping the clear color. */
165 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
166
167 values[i] = color->i[i] != 0;
168 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
169 return true; /* need ELIMINATE_FAST_CLEAR */
170 } else if (desc->channel[i].pure_integer &&
171 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
172 /* Use the maximum value for clamping the clear color. */
173 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
174
175 values[i] = color->ui[i] != 0U;
176 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
177 return true; /* need ELIMINATE_FAST_CLEAR */
178 } else {
179 values[i] = color->f[i] != 0.0F;
180 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
181 return true; /* need ELIMINATE_FAST_CLEAR */
182 }
183
184 if (desc->swizzle[i] == alpha_channel) {
185 alpha_value = values[i];
186 has_alpha = true;
187 } else {
188 color_value = values[i];
189 has_color = true;
190 }
191 }
192
193 /* If alpha isn't present, make it the same as color, and vice versa. */
194 if (!has_alpha)
195 alpha_value = color_value;
196 else if (!has_color)
197 color_value = alpha_value;
198
199 if (color_value != alpha_value &&
200 base_alpha_is_on_msb != surf_alpha_is_on_msb)
201 return true; /* require ELIMINATE_FAST_CLEAR */
202
203 /* Check if all color values are equal if they are present. */
204 for (int i = 0; i < 4; ++i) {
205 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
206 desc->swizzle[i] != alpha_channel &&
207 values[i] != color_value)
208 return true; /* require ELIMINATE_FAST_CLEAR */
209 }
210
211 /* This doesn't need ELIMINATE_FAST_CLEAR.
212 * CB uses both the DCC clear codes and the CB clear color registers,
213 * so they must match.
214 */
215 *eliminate_needed = false;
216
217 if (color_value)
218 *clear_value |= 0x80808080U;
219 if (alpha_value)
220 *clear_value |= 0x40404040U;
221 return true;
222 }
223
224 void vi_dcc_clear_level(struct si_context *sctx,
225 struct si_texture *tex,
226 unsigned level, unsigned clear_value)
227 {
228 struct pipe_resource *dcc_buffer;
229 uint64_t dcc_offset, clear_size;
230
231 assert(vi_dcc_enabled(tex, level));
232
233 if (tex->dcc_separate_buffer) {
234 dcc_buffer = &tex->dcc_separate_buffer->b.b;
235 dcc_offset = 0;
236 } else {
237 dcc_buffer = &tex->buffer.b.b;
238 dcc_offset = tex->dcc_offset;
239 }
240
241 if (sctx->chip_class >= GFX9) {
242 /* Mipmap level clears aren't implemented. */
243 assert(tex->buffer.b.b.last_level == 0);
244 /* 4x and 8x MSAA needs a sophisticated compute shader for
245 * the clear. See AMDVLK. */
246 assert(tex->num_color_samples <= 2);
247 clear_size = tex->surface.dcc_size;
248 } else {
249 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
250
251 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
252 assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
253 /* Layered 4x and 8x MSAA DCC fast clears need to clear
254 * dcc_fast_clear_size bytes for each layer. A compute shader
255 * would be more efficient than separate per-layer clear operations.
256 */
257 assert(tex->num_color_samples <= 2 || num_layers == 1);
258
259 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
260 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
261 num_layers;
262 }
263
264 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
265 clear_value, SI_COHERENCY_CB_META);
266 }
267
268 /* Set the same micro tile mode as the destination of the last MSAA resolve.
269 * This allows hitting the MSAA resolve fast path, which requires that both
270 * src and dst micro tile modes match.
271 */
272 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
273 struct si_texture *tex)
274 {
275 if (tex->buffer.b.is_shared ||
276 tex->buffer.b.b.nr_samples <= 1 ||
277 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
278 return;
279
280 assert(sscreen->info.chip_class >= GFX9 ||
281 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
282 assert(tex->buffer.b.b.last_level == 0);
283
284 if (sscreen->info.chip_class >= GFX9) {
285 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
286 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
287
288 /* If you do swizzle_mode % 4, you'll get:
289 * 0 = Depth
290 * 1 = Standard,
291 * 2 = Displayable
292 * 3 = Rotated
293 *
294 * Depth-sample order isn't allowed:
295 */
296 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
297
298 switch (tex->last_msaa_resolve_target_micro_mode) {
299 case RADEON_MICRO_MODE_DISPLAY:
300 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
301 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
302 break;
303 case RADEON_MICRO_MODE_THIN:
304 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
305 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
306 break;
307 case RADEON_MICRO_MODE_ROTATED:
308 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
309 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
310 break;
311 default: /* depth */
312 assert(!"unexpected micro mode");
313 return;
314 }
315 } else if (sscreen->info.chip_class >= CIK) {
316 /* These magic numbers were copied from addrlib. It doesn't use
317 * any definitions for them either. They are all 2D_TILED_THIN1
318 * modes with different bpp and micro tile mode.
319 */
320 switch (tex->last_msaa_resolve_target_micro_mode) {
321 case RADEON_MICRO_MODE_DISPLAY:
322 tex->surface.u.legacy.tiling_index[0] = 10;
323 break;
324 case RADEON_MICRO_MODE_THIN:
325 tex->surface.u.legacy.tiling_index[0] = 14;
326 break;
327 case RADEON_MICRO_MODE_ROTATED:
328 tex->surface.u.legacy.tiling_index[0] = 28;
329 break;
330 default: /* depth, thick */
331 assert(!"unexpected micro mode");
332 return;
333 }
334 } else { /* SI */
335 switch (tex->last_msaa_resolve_target_micro_mode) {
336 case RADEON_MICRO_MODE_DISPLAY:
337 switch (tex->surface.bpe) {
338 case 1:
339 tex->surface.u.legacy.tiling_index[0] = 10;
340 break;
341 case 2:
342 tex->surface.u.legacy.tiling_index[0] = 11;
343 break;
344 default: /* 4, 8 */
345 tex->surface.u.legacy.tiling_index[0] = 12;
346 break;
347 }
348 break;
349 case RADEON_MICRO_MODE_THIN:
350 switch (tex->surface.bpe) {
351 case 1:
352 tex->surface.u.legacy.tiling_index[0] = 14;
353 break;
354 case 2:
355 tex->surface.u.legacy.tiling_index[0] = 15;
356 break;
357 case 4:
358 tex->surface.u.legacy.tiling_index[0] = 16;
359 break;
360 default: /* 8, 16 */
361 tex->surface.u.legacy.tiling_index[0] = 17;
362 break;
363 }
364 break;
365 default: /* depth, thick */
366 assert(!"unexpected micro mode");
367 return;
368 }
369 }
370
371 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
372
373 p_atomic_inc(&sscreen->dirty_tex_counter);
374 }
375
376 static void si_do_fast_color_clear(struct si_context *sctx,
377 unsigned *buffers,
378 const union pipe_color_union *color)
379 {
380 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
381 int i;
382
383 /* This function is broken in BE, so just disable this path for now */
384 #ifdef PIPE_ARCH_BIG_ENDIAN
385 return;
386 #endif
387
388 if (sctx->render_cond)
389 return;
390
391 for (i = 0; i < fb->nr_cbufs; i++) {
392 struct si_texture *tex;
393 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
394
395 if (!fb->cbufs[i])
396 continue;
397
398 /* if this colorbuffer is not being cleared */
399 if (!(*buffers & clear_bit))
400 continue;
401
402 unsigned level = fb->cbufs[i]->u.tex.level;
403 if (level > 0)
404 continue;
405
406 tex = (struct si_texture *)fb->cbufs[i]->texture;
407
408 /* TODO: GFX9: Implement DCC fast clear for level 0 of
409 * mipmapped textures. Mipmapped DCC has to clear a rectangular
410 * area of DCC for level 0 (because the whole miptree is
411 * organized in a 2D plane).
412 */
413 if (sctx->chip_class >= GFX9 &&
414 tex->buffer.b.b.last_level > 0)
415 continue;
416
417 /* the clear is allowed if all layers are bound */
418 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
419 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
420 continue;
421 }
422
423 /* only supported on tiled surfaces */
424 if (tex->surface.is_linear) {
425 continue;
426 }
427
428 /* shared textures can't use fast clear without an explicit flush,
429 * because there is no way to communicate the clear color among
430 * all clients
431 */
432 if (tex->buffer.b.is_shared &&
433 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
434 continue;
435
436 if (sctx->chip_class <= VI &&
437 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
438 !sctx->screen->info.htile_cmask_support_1d_tiling)
439 continue;
440
441 /* Fast clear is the most appropriate place to enable DCC for
442 * displayable surfaces.
443 */
444 if (sctx->chip_class >= VI &&
445 !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
446 vi_separate_dcc_try_enable(sctx, tex);
447
448 /* RB+ isn't supported with a CMASK clear only on Stoney,
449 * so all clears are considered to be hypothetically slow
450 * clears, which is weighed when determining whether to
451 * enable separate DCC.
452 */
453 if (tex->dcc_gather_statistics &&
454 sctx->family == CHIP_STONEY)
455 tex->num_slow_clears++;
456 }
457
458 bool need_decompress_pass = false;
459
460 /* Use a slow clear for small surfaces where the cost of
461 * the eliminate pass can be higher than the benefit of fast
462 * clear. The closed driver does this, but the numbers may differ.
463 *
464 * This helps on both dGPUs and APUs, even small APUs like Mullins.
465 */
466 bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
467 tex->buffer.b.b.width0 *
468 tex->buffer.b.b.height0 <= 512 * 512;
469
470 /* Try to clear DCC first, otherwise try CMASK. */
471 if (vi_dcc_enabled(tex, 0)) {
472 uint32_t reset_value;
473 bool eliminate_needed;
474
475 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
476 continue;
477
478 /* This can happen with mipmapping or MSAA. */
479 if (sctx->chip_class == VI &&
480 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
481 continue;
482
483 if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
484 fb->cbufs[i]->format,
485 color, &reset_value,
486 &eliminate_needed))
487 continue;
488
489 if (eliminate_needed && too_small)
490 continue;
491
492 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
493 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask.size) {
494 /* TODO: This doesn't work with MSAA. */
495 if (eliminate_needed)
496 continue;
497
498 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
499 tex->cmask.offset, tex->cmask.size,
500 0xCCCCCCCC, SI_COHERENCY_CB_META);
501 need_decompress_pass = true;
502 }
503
504 vi_dcc_clear_level(sctx, tex, 0, reset_value);
505
506 if (eliminate_needed)
507 need_decompress_pass = true;
508
509 tex->separate_dcc_dirty = true;
510 } else {
511 if (too_small)
512 continue;
513
514 /* 128-bit formats are unusupported */
515 if (tex->surface.bpe > 8) {
516 continue;
517 }
518
519 /* RB+ doesn't work with CMASK fast clear on Stoney. */
520 if (sctx->family == CHIP_STONEY)
521 continue;
522
523 /* ensure CMASK is enabled */
524 si_alloc_separate_cmask(sctx->screen, tex);
525 if (tex->cmask.size == 0) {
526 continue;
527 }
528
529 /* Do the fast clear. */
530 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
531 tex->cmask.offset, tex->cmask.size, 0,
532 SI_COHERENCY_CB_META);
533 need_decompress_pass = true;
534 }
535
536 if (need_decompress_pass &&
537 !(tex->dirty_level_mask & (1 << level))) {
538 tex->dirty_level_mask |= 1 << level;
539 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
540 }
541
542 /* We can change the micro tile mode before a full clear. */
543 si_set_optimal_micro_tile_mode(sctx->screen, tex);
544
545 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
546 sctx->framebuffer.dirty_cbufs |= 1 << i;
547 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
548 }
549 *buffers &= ~clear_bit;
550 }
551 }
552
553 static void si_clear(struct pipe_context *ctx, unsigned buffers,
554 const union pipe_color_union *color,
555 double depth, unsigned stencil)
556 {
557 struct si_context *sctx = (struct si_context *)ctx;
558 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
559 struct pipe_surface *zsbuf = fb->zsbuf;
560 struct si_texture *zstex =
561 zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
562
563 if (buffers & PIPE_CLEAR_COLOR) {
564 si_do_fast_color_clear(sctx, &buffers, color);
565 if (!buffers)
566 return; /* all buffers have been fast cleared */
567
568 /* These buffers cannot use fast clear, make sure to disable expansion. */
569 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
570 struct si_texture *tex;
571
572 /* If not clearing this buffer, skip. */
573 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
574 continue;
575
576 tex = (struct si_texture *)fb->cbufs[i]->texture;
577 if (tex->surface.fmask_size == 0)
578 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
579 }
580 }
581
582 if (zstex &&
583 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
584 zsbuf->u.tex.first_layer == 0 &&
585 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
586 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
587 if (buffers & PIPE_CLEAR_DEPTH &&
588 (!zstex->tc_compatible_htile ||
589 depth == 0 || depth == 1)) {
590 /* Need to disable EXPCLEAR temporarily if clearing
591 * to a new value. */
592 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
593 sctx->db_depth_disable_expclear = true;
594 }
595
596 if (zstex->depth_clear_value != (float)depth) {
597 /* Update DB_DEPTH_CLEAR. */
598 zstex->depth_clear_value = depth;
599 sctx->framebuffer.dirty_zsbuf = true;
600 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
601 }
602 sctx->db_depth_clear = true;
603 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
604 }
605
606 /* TC-compatible HTILE only supports stencil clears to 0. */
607 if (buffers & PIPE_CLEAR_STENCIL &&
608 (!zstex->tc_compatible_htile || stencil == 0)) {
609 stencil &= 0xff;
610
611 /* Need to disable EXPCLEAR temporarily if clearing
612 * to a new value. */
613 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
614 sctx->db_stencil_disable_expclear = true;
615 }
616
617 if (zstex->stencil_clear_value != (uint8_t)stencil) {
618 /* Update DB_STENCIL_CLEAR. */
619 zstex->stencil_clear_value = stencil;
620 sctx->framebuffer.dirty_zsbuf = true;
621 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
622 }
623 sctx->db_stencil_clear = true;
624 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
625 }
626
627 /* TODO: Find out what's wrong here. Fast depth clear leads to
628 * corruption in ARK: Survival Evolved, but that may just be
629 * a coincidence and the root cause is elsewhere.
630 *
631 * The corruption can be fixed by putting the DB flush before
632 * or after the depth clear. (surprisingly)
633 *
634 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
635 *
636 * This hack decreases back-to-back ClearDepth performance.
637 */
638 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
639 sctx->screen->clear_db_cache_before_clear)
640 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
641 }
642
643 si_blitter_begin(sctx, SI_CLEAR);
644 util_blitter_clear(sctx->blitter, fb->width, fb->height,
645 util_framebuffer_get_num_layers(fb),
646 buffers, color, depth, stencil);
647 si_blitter_end(sctx);
648
649 if (sctx->db_depth_clear) {
650 sctx->db_depth_clear = false;
651 sctx->db_depth_disable_expclear = false;
652 zstex->depth_cleared = true;
653 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
654 }
655
656 if (sctx->db_stencil_clear) {
657 sctx->db_stencil_clear = false;
658 sctx->db_stencil_disable_expclear = false;
659 zstex->stencil_cleared = true;
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
661 }
662 }
663
664 static void si_clear_render_target(struct pipe_context *ctx,
665 struct pipe_surface *dst,
666 const union pipe_color_union *color,
667 unsigned dstx, unsigned dsty,
668 unsigned width, unsigned height,
669 bool render_condition_enabled)
670 {
671 struct si_context *sctx = (struct si_context *)ctx;
672
673 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
674 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
675 util_blitter_clear_render_target(sctx->blitter, dst, color,
676 dstx, dsty, width, height);
677 si_blitter_end(sctx);
678 }
679
680 static void si_clear_depth_stencil(struct pipe_context *ctx,
681 struct pipe_surface *dst,
682 unsigned clear_flags,
683 double depth,
684 unsigned stencil,
685 unsigned dstx, unsigned dsty,
686 unsigned width, unsigned height,
687 bool render_condition_enabled)
688 {
689 struct si_context *sctx = (struct si_context *)ctx;
690
691 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
692 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
693 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
694 dstx, dsty, width, height);
695 si_blitter_end(sctx);
696 }
697
698 static void si_clear_texture(struct pipe_context *pipe,
699 struct pipe_resource *tex,
700 unsigned level,
701 const struct pipe_box *box,
702 const void *data)
703 {
704 struct pipe_screen *screen = pipe->screen;
705 struct si_texture *stex = (struct si_texture*)tex;
706 struct pipe_surface tmpl = {{0}};
707 struct pipe_surface *sf;
708 const struct util_format_description *desc =
709 util_format_description(tex->format);
710
711 tmpl.format = tex->format;
712 tmpl.u.tex.first_layer = box->z;
713 tmpl.u.tex.last_layer = box->z + box->depth - 1;
714 tmpl.u.tex.level = level;
715 sf = pipe->create_surface(pipe, tex, &tmpl);
716 if (!sf)
717 return;
718
719 if (stex->is_depth) {
720 unsigned clear;
721 float depth;
722 uint8_t stencil = 0;
723
724 /* Depth is always present. */
725 clear = PIPE_CLEAR_DEPTH;
726 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
727
728 if (stex->surface.has_stencil) {
729 clear |= PIPE_CLEAR_STENCIL;
730 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
731 }
732
733 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
734 box->x, box->y,
735 box->width, box->height, false);
736 } else {
737 union pipe_color_union color;
738
739 /* pipe_color_union requires the full vec4 representation. */
740 if (util_format_is_pure_uint(tex->format))
741 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
742 else if (util_format_is_pure_sint(tex->format))
743 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
744 else
745 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
746
747 if (screen->is_format_supported(screen, tex->format,
748 tex->target, 0,
749 PIPE_BIND_RENDER_TARGET)) {
750 si_clear_render_target(pipe, sf, &color,
751 box->x, box->y,
752 box->width, box->height, false);
753 } else {
754 /* Software fallback - just for R9G9B9E5_FLOAT */
755 util_clear_render_target(pipe, sf, &color,
756 box->x, box->y,
757 box->width, box->height);
758 }
759 }
760 pipe_surface_reference(&sf, NULL);
761 }
762
763 void si_init_clear_functions(struct si_context *sctx)
764 {
765 sctx->b.clear = si_clear;
766 sctx->b.clear_render_target = si_clear_render_target;
767 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
768 sctx->b.clear_texture = si_clear_texture;
769 }