2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/format/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
33 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
34 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
37 static void si_alloc_separate_cmask(struct si_screen
*sscreen
,
38 struct si_texture
*tex
)
40 /* CMASK for MSAA is allocated in advance or always disabled
41 * by "nofmask" option.
43 if (tex
->cmask_buffer
|| !tex
->surface
.cmask_size
||
44 tex
->buffer
.b
.b
.nr_samples
>= 2)
48 si_aligned_buffer_create(&sscreen
->b
,
49 SI_RESOURCE_FLAG_UNMAPPABLE
,
51 tex
->surface
.cmask_size
,
52 tex
->surface
.cmask_alignment
);
53 if (tex
->cmask_buffer
== NULL
)
56 tex
->cmask_base_address_reg
= tex
->cmask_buffer
->gpu_address
>> 8;
57 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
59 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
62 static bool si_set_clear_color(struct si_texture
*tex
,
63 enum pipe_format surface_format
,
64 const union pipe_color_union
*color
)
68 memset(&uc
, 0, sizeof(uc
));
70 if (tex
->surface
.bpe
== 16) {
71 /* DCC fast clear only:
72 * CLEAR_WORD0 = R = G = B
75 assert(color
->ui
[0] == color
->ui
[1] &&
76 color
->ui
[0] == color
->ui
[2]);
77 uc
.ui
[0] = color
->ui
[0];
78 uc
.ui
[1] = color
->ui
[3];
80 util_pack_color_union(surface_format
, &uc
, color
);
83 if (memcmp(tex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t)) == 0)
86 memcpy(tex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
90 /** Linearize and convert luminace/intensity to red. */
91 enum pipe_format
si_simplify_cb_format(enum pipe_format format
)
93 format
= util_format_linear(format
);
94 format
= util_format_luminance_to_red(format
);
95 return util_format_intensity_to_red(format
);
98 bool vi_alpha_is_on_msb(struct si_screen
*sscreen
, enum pipe_format format
)
100 format
= si_simplify_cb_format(format
);
101 const struct util_format_description
*desc
= util_format_description(format
);
103 /* Formats with 3 channels can't have alpha. */
104 if (desc
->nr_channels
== 3)
105 return true; /* same as xxxA; is any value OK here? */
107 if (sscreen
->info
.chip_class
>= GFX10
&& desc
->nr_channels
== 1)
108 return desc
->swizzle
[3] == PIPE_SWIZZLE_X
;
110 return si_translate_colorswap(format
, false) <= 1;
113 static bool vi_get_fast_clear_parameters(struct si_screen
*sscreen
,
114 enum pipe_format base_format
,
115 enum pipe_format surface_format
,
116 const union pipe_color_union
*color
,
117 uint32_t* clear_value
,
118 bool *eliminate_needed
)
120 /* If we want to clear without needing a fast clear eliminate step, we
121 * can set color and alpha independently to 0 or 1 (or 0/max for integer
124 bool values
[4] = {}; /* whether to clear to 0 or 1 */
125 bool color_value
= false; /* clear color to 0 or 1 */
126 bool alpha_value
= false; /* clear alpha to 0 or 1 */
127 int alpha_channel
; /* index of the alpha component */
128 bool has_color
= false;
129 bool has_alpha
= false;
131 const struct util_format_description
*desc
=
132 util_format_description(si_simplify_cb_format(surface_format
));
134 /* 128-bit fast clear with different R,G,B values is unsupported. */
135 if (desc
->block
.bits
== 128 &&
136 (color
->ui
[0] != color
->ui
[1] ||
137 color
->ui
[0] != color
->ui
[2]))
140 *eliminate_needed
= true;
141 *clear_value
= DCC_CLEAR_COLOR_REG
;
143 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
144 return true; /* need ELIMINATE_FAST_CLEAR */
146 bool base_alpha_is_on_msb
= vi_alpha_is_on_msb(sscreen
, base_format
);
147 bool surf_alpha_is_on_msb
= vi_alpha_is_on_msb(sscreen
, surface_format
);
149 /* Formats with 3 channels can't have alpha. */
150 if (desc
->nr_channels
== 3)
152 else if (surf_alpha_is_on_msb
)
153 alpha_channel
= desc
->nr_channels
- 1;
157 for (int i
= 0; i
< 4; ++i
) {
158 if (desc
->swizzle
[i
] >= PIPE_SWIZZLE_0
)
161 if (desc
->channel
[i
].pure_integer
&&
162 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
163 /* Use the maximum value for clamping the clear color. */
164 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
166 values
[i
] = color
->i
[i
] != 0;
167 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
168 return true; /* need ELIMINATE_FAST_CLEAR */
169 } else if (desc
->channel
[i
].pure_integer
&&
170 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
171 /* Use the maximum value for clamping the clear color. */
172 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
174 values
[i
] = color
->ui
[i
] != 0U;
175 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
176 return true; /* need ELIMINATE_FAST_CLEAR */
178 values
[i
] = color
->f
[i
] != 0.0F
;
179 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
180 return true; /* need ELIMINATE_FAST_CLEAR */
183 if (desc
->swizzle
[i
] == alpha_channel
) {
184 alpha_value
= values
[i
];
187 color_value
= values
[i
];
192 /* If alpha isn't present, make it the same as color, and vice versa. */
194 alpha_value
= color_value
;
196 color_value
= alpha_value
;
198 if (color_value
!= alpha_value
&&
199 base_alpha_is_on_msb
!= surf_alpha_is_on_msb
)
200 return true; /* require ELIMINATE_FAST_CLEAR */
202 /* Check if all color values are equal if they are present. */
203 for (int i
= 0; i
< 4; ++i
) {
204 if (desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
205 desc
->swizzle
[i
] != alpha_channel
&&
206 values
[i
] != color_value
)
207 return true; /* require ELIMINATE_FAST_CLEAR */
210 /* This doesn't need ELIMINATE_FAST_CLEAR.
211 * On chips predating Raven2, the DCC clear codes and the CB clear
212 * color registers must match.
214 *eliminate_needed
= false;
218 *clear_value
= DCC_CLEAR_COLOR_1111
;
220 *clear_value
= DCC_CLEAR_COLOR_1110
;
223 *clear_value
= DCC_CLEAR_COLOR_0001
;
225 *clear_value
= DCC_CLEAR_COLOR_0000
;
230 bool vi_dcc_clear_level(struct si_context
*sctx
,
231 struct si_texture
*tex
,
232 unsigned level
, unsigned clear_value
)
234 struct pipe_resource
*dcc_buffer
;
235 uint64_t dcc_offset
, clear_size
;
237 assert(vi_dcc_enabled(tex
, level
));
239 if (tex
->dcc_separate_buffer
) {
240 dcc_buffer
= &tex
->dcc_separate_buffer
->b
.b
;
243 dcc_buffer
= &tex
->buffer
.b
.b
;
244 dcc_offset
= tex
->surface
.dcc_offset
;
247 if (sctx
->chip_class
>= GFX9
) {
248 /* Mipmap level clears aren't implemented. */
249 if (tex
->buffer
.b
.b
.last_level
> 0)
252 /* 4x and 8x MSAA needs a sophisticated compute shader for
253 * the clear. See AMDVLK. */
254 if (tex
->buffer
.b
.b
.nr_storage_samples
>= 4)
257 clear_size
= tex
->surface
.dcc_size
;
259 unsigned num_layers
= util_num_layers(&tex
->buffer
.b
.b
, level
);
261 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
262 if (!tex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
)
265 /* Layered 4x and 8x MSAA DCC fast clears need to clear
266 * dcc_fast_clear_size bytes for each layer. A compute shader
267 * would be more efficient than separate per-layer clear operations.
269 if (tex
->buffer
.b
.b
.nr_storage_samples
>= 4 && num_layers
> 1)
272 dcc_offset
+= tex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
273 clear_size
= tex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
*
277 si_clear_buffer(sctx
, dcc_buffer
, dcc_offset
, clear_size
,
278 &clear_value
, 4, SI_COHERENCY_CB_META
, false);
282 /* Set the same micro tile mode as the destination of the last MSAA resolve.
283 * This allows hitting the MSAA resolve fast path, which requires that both
284 * src and dst micro tile modes match.
286 static void si_set_optimal_micro_tile_mode(struct si_screen
*sscreen
,
287 struct si_texture
*tex
)
289 if (sscreen
->info
.chip_class
>= GFX10
||
290 tex
->buffer
.b
.is_shared
||
291 tex
->buffer
.b
.b
.nr_samples
<= 1 ||
292 tex
->surface
.micro_tile_mode
== tex
->last_msaa_resolve_target_micro_mode
)
295 assert(sscreen
->info
.chip_class
>= GFX9
||
296 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
297 assert(tex
->buffer
.b
.b
.last_level
== 0);
299 if (sscreen
->info
.chip_class
>= GFX9
) {
300 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
301 assert(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
303 /* If you do swizzle_mode % 4, you'll get:
309 * Depth-sample order isn't allowed:
311 assert(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
313 switch (tex
->last_msaa_resolve_target_micro_mode
) {
314 case RADEON_MICRO_MODE_DISPLAY
:
315 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
316 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
318 case RADEON_MICRO_MODE_THIN
:
319 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
320 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
322 case RADEON_MICRO_MODE_ROTATED
:
323 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
324 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
327 assert(!"unexpected micro mode");
330 } else if (sscreen
->info
.chip_class
>= GFX7
) {
331 /* These magic numbers were copied from addrlib. It doesn't use
332 * any definitions for them either. They are all 2D_TILED_THIN1
333 * modes with different bpp and micro tile mode.
335 switch (tex
->last_msaa_resolve_target_micro_mode
) {
336 case RADEON_MICRO_MODE_DISPLAY
:
337 tex
->surface
.u
.legacy
.tiling_index
[0] = 10;
339 case RADEON_MICRO_MODE_THIN
:
340 tex
->surface
.u
.legacy
.tiling_index
[0] = 14;
342 case RADEON_MICRO_MODE_ROTATED
:
343 tex
->surface
.u
.legacy
.tiling_index
[0] = 28;
345 default: /* depth, thick */
346 assert(!"unexpected micro mode");
350 switch (tex
->last_msaa_resolve_target_micro_mode
) {
351 case RADEON_MICRO_MODE_DISPLAY
:
352 switch (tex
->surface
.bpe
) {
354 tex
->surface
.u
.legacy
.tiling_index
[0] = 10;
357 tex
->surface
.u
.legacy
.tiling_index
[0] = 11;
360 tex
->surface
.u
.legacy
.tiling_index
[0] = 12;
364 case RADEON_MICRO_MODE_THIN
:
365 switch (tex
->surface
.bpe
) {
367 tex
->surface
.u
.legacy
.tiling_index
[0] = 14;
370 tex
->surface
.u
.legacy
.tiling_index
[0] = 15;
373 tex
->surface
.u
.legacy
.tiling_index
[0] = 16;
376 tex
->surface
.u
.legacy
.tiling_index
[0] = 17;
380 default: /* depth, thick */
381 assert(!"unexpected micro mode");
386 tex
->surface
.micro_tile_mode
= tex
->last_msaa_resolve_target_micro_mode
;
388 p_atomic_inc(&sscreen
->dirty_tex_counter
);
391 static void si_do_fast_color_clear(struct si_context
*sctx
,
393 const union pipe_color_union
*color
)
395 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
398 /* This function is broken in BE, so just disable this path for now */
399 #if UTIL_ARCH_BIG_ENDIAN
403 if (sctx
->render_cond
)
406 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
407 struct si_texture
*tex
;
408 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
413 /* if this colorbuffer is not being cleared */
414 if (!(*buffers
& clear_bit
))
417 unsigned level
= fb
->cbufs
[i
]->u
.tex
.level
;
421 tex
= (struct si_texture
*)fb
->cbufs
[i
]->texture
;
423 /* TODO: GFX9: Implement DCC fast clear for level 0 of
424 * mipmapped textures. Mipmapped DCC has to clear a rectangular
425 * area of DCC for level 0 (because the whole miptree is
426 * organized in a 2D plane).
428 if (sctx
->chip_class
>= GFX9
&&
429 tex
->buffer
.b
.b
.last_level
> 0)
432 /* the clear is allowed if all layers are bound */
433 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
434 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->buffer
.b
.b
, 0)) {
438 /* only supported on tiled surfaces */
439 if (tex
->surface
.is_linear
) {
443 /* shared textures can't use fast clear without an explicit flush,
444 * because there is no way to communicate the clear color among
447 if (tex
->buffer
.b
.is_shared
&&
448 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
451 if (sctx
->chip_class
<= GFX8
&&
452 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
453 !sctx
->screen
->info
.htile_cmask_support_1d_tiling
)
456 /* Use a slow clear for small surfaces where the cost of
457 * the eliminate pass can be higher than the benefit of fast
458 * clear. The closed driver does this, but the numbers may differ.
460 * This helps on both dGPUs and APUs, even small APUs like Mullins.
462 bool too_small
= tex
->buffer
.b
.b
.nr_samples
<= 1 &&
463 tex
->buffer
.b
.b
.width0
*
464 tex
->buffer
.b
.b
.height0
<= 512 * 512;
465 bool eliminate_needed
= false;
466 bool fmask_decompress_needed
= false;
468 /* Fast clear is the most appropriate place to enable DCC for
469 * displayable surfaces.
471 if (sctx
->family
== CHIP_STONEY
&& !too_small
) {
472 vi_separate_dcc_try_enable(sctx
, tex
);
474 /* RB+ isn't supported with a CMASK clear only on Stoney,
475 * so all clears are considered to be hypothetically slow
476 * clears, which is weighed when determining whether to
477 * enable separate DCC.
479 if (tex
->dcc_gather_statistics
) /* only for Stoney */
480 tex
->num_slow_clears
++;
483 /* Try to clear DCC first, otherwise try CMASK. */
484 if (vi_dcc_enabled(tex
, 0)) {
485 uint32_t reset_value
;
487 if (sctx
->screen
->debug_flags
& DBG(NO_DCC_CLEAR
))
490 if (!vi_get_fast_clear_parameters(sctx
->screen
,
491 tex
->buffer
.b
.b
.format
,
492 fb
->cbufs
[i
]->format
,
497 if (eliminate_needed
&& too_small
)
500 /* TODO: This DCC+CMASK clear doesn't work with MSAA. */
501 if (tex
->buffer
.b
.b
.nr_samples
>= 2 && tex
->cmask_buffer
&&
505 if (!vi_dcc_clear_level(sctx
, tex
, 0, reset_value
))
508 tex
->separate_dcc_dirty
= true;
509 tex
->displayable_dcc_dirty
= true;
511 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
512 if (tex
->buffer
.b
.b
.nr_samples
>= 2 && tex
->cmask_buffer
) {
513 uint32_t clear_value
= 0xCCCCCCCC;
514 si_clear_buffer(sctx
, &tex
->cmask_buffer
->b
.b
,
515 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
516 &clear_value
, 4, SI_COHERENCY_CB_META
, false);
517 fmask_decompress_needed
= true;
523 /* 128-bit formats are unusupported */
524 if (tex
->surface
.bpe
> 8) {
528 /* RB+ doesn't work with CMASK fast clear on Stoney. */
529 if (sctx
->family
== CHIP_STONEY
)
532 /* ensure CMASK is enabled */
533 si_alloc_separate_cmask(sctx
->screen
, tex
);
534 if (!tex
->cmask_buffer
)
537 /* Do the fast clear. */
538 uint32_t clear_value
= 0;
539 si_clear_buffer(sctx
, &tex
->cmask_buffer
->b
.b
,
540 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
541 &clear_value
, 4, SI_COHERENCY_CB_META
, false);
542 eliminate_needed
= true;
545 if ((eliminate_needed
|| fmask_decompress_needed
) &&
546 !(tex
->dirty_level_mask
& (1 << level
))) {
547 tex
->dirty_level_mask
|= 1 << level
;
548 p_atomic_inc(&sctx
->screen
->compressed_colortex_counter
);
551 /* We can change the micro tile mode before a full clear. */
552 si_set_optimal_micro_tile_mode(sctx
->screen
, tex
);
554 *buffers
&= ~clear_bit
;
556 /* Chips with DCC constant encoding don't need to set the clear
557 * color registers for DCC clear values 0 and 1.
559 if (sctx
->screen
->info
.has_dcc_constant_encode
&& !eliminate_needed
)
562 if (si_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
)) {
563 sctx
->framebuffer
.dirty_cbufs
|= 1 << i
;
564 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
569 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
570 const union pipe_color_union
*color
,
571 double depth
, unsigned stencil
)
573 struct si_context
*sctx
= (struct si_context
*)ctx
;
574 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
575 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
576 struct si_texture
*zstex
=
577 zsbuf
? (struct si_texture
*)zsbuf
->texture
: NULL
;
578 bool needs_db_flush
= false;
580 if (buffers
& PIPE_CLEAR_COLOR
) {
581 si_do_fast_color_clear(sctx
, &buffers
, color
);
583 return; /* all buffers have been fast cleared */
585 /* These buffers cannot use fast clear, make sure to disable expansion. */
586 for (unsigned i
= 0; i
< fb
->nr_cbufs
; i
++) {
587 struct si_texture
*tex
;
589 /* If not clearing this buffer, skip. */
590 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)) || !fb
->cbufs
[i
])
593 tex
= (struct si_texture
*)fb
->cbufs
[i
]->texture
;
594 if (tex
->surface
.fmask_size
== 0)
595 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
600 zsbuf
->u
.tex
.first_layer
== 0 &&
601 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->buffer
.b
.b
, 0)) {
602 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
603 if (buffers
& PIPE_CLEAR_DEPTH
&&
604 si_htile_enabled(zstex
, zsbuf
->u
.tex
.level
, PIPE_MASK_Z
) &&
605 (!zstex
->tc_compatible_htile
||
606 depth
== 0 || depth
== 1)) {
607 /* Need to disable EXPCLEAR temporarily if clearing
609 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
610 sctx
->db_depth_disable_expclear
= true;
613 if (zstex
->depth_clear_value
!= (float)depth
) {
614 if ((zstex
->depth_clear_value
!= 0) != (depth
!= 0)) {
615 /* ZRANGE_PRECISION register of a bound surface will change so we
616 * must flush the DB caches. */
617 needs_db_flush
= true;
619 /* Update DB_DEPTH_CLEAR. */
620 zstex
->depth_clear_value
= depth
;
621 sctx
->framebuffer
.dirty_zsbuf
= true;
622 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
624 sctx
->db_depth_clear
= true;
625 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
628 /* TC-compatible HTILE only supports stencil clears to 0. */
629 if (buffers
& PIPE_CLEAR_STENCIL
&&
630 si_htile_enabled(zstex
, zsbuf
->u
.tex
.level
, PIPE_MASK_S
) &&
631 (!zstex
->tc_compatible_htile
|| stencil
== 0)) {
634 /* Need to disable EXPCLEAR temporarily if clearing
636 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
637 sctx
->db_stencil_disable_expclear
= true;
640 if (zstex
->stencil_clear_value
!= (uint8_t)stencil
) {
641 /* Update DB_STENCIL_CLEAR. */
642 zstex
->stencil_clear_value
= stencil
;
643 sctx
->framebuffer
.dirty_zsbuf
= true;
644 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
646 sctx
->db_stencil_clear
= true;
647 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
651 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
;
654 si_blitter_begin(sctx
, SI_CLEAR
);
655 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
656 util_framebuffer_get_num_layers(fb
),
657 buffers
, color
, depth
, stencil
,
658 sctx
->framebuffer
.nr_samples
> 1);
659 si_blitter_end(sctx
);
661 if (sctx
->db_depth_clear
) {
662 sctx
->db_depth_clear
= false;
663 sctx
->db_depth_disable_expclear
= false;
664 zstex
->depth_cleared
= true;
665 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
668 if (sctx
->db_stencil_clear
) {
669 sctx
->db_stencil_clear
= false;
670 sctx
->db_stencil_disable_expclear
= false;
671 zstex
->stencil_cleared
= true;
672 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
676 static void si_clear_render_target(struct pipe_context
*ctx
,
677 struct pipe_surface
*dst
,
678 const union pipe_color_union
*color
,
679 unsigned dstx
, unsigned dsty
,
680 unsigned width
, unsigned height
,
681 bool render_condition_enabled
)
683 struct si_context
*sctx
= (struct si_context
*)ctx
;
684 struct si_texture
*sdst
= (struct si_texture
*)dst
->texture
;
686 if (dst
->texture
->nr_samples
<= 1 && !sdst
->surface
.dcc_offset
) {
687 si_compute_clear_render_target(ctx
, dst
, color
, dstx
, dsty
, width
,
688 height
, render_condition_enabled
);
692 si_blitter_begin(sctx
, SI_CLEAR_SURFACE
|
693 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
694 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
695 dstx
, dsty
, width
, height
);
696 si_blitter_end(sctx
);
699 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
700 struct pipe_surface
*dst
,
701 unsigned clear_flags
,
704 unsigned dstx
, unsigned dsty
,
705 unsigned width
, unsigned height
,
706 bool render_condition_enabled
)
708 struct si_context
*sctx
= (struct si_context
*)ctx
;
710 si_blitter_begin(sctx
, SI_CLEAR_SURFACE
|
711 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
712 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
713 dstx
, dsty
, width
, height
);
714 si_blitter_end(sctx
);
717 static void si_clear_texture(struct pipe_context
*pipe
,
718 struct pipe_resource
*tex
,
720 const struct pipe_box
*box
,
723 struct pipe_screen
*screen
= pipe
->screen
;
724 struct si_texture
*stex
= (struct si_texture
*)tex
;
725 struct pipe_surface tmpl
= {{0}};
726 struct pipe_surface
*sf
;
728 tmpl
.format
= tex
->format
;
729 tmpl
.u
.tex
.first_layer
= box
->z
;
730 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
731 tmpl
.u
.tex
.level
= level
;
732 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
736 if (stex
->is_depth
) {
741 /* Depth is always present. */
742 clear
= PIPE_CLEAR_DEPTH
;
743 util_format_unpack_z_float(tex
->format
, &depth
, data
, 1);
745 if (stex
->surface
.has_stencil
) {
746 clear
|= PIPE_CLEAR_STENCIL
;
747 util_format_unpack_s_8uint(tex
->format
,
751 si_clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
753 box
->width
, box
->height
, false);
755 union pipe_color_union color
;
757 util_format_unpack_rgba(tex
->format
, color
.ui
, data
, 1);
759 if (screen
->is_format_supported(screen
, tex
->format
,
761 PIPE_BIND_RENDER_TARGET
)) {
762 si_clear_render_target(pipe
, sf
, &color
,
764 box
->width
, box
->height
, false);
766 /* Software fallback - just for R9G9B9E5_FLOAT */
767 util_clear_render_target(pipe
, sf
, &color
,
769 box
->width
, box
->height
);
772 pipe_surface_reference(&sf
, NULL
);
775 void si_init_clear_functions(struct si_context
*sctx
)
777 sctx
->b
.clear_render_target
= si_clear_render_target
;
778 sctx
->b
.clear_texture
= si_clear_texture
;
780 if (sctx
->has_graphics
) {
781 sctx
->b
.clear
= si_clear
;
782 sctx
->b
.clear_depth_stencil
= si_clear_depth_stencil
;