src/gallium/drivers/radeonsi/si_commands.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "sid.h"
  28 #include "si_pipe.h"
  29 #include "si_pm4.h"
  30
  31 void si_cmd_context_control(struct si_pm4_state *pm4)
  32 {
  33         si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
  34         si_pm4_cmd_add(pm4, 0x80000000);
  35         si_pm4_cmd_add(pm4, 0x80000000);
  36         si_pm4_cmd_end(pm4, false);
  37 }
  38
  39 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
  40                          uint64_t index_base, uint32_t index_count,
  41                          uint32_t initiator, bool predicate)
  42 {
  43         si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_2);
  44         si_pm4_cmd_add(pm4, max_size);
  45         si_pm4_cmd_add(pm4, index_base);
  46         si_pm4_cmd_add(pm4, (index_base >> 32UL) & 0xFF);
  47         si_pm4_cmd_add(pm4, index_count);
  48         si_pm4_cmd_add(pm4, initiator);
  49         si_pm4_cmd_end(pm4, predicate);
  50 }
  51
  52 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
  53                             uint32_t initiator, bool predicate)
  54 {
  55         si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_AUTO);
  56         si_pm4_cmd_add(pm4, count);
  57         si_pm4_cmd_add(pm4, initiator);
  58         si_pm4_cmd_end(pm4, predicate);
  59 }
  60
  61 void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
  62 {
  63         if (pm4->chip_class >= CIK) {
  64                 si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
  65                 si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
  66                 si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
  67                 si_pm4_cmd_add(pm4, 0xff);              /* CP_COHER_SIZE_HI */
  68                 si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
  69                 si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE_HI */
  70                 si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
  71                 si_pm4_cmd_end(pm4, false);
  72         } else {
  73                 si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
  74                 si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
  75                 si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
  76                 si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
  77                 si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
  78                 si_pm4_cmd_end(pm4, false);
  79         }
  80 }