2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
26 #include "radeon/r600_pipe_common.h"
27 #include "radeon/radeon_elf_util.h"
28 #include "radeon/radeon_llvm_util.h"
30 #include "radeon/r600_cs.h"
32 #include "si_shader.h"
35 #define MAX_GLOBAL_BUFFERS 20
38 struct si_context
*ctx
;
41 unsigned private_size
;
43 struct si_shader shader
;
44 unsigned num_user_sgprs
;
46 struct r600_resource
*input_buffer
;
47 struct pipe_resource
*global_buffers
[MAX_GLOBAL_BUFFERS
];
49 #if HAVE_LLVM < 0x0306
51 struct si_shader
*kernels
;
52 LLVMContextRef llvm_ctx
;
56 static void init_scratch_buffer(struct si_context
*sctx
, struct si_compute
*program
)
58 unsigned scratch_bytes
= 0;
59 uint64_t scratch_buffer_va
;
62 /* Compute the scratch buffer size using the maximum number of waves.
63 * This way we don't need to recompute it for each kernel launch. */
64 unsigned scratch_waves
= 32 * sctx
->screen
->b
.info
.max_compute_units
;
65 for (i
= 0; i
< program
->shader
.binary
.global_symbol_count
; i
++) {
67 program
->shader
.binary
.global_symbol_offsets
[i
];
68 unsigned scratch_bytes_needed
;
70 si_shader_binary_read_config(&program
->shader
, offset
);
71 scratch_bytes_needed
= program
->shader
.scratch_bytes_per_wave
;
72 scratch_bytes
= MAX2(scratch_bytes
, scratch_bytes_needed
);
75 if (scratch_bytes
== 0)
78 program
->shader
.scratch_bo
=
79 si_resource_create_custom(sctx
->b
.b
.screen
,
81 scratch_bytes
* scratch_waves
);
83 scratch_buffer_va
= program
->shader
.scratch_bo
->gpu_address
;
85 /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
86 * to the maximum bytes needed, so it can compute the stride
89 program
->shader
.scratch_bytes_per_wave
= scratch_bytes
;
91 /* Patch the shader with the scratch buffer address. */
92 si_shader_apply_scratch_relocs(sctx
,
93 &program
->shader
, scratch_buffer_va
);
96 static void *si_create_compute_state(
97 struct pipe_context
*ctx
,
98 const struct pipe_compute_state
*cso
)
100 struct si_context
*sctx
= (struct si_context
*)ctx
;
101 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
102 const struct pipe_llvm_program_header
*header
;
106 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
109 program
->local_size
= cso
->req_local_mem
;
110 program
->private_size
= cso
->req_private_mem
;
111 program
->input_size
= cso
->req_input_mem
;
113 #if HAVE_LLVM < 0x0306
116 program
->llvm_ctx
= LLVMContextCreate();
117 program
->num_kernels
= radeon_llvm_get_num_kernels(program
->llvm_ctx
,
118 code
, header
->num_bytes
);
119 program
->kernels
= CALLOC(sizeof(struct si_shader
),
120 program
->num_kernels
);
121 for (i
= 0; i
< program
->num_kernels
; i
++) {
122 LLVMModuleRef mod
= radeon_llvm_get_kernel_module(program
->llvm_ctx
, i
,
123 code
, header
->num_bytes
);
124 si_compile_llvm(sctx
->screen
, &program
->kernels
[i
], sctx
->tm
,
125 mod
, &sctx
->b
.debug
, TGSI_PROCESSOR_COMPUTE
);
126 LLVMDisposeModule(mod
);
131 radeon_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
133 /* init_scratch_buffer patches the shader code with the scratch address,
134 * so we need to call it before si_shader_binary_read() which uploads
135 * the shader code to the GPU.
137 init_scratch_buffer(sctx
, program
);
138 si_shader_binary_read(sctx
->screen
, &program
->shader
, &sctx
->b
.debug
,
139 TGSI_PROCESSOR_COMPUTE
);
140 si_shader_binary_upload(sctx
->screen
, &program
->shader
);
143 program
->input_buffer
= si_resource_create_custom(sctx
->b
.b
.screen
,
144 PIPE_USAGE_IMMUTABLE
, program
->input_size
);
149 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
151 struct si_context
*sctx
= (struct si_context
*)ctx
;
152 sctx
->cs_shader_state
.program
= (struct si_compute
*)state
;
155 static void si_set_global_binding(
156 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
157 struct pipe_resource
**resources
,
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
165 for (i
= first
; i
< first
+ n
; i
++) {
166 pipe_resource_reference(&program
->global_buffers
[i
], NULL
);
171 for (i
= first
; i
< first
+ n
; i
++) {
174 pipe_resource_reference(&program
->global_buffers
[i
], resources
[i
]);
175 va
= r600_resource(resources
[i
])->gpu_address
;
176 offset
= util_le32_to_cpu(*handles
[i
]);
178 va
= util_cpu_to_le64(va
);
179 memcpy(handles
[i
], &va
, sizeof(va
));
184 * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
185 * /p block_layout is the number of threads in each work group.
186 * /p grid layout is the number of work groups.
188 static unsigned compute_num_waves_for_scratch(
189 const struct radeon_info
*info
,
190 const uint
*block_layout
,
191 const uint
*grid_layout
)
193 unsigned num_sh
= MAX2(info
->max_sh_per_se
, 1);
194 unsigned num_se
= MAX2(info
->max_se
, 1);
195 unsigned num_blocks
= 1;
196 unsigned threads_per_block
= 1;
197 unsigned waves_per_block
;
198 unsigned waves_per_sh
;
200 unsigned scratch_waves
;
203 for (i
= 0; i
< 3; i
++) {
204 threads_per_block
*= block_layout
[i
];
205 num_blocks
*= grid_layout
[i
];
208 waves_per_block
= align(threads_per_block
, 64) / 64;
209 waves
= waves_per_block
* num_blocks
;
210 waves_per_sh
= align(waves
, num_sh
* num_se
) / (num_sh
* num_se
);
211 scratch_waves
= waves_per_sh
* num_sh
* num_se
;
213 if (waves_per_block
> waves_per_sh
) {
214 scratch_waves
= waves_per_block
* num_sh
* num_se
;
217 return scratch_waves
;
220 static void si_launch_grid(
221 struct pipe_context
*ctx
,
222 const uint
*block_layout
, const uint
*grid_layout
,
223 uint32_t pc
, const void *input
)
225 struct si_context
*sctx
= (struct si_context
*)ctx
;
226 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
227 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
228 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
229 struct r600_resource
*input_buffer
= program
->input_buffer
;
230 unsigned kernel_args_size
;
231 unsigned num_work_size_bytes
= 36;
232 uint32_t kernel_args_offset
= 0;
233 uint32_t *kernel_args
;
234 uint64_t kernel_args_va
;
235 uint64_t scratch_buffer_va
= 0;
238 struct si_shader
*shader
= &program
->shader
;
240 unsigned num_waves_for_scratch
;
242 #if HAVE_LLVM < 0x0306
243 shader
= &program
->kernels
[pc
];
247 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0) | PKT3_SHADER_TYPE_S(1));
248 radeon_emit(cs
, 0x80000000);
249 radeon_emit(cs
, 0x80000000);
251 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
252 SI_CONTEXT_INV_GLOBAL_L2
|
253 SI_CONTEXT_INV_ICACHE
|
254 SI_CONTEXT_INV_SMEM_L1
|
255 SI_CONTEXT_FLUSH_WITH_INV_L2
|
256 SI_CONTEXT_FLAG_COMPUTE
;
257 si_emit_cache_flush(sctx
, NULL
);
259 pm4
->compute_pkt
= true;
261 #if HAVE_LLVM >= 0x0306
262 /* Read the config information */
263 si_shader_binary_read_config(shader
, pc
);
266 /* Upload the kernel arguments */
268 /* The extra num_work_size_bytes are for work group / work item size information */
269 kernel_args_size
= program
->input_size
+ num_work_size_bytes
+ 8 /* For scratch va */;
271 kernel_args
= sctx
->b
.ws
->buffer_map(input_buffer
->buf
,
272 sctx
->b
.gfx
.cs
, PIPE_TRANSFER_WRITE
);
273 for (i
= 0; i
< 3; i
++) {
274 kernel_args
[i
] = grid_layout
[i
];
275 kernel_args
[i
+ 3] = grid_layout
[i
] * block_layout
[i
];
276 kernel_args
[i
+ 6] = block_layout
[i
];
279 num_waves_for_scratch
= compute_num_waves_for_scratch(
280 &sctx
->screen
->b
.info
, block_layout
, grid_layout
);
282 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), input
, program
->input_size
);
284 if (shader
->scratch_bytes_per_wave
> 0) {
286 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
287 "Total Scratch: %u bytes\n", num_waves_for_scratch
,
288 shader
->scratch_bytes_per_wave
,
289 shader
->scratch_bytes_per_wave
*
290 num_waves_for_scratch
);
292 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
294 RADEON_USAGE_READWRITE
,
295 RADEON_PRIO_SCRATCH_BUFFER
);
297 scratch_buffer_va
= shader
->scratch_bo
->gpu_address
;
300 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
301 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
305 kernel_args_va
= input_buffer
->gpu_address
;
306 kernel_args_va
+= kernel_args_offset
;
308 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, input_buffer
,
309 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
311 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
, kernel_args_va
);
312 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) | S_008F04_STRIDE(0));
313 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 8, scratch_buffer_va
);
314 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 12,
315 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va
>> 32)
316 | S_008F04_STRIDE(shader
->scratch_bytes_per_wave
/ 64));
318 si_pm4_set_reg(pm4
, R_00B810_COMPUTE_START_X
, 0);
319 si_pm4_set_reg(pm4
, R_00B814_COMPUTE_START_Y
, 0);
320 si_pm4_set_reg(pm4
, R_00B818_COMPUTE_START_Z
, 0);
322 si_pm4_set_reg(pm4
, R_00B81C_COMPUTE_NUM_THREAD_X
,
323 S_00B81C_NUM_THREAD_FULL(block_layout
[0]));
324 si_pm4_set_reg(pm4
, R_00B820_COMPUTE_NUM_THREAD_Y
,
325 S_00B820_NUM_THREAD_FULL(block_layout
[1]));
326 si_pm4_set_reg(pm4
, R_00B824_COMPUTE_NUM_THREAD_Z
,
327 S_00B824_NUM_THREAD_FULL(block_layout
[2]));
330 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
331 struct r600_resource
*buffer
=
332 (struct r600_resource
*)program
->global_buffers
[i
];
336 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, buffer
,
337 RADEON_USAGE_READWRITE
,
338 RADEON_PRIO_COMPUTE_GLOBAL
);
341 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
342 * and is now per pipe, so it should be handled in the
343 * kernel if we want to use something other than the default value,
344 * which is now 0x22f.
346 if (sctx
->b
.chip_class
<= SI
) {
347 /* XXX: This should be:
348 * (number of compute units) * 4 * (waves per simd) - 1 */
350 si_pm4_set_reg(pm4
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
351 0x190 /* Default value */);
354 shader_va
= shader
->bo
->gpu_address
;
356 #if HAVE_LLVM >= 0x0306
359 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, shader
->bo
,
360 RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
361 si_pm4_set_reg(pm4
, R_00B830_COMPUTE_PGM_LO
, shader_va
>> 8);
362 si_pm4_set_reg(pm4
, R_00B834_COMPUTE_PGM_HI
, shader_va
>> 40);
364 si_pm4_set_reg(pm4
, R_00B848_COMPUTE_PGM_RSRC1
, shader
->rsrc1
);
366 lds_blocks
= shader
->lds_size
;
367 /* XXX: We are over allocating LDS. For SI, the shader reports LDS in
368 * blocks of 256 bytes, so if there are 4 bytes lds allocated in
369 * the shader and 4 bytes allocated by the state tracker, then
370 * we will set LDS_SIZE to 512 bytes rather than 256.
372 if (sctx
->b
.chip_class
<= SI
) {
373 lds_blocks
+= align(program
->local_size
, 256) >> 8;
375 lds_blocks
+= align(program
->local_size
, 512) >> 9;
378 assert(lds_blocks
<= 0xFF);
380 shader
->rsrc2
&= C_00B84C_LDS_SIZE
;
381 shader
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
383 si_pm4_set_reg(pm4
, R_00B84C_COMPUTE_PGM_RSRC2
, shader
->rsrc2
);
384 si_pm4_set_reg(pm4
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 0);
386 si_pm4_set_reg(pm4
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
,
387 S_00B858_SH0_CU_EN(0xffff /* Default value */)
388 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
391 si_pm4_set_reg(pm4
, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1
,
392 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
393 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
396 num_waves_for_scratch
=
397 MIN2(num_waves_for_scratch
,
398 32 * sctx
->screen
->b
.info
.max_compute_units
);
399 si_pm4_set_reg(pm4
, R_00B860_COMPUTE_TMPRING_SIZE
,
400 /* The maximum value for WAVES is 32 * num CU.
401 * If you program this value incorrectly, the GPU will hang if
402 * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
404 S_00B860_WAVES(num_waves_for_scratch
)
405 | S_00B860_WAVESIZE(shader
->scratch_bytes_per_wave
>> 10))
408 si_pm4_cmd_begin(pm4
, PKT3_DISPATCH_DIRECT
);
409 si_pm4_cmd_add(pm4
, grid_layout
[0]); /* Thread groups DIM_X */
410 si_pm4_cmd_add(pm4
, grid_layout
[1]); /* Thread groups DIM_Y */
411 si_pm4_cmd_add(pm4
, grid_layout
[2]); /* Thread gropus DIM_Z */
412 si_pm4_cmd_add(pm4
, 1); /* DISPATCH_INITIATOR */
413 si_pm4_cmd_end(pm4
, false);
415 si_pm4_emit(sctx
, pm4
);
418 fprintf(stderr
, "cdw: %i\n", sctx
->cs
->cdw
);
419 for (i
= 0; i
< sctx
->cs
->cdw
; i
++) {
420 fprintf(stderr
, "%4i : 0x%08X\n", i
, sctx
->cs
->buf
[i
]);
424 si_pm4_free_state(sctx
, pm4
, ~0);
426 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
|
427 SI_CONTEXT_INV_VMEM_L1
|
428 SI_CONTEXT_INV_GLOBAL_L2
|
429 SI_CONTEXT_INV_ICACHE
|
430 SI_CONTEXT_INV_SMEM_L1
|
431 SI_CONTEXT_FLAG_COMPUTE
;
432 si_emit_cache_flush(sctx
, NULL
);
436 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
437 struct si_compute
*program
= (struct si_compute
*)state
;
443 #if HAVE_LLVM < 0x0306
444 if (program
->kernels
) {
445 for (int i
= 0; i
< program
->num_kernels
; i
++){
446 if (program
->kernels
[i
].bo
){
447 si_shader_destroy(&program
->kernels
[i
]);
450 FREE(program
->kernels
);
453 if (program
->llvm_ctx
){
454 LLVMContextDispose(program
->llvm_ctx
);
457 FREE(program
->shader
.binary
.config
);
458 FREE(program
->shader
.binary
.rodata
);
459 FREE(program
->shader
.binary
.global_symbol_offsets
);
460 si_shader_destroy(&program
->shader
);
463 pipe_resource_reference(
464 (struct pipe_resource
**)&program
->input_buffer
, NULL
);
469 static void si_set_compute_resources(struct pipe_context
* ctx_
,
470 unsigned start
, unsigned count
,
471 struct pipe_surface
** surfaces
) { }
473 void si_init_compute_functions(struct si_context
*sctx
)
475 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
476 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
477 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
478 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
479 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
480 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
481 sctx
->b
.b
.launch_grid
= si_launch_grid
;