2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
31 #include "amd_kernel_code_t.h"
32 #include "si_build_pm4.h"
33 #include "si_compute.h"
35 #define COMPUTE_DBG(sscreen, fmt, args...) \
37 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
40 struct dispatch_packet
{
43 uint16_t workgroup_size_x
;
44 uint16_t workgroup_size_y
;
45 uint16_t workgroup_size_z
;
50 uint32_t private_segment_size
;
51 uint32_t group_segment_size
;
52 uint64_t kernel_object
;
53 uint64_t kernarg_address
;
57 static const amd_kernel_code_t
*si_compute_get_code_object(
58 const struct si_compute
*program
,
59 uint64_t symbol_offset
)
61 if (!program
->use_code_object_v2
) {
64 return (const amd_kernel_code_t
*)
65 (program
->shader
.binary
.code
+ symbol_offset
);
68 static void code_object_to_config(const amd_kernel_code_t
*code_object
,
69 struct si_shader_config
*out_config
) {
71 uint32_t rsrc1
= code_object
->compute_pgm_resource_registers
;
72 uint32_t rsrc2
= code_object
->compute_pgm_resource_registers
>> 32;
73 out_config
->num_sgprs
= code_object
->wavefront_sgpr_count
;
74 out_config
->num_vgprs
= code_object
->workitem_vgpr_count
;
75 out_config
->float_mode
= G_00B028_FLOAT_MODE(rsrc1
);
76 out_config
->rsrc1
= rsrc1
;
77 out_config
->lds_size
= MAX2(out_config
->lds_size
, G_00B84C_LDS_SIZE(rsrc2
));
78 out_config
->rsrc2
= rsrc2
;
79 out_config
->scratch_bytes_per_wave
=
80 align(code_object
->workitem_private_segment_byte_size
* 64, 1024);
83 /* Asynchronous compute shader compilation. */
84 static void si_create_compute_state_async(void *job
, int thread_index
)
86 struct si_compute
*program
= (struct si_compute
*)job
;
87 struct si_shader
*shader
= &program
->shader
;
88 struct si_shader_selector sel
;
89 struct ac_llvm_compiler
*compiler
;
90 struct pipe_debug_callback
*debug
= &program
->compiler_ctx_state
.debug
;
91 struct si_screen
*sscreen
= program
->screen
;
93 assert(!debug
->debug_message
|| debug
->async
);
94 assert(thread_index
>= 0);
95 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
96 compiler
= &sscreen
->compiler
[thread_index
];
98 memset(&sel
, 0, sizeof(sel
));
100 sel
.screen
= sscreen
;
102 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
) {
103 tgsi_scan_shader(program
->ir
.tgsi
, &sel
.info
);
104 sel
.tokens
= program
->ir
.tgsi
;
106 assert(program
->ir_type
== PIPE_SHADER_IR_NIR
);
107 sel
.nir
= program
->ir
.nir
;
109 si_nir_opts(sel
.nir
);
110 si_nir_scan_shader(sel
.nir
, &sel
.info
);
114 /* Store the declared LDS size into tgsi_shader_info for the shader
115 * cache to include it.
117 sel
.info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
] = program
->local_size
;
119 sel
.type
= PIPE_SHADER_COMPUTE
;
120 si_get_active_slot_masks(&sel
.info
,
121 &program
->active_const_and_shader_buffers
,
122 &program
->active_samplers_and_images
);
124 program
->shader
.selector
= &sel
;
125 program
->shader
.is_monolithic
= true;
126 program
->uses_grid_size
= sel
.info
.uses_grid_size
;
127 program
->uses_bindless_samplers
= sel
.info
.uses_bindless_samplers
;
128 program
->uses_bindless_images
= sel
.info
.uses_bindless_images
;
129 program
->reads_variable_block_size
=
130 sel
.info
.uses_block_size
&&
131 sel
.info
.properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0;
132 program
->num_cs_user_data_dwords
=
133 sel
.info
.properties
[TGSI_PROPERTY_CS_USER_DATA_DWORDS
];
135 void *ir_binary
= si_get_ir_binary(&sel
);
137 /* Try to load the shader from the shader cache. */
138 mtx_lock(&sscreen
->shader_cache_mutex
);
141 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
142 mtx_unlock(&sscreen
->shader_cache_mutex
);
144 si_shader_dump_stats_for_shader_db(shader
, debug
);
145 si_shader_dump(sscreen
, shader
, debug
, PIPE_SHADER_COMPUTE
,
148 if (si_shader_binary_upload(sscreen
, shader
))
149 program
->shader
.compilation_failed
= true;
151 mtx_unlock(&sscreen
->shader_cache_mutex
);
153 if (si_shader_create(sscreen
, compiler
, &program
->shader
, debug
)) {
154 program
->shader
.compilation_failed
= true;
156 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
157 FREE(program
->ir
.tgsi
);
158 program
->shader
.selector
= NULL
;
162 bool scratch_enabled
= shader
->config
.scratch_bytes_per_wave
> 0;
163 unsigned user_sgprs
= SI_NUM_RESOURCE_SGPRS
+
164 (sel
.info
.uses_grid_size
? 3 : 0) +
165 (program
->reads_variable_block_size
? 3 : 0) +
166 program
->num_cs_user_data_dwords
;
168 shader
->config
.rsrc1
=
169 S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
170 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
171 S_00B848_DX10_CLAMP(1) |
172 S_00B848_FLOAT_MODE(shader
->config
.float_mode
);
174 shader
->config
.rsrc2
=
175 S_00B84C_USER_SGPR(user_sgprs
) |
176 S_00B84C_SCRATCH_EN(scratch_enabled
) |
177 S_00B84C_TGID_X_EN(sel
.info
.uses_block_id
[0]) |
178 S_00B84C_TGID_Y_EN(sel
.info
.uses_block_id
[1]) |
179 S_00B84C_TGID_Z_EN(sel
.info
.uses_block_id
[2]) |
180 S_00B84C_TIDIG_COMP_CNT(sel
.info
.uses_thread_id
[2] ? 2 :
181 sel
.info
.uses_thread_id
[1] ? 1 : 0) |
182 S_00B84C_LDS_SIZE(shader
->config
.lds_size
);
185 mtx_lock(&sscreen
->shader_cache_mutex
);
186 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
188 mtx_unlock(&sscreen
->shader_cache_mutex
);
192 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
193 FREE(program
->ir
.tgsi
);
195 program
->shader
.selector
= NULL
;
198 static void *si_create_compute_state(
199 struct pipe_context
*ctx
,
200 const struct pipe_compute_state
*cso
)
202 struct si_context
*sctx
= (struct si_context
*)ctx
;
203 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
204 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
206 pipe_reference_init(&program
->reference
, 1);
207 program
->screen
= (struct si_screen
*)ctx
->screen
;
208 program
->ir_type
= cso
->ir_type
;
209 program
->local_size
= cso
->req_local_mem
;
210 program
->private_size
= cso
->req_private_mem
;
211 program
->input_size
= cso
->req_input_mem
;
212 program
->use_code_object_v2
= cso
->ir_type
== PIPE_SHADER_IR_NATIVE
;
214 if (cso
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
215 if (cso
->ir_type
== PIPE_SHADER_IR_TGSI
) {
216 program
->ir
.tgsi
= tgsi_dup_tokens(cso
->prog
);
217 if (!program
->ir
.tgsi
) {
222 assert(cso
->ir_type
== PIPE_SHADER_IR_NIR
);
223 program
->ir
.nir
= (struct nir_shader
*) cso
->prog
;
226 program
->compiler_ctx_state
.debug
= sctx
->debug
;
227 program
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
228 p_atomic_inc(&sscreen
->num_shaders_created
);
230 si_schedule_initial_compile(sctx
, PIPE_SHADER_COMPUTE
,
232 &program
->compiler_ctx_state
,
233 program
, si_create_compute_state_async
);
235 const struct pipe_llvm_program_header
*header
;
238 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
240 ac_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
241 if (program
->use_code_object_v2
) {
242 const amd_kernel_code_t
*code_object
=
243 si_compute_get_code_object(program
, 0);
244 code_object_to_config(code_object
, &program
->shader
.config
);
245 if (program
->shader
.binary
.reloc_count
!= 0) {
246 fprintf(stderr
, "Error: %d unsupported relocations\n",
247 program
->shader
.binary
.reloc_count
);
252 si_shader_binary_read_config(&program
->shader
.binary
,
253 &program
->shader
.config
, 0);
255 si_shader_dump(sctx
->screen
, &program
->shader
, &sctx
->debug
,
256 PIPE_SHADER_COMPUTE
, stderr
, true);
257 if (si_shader_binary_upload(sctx
->screen
, &program
->shader
) < 0) {
258 fprintf(stderr
, "LLVM failed to upload shader\n");
267 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
269 struct si_context
*sctx
= (struct si_context
*)ctx
;
270 struct si_compute
*program
= (struct si_compute
*)state
;
272 sctx
->cs_shader_state
.program
= program
;
276 /* Wait because we need active slot usage masks. */
277 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
)
278 util_queue_fence_wait(&program
->ready
);
280 si_set_active_descriptors(sctx
,
281 SI_DESCS_FIRST_COMPUTE
+
282 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
283 program
->active_const_and_shader_buffers
);
284 si_set_active_descriptors(sctx
,
285 SI_DESCS_FIRST_COMPUTE
+
286 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
287 program
->active_samplers_and_images
);
290 static void si_set_global_binding(
291 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
292 struct pipe_resource
**resources
,
296 struct si_context
*sctx
= (struct si_context
*)ctx
;
297 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
299 assert(first
+ n
<= MAX_GLOBAL_BUFFERS
);
302 for (i
= 0; i
< n
; i
++) {
303 pipe_resource_reference(&program
->global_buffers
[first
+ i
], NULL
);
308 for (i
= 0; i
< n
; i
++) {
311 pipe_resource_reference(&program
->global_buffers
[first
+ i
], resources
[i
]);
312 va
= si_resource(resources
[i
])->gpu_address
;
313 offset
= util_le32_to_cpu(*handles
[i
]);
315 va
= util_cpu_to_le64(va
);
316 memcpy(handles
[i
], &va
, sizeof(va
));
320 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
)
324 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
325 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
326 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
327 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
329 if (sctx
->chip_class
>= GFX7
) {
330 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
331 radeon_set_sh_reg_seq(cs
,
332 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
333 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
334 S_00B864_SH1_CU_EN(0xffff));
335 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
336 S_00B868_SH1_CU_EN(0xffff));
339 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
340 * and is now per pipe, so it should be handled in the
341 * kernel if we want to use something other than the default value,
342 * which is now 0x22f.
344 if (sctx
->chip_class
<= GFX6
) {
345 /* XXX: This should be:
346 * (number of compute units) * 4 * (waves per simd) - 1 */
348 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
349 0x190 /* Default value */);
352 /* Set the pointer to border colors. */
353 bc_va
= sctx
->border_color_buffer
->gpu_address
;
355 if (sctx
->chip_class
>= GFX7
) {
356 radeon_set_uconfig_reg_seq(cs
, R_030E00_TA_CS_BC_BASE_ADDR
, 2);
357 radeon_emit(cs
, bc_va
>> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
358 radeon_emit(cs
, S_030E04_ADDRESS(bc_va
>> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
360 if (sctx
->screen
->info
.si_TA_CS_BC_BASE_ADDR_allowed
) {
361 radeon_set_config_reg(cs
, R_00950C_TA_CS_BC_BASE_ADDR
,
367 static bool si_setup_compute_scratch_buffer(struct si_context
*sctx
,
368 struct si_shader
*shader
,
369 struct si_shader_config
*config
)
371 uint64_t scratch_bo_size
, scratch_needed
;
373 scratch_needed
= config
->scratch_bytes_per_wave
* sctx
->scratch_waves
;
374 if (sctx
->compute_scratch_buffer
)
375 scratch_bo_size
= sctx
->compute_scratch_buffer
->b
.b
.width0
;
377 if (scratch_bo_size
< scratch_needed
) {
378 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
380 sctx
->compute_scratch_buffer
=
381 si_aligned_buffer_create(&sctx
->screen
->b
,
382 SI_RESOURCE_FLAG_UNMAPPABLE
,
384 scratch_needed
, 256);
386 if (!sctx
->compute_scratch_buffer
)
390 if (sctx
->compute_scratch_buffer
!= shader
->scratch_bo
&& scratch_needed
) {
391 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
393 si_shader_apply_scratch_relocs(shader
, scratch_va
);
395 if (si_shader_binary_upload(sctx
->screen
, shader
))
398 si_resource_reference(&shader
->scratch_bo
,
399 sctx
->compute_scratch_buffer
);
405 static bool si_switch_compute_shader(struct si_context
*sctx
,
406 struct si_compute
*program
,
407 struct si_shader
*shader
,
408 const amd_kernel_code_t
*code_object
,
411 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
412 struct si_shader_config inline_config
= {0};
413 struct si_shader_config
*config
;
416 if (sctx
->cs_shader_state
.emitted_program
== program
&&
417 sctx
->cs_shader_state
.offset
== offset
)
420 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
421 config
= &shader
->config
;
425 config
= &inline_config
;
427 code_object_to_config(code_object
, config
);
429 si_shader_binary_read_config(&shader
->binary
, config
, offset
);
432 lds_blocks
= config
->lds_size
;
433 /* XXX: We are over allocating LDS. For GFX6, the shader reports
434 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
435 * allocated in the shader and 4 bytes allocated by the state
436 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
438 if (sctx
->chip_class
<= GFX6
) {
439 lds_blocks
+= align(program
->local_size
, 256) >> 8;
441 lds_blocks
+= align(program
->local_size
, 512) >> 9;
444 /* TODO: use si_multiwave_lds_size_workaround */
445 assert(lds_blocks
<= 0xFF);
447 config
->rsrc2
&= C_00B84C_LDS_SIZE
;
448 config
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
451 if (!si_setup_compute_scratch_buffer(sctx
, shader
, config
))
454 if (shader
->scratch_bo
) {
455 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
456 "Total Scratch: %u bytes\n", sctx
->scratch_waves
,
457 config
->scratch_bytes_per_wave
,
458 config
->scratch_bytes_per_wave
*
459 sctx
->scratch_waves
);
461 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
462 shader
->scratch_bo
, RADEON_USAGE_READWRITE
,
463 RADEON_PRIO_SCRATCH_BUFFER
);
466 /* Prefetch the compute shader to TC L2.
468 * We should also prefetch graphics shaders if a compute dispatch was
469 * the last command, and the compute shader if a draw call was the last
470 * command. However, that would add more complexity and we're likely
471 * to get a shader state change in that case anyway.
473 if (sctx
->chip_class
>= GFX7
) {
474 cik_prefetch_TC_L2_async(sctx
, &program
->shader
.bo
->b
.b
,
475 0, program
->shader
.bo
->b
.b
.width0
);
478 shader_va
= shader
->bo
->gpu_address
+ offset
;
479 if (program
->use_code_object_v2
) {
480 /* Shader code is placed after the amd_kernel_code_t
482 shader_va
+= sizeof(amd_kernel_code_t
);
485 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, shader
->bo
,
486 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
488 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
489 radeon_emit(cs
, shader_va
>> 8);
490 radeon_emit(cs
, S_00B834_DATA(shader_va
>> 40));
492 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
493 radeon_emit(cs
, config
->rsrc1
);
494 radeon_emit(cs
, config
->rsrc2
);
496 COMPUTE_DBG(sctx
->screen
, "COMPUTE_PGM_RSRC1: 0x%08x "
497 "COMPUTE_PGM_RSRC2: 0x%08x\n", config
->rsrc1
, config
->rsrc2
);
499 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
500 S_00B860_WAVES(sctx
->scratch_waves
)
501 | S_00B860_WAVESIZE(config
->scratch_bytes_per_wave
>> 10));
503 sctx
->cs_shader_state
.emitted_program
= program
;
504 sctx
->cs_shader_state
.offset
= offset
;
505 sctx
->cs_shader_state
.uses_scratch
=
506 config
->scratch_bytes_per_wave
!= 0;
511 static void setup_scratch_rsrc_user_sgprs(struct si_context
*sctx
,
512 const amd_kernel_code_t
*code_object
,
515 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
516 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
518 unsigned max_private_element_size
= AMD_HSA_BITS_GET(
519 code_object
->code_properties
,
520 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
);
522 uint32_t scratch_dword0
= scratch_va
& 0xffffffff;
523 uint32_t scratch_dword1
=
524 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
525 S_008F04_SWIZZLE_ENABLE(1);
527 /* Disable address clamping */
528 uint32_t scratch_dword2
= 0xffffffff;
529 uint32_t scratch_dword3
=
530 S_008F0C_INDEX_STRIDE(3) |
531 S_008F0C_ADD_TID_ENABLE(1);
533 if (sctx
->chip_class
>= GFX9
) {
534 assert(max_private_element_size
== 1); /* always 4 bytes on GFX9 */
536 scratch_dword3
|= S_008F0C_ELEMENT_SIZE(max_private_element_size
);
538 if (sctx
->chip_class
< GFX8
) {
539 /* BUF_DATA_FORMAT is ignored, but it cannot be
540 * BUF_DATA_FORMAT_INVALID. */
542 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8
);
546 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
548 radeon_emit(cs
, scratch_dword0
);
549 radeon_emit(cs
, scratch_dword1
);
550 radeon_emit(cs
, scratch_dword2
);
551 radeon_emit(cs
, scratch_dword3
);
554 static void si_setup_user_sgprs_co_v2(struct si_context
*sctx
,
555 const amd_kernel_code_t
*code_object
,
556 const struct pipe_grid_info
*info
,
557 uint64_t kernel_args_va
)
559 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
560 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
562 static const enum amd_code_property_mask_t workgroup_count_masks
[] = {
563 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X
,
564 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y
,
565 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
568 unsigned i
, user_sgpr
= 0;
569 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
570 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
)) {
571 if (code_object
->workitem_private_segment_byte_size
> 0) {
572 setup_scratch_rsrc_user_sgprs(sctx
, code_object
,
578 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
579 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
)) {
580 struct dispatch_packet dispatch
;
581 unsigned dispatch_offset
;
582 struct si_resource
*dispatch_buf
= NULL
;
583 uint64_t dispatch_va
;
585 /* Upload dispatch ptr */
586 memset(&dispatch
, 0, sizeof(dispatch
));
588 dispatch
.workgroup_size_x
= util_cpu_to_le16(info
->block
[0]);
589 dispatch
.workgroup_size_y
= util_cpu_to_le16(info
->block
[1]);
590 dispatch
.workgroup_size_z
= util_cpu_to_le16(info
->block
[2]);
592 dispatch
.grid_size_x
= util_cpu_to_le32(info
->grid
[0] * info
->block
[0]);
593 dispatch
.grid_size_y
= util_cpu_to_le32(info
->grid
[1] * info
->block
[1]);
594 dispatch
.grid_size_z
= util_cpu_to_le32(info
->grid
[2] * info
->block
[2]);
596 dispatch
.private_segment_size
= util_cpu_to_le32(program
->private_size
);
597 dispatch
.group_segment_size
= util_cpu_to_le32(program
->local_size
);
599 dispatch
.kernarg_address
= util_cpu_to_le64(kernel_args_va
);
601 u_upload_data(sctx
->b
.const_uploader
, 0, sizeof(dispatch
),
602 256, &dispatch
, &dispatch_offset
,
603 (struct pipe_resource
**)&dispatch_buf
);
606 fprintf(stderr
, "Error: Failed to allocate dispatch "
609 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, dispatch_buf
,
610 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
612 dispatch_va
= dispatch_buf
->gpu_address
+ dispatch_offset
;
614 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
616 radeon_emit(cs
, dispatch_va
);
617 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(dispatch_va
>> 32) |
620 si_resource_reference(&dispatch_buf
, NULL
);
624 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
625 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
)) {
626 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
628 radeon_emit(cs
, kernel_args_va
);
629 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
634 for (i
= 0; i
< 3 && user_sgpr
< 16; i
++) {
635 if (code_object
->code_properties
& workgroup_count_masks
[i
]) {
636 radeon_set_sh_reg_seq(cs
,
637 R_00B900_COMPUTE_USER_DATA_0
+
639 radeon_emit(cs
, info
->grid
[i
]);
645 static bool si_upload_compute_input(struct si_context
*sctx
,
646 const amd_kernel_code_t
*code_object
,
647 const struct pipe_grid_info
*info
)
649 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
650 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
651 struct si_resource
*input_buffer
= NULL
;
652 unsigned kernel_args_size
;
653 unsigned num_work_size_bytes
= program
->use_code_object_v2
? 0 : 36;
654 uint32_t kernel_args_offset
= 0;
655 uint32_t *kernel_args
;
656 void *kernel_args_ptr
;
657 uint64_t kernel_args_va
;
660 /* The extra num_work_size_bytes are for work group / work item size information */
661 kernel_args_size
= program
->input_size
+ num_work_size_bytes
;
663 u_upload_alloc(sctx
->b
.const_uploader
, 0, kernel_args_size
,
664 sctx
->screen
->info
.tcc_cache_line_size
,
666 (struct pipe_resource
**)&input_buffer
, &kernel_args_ptr
);
668 if (unlikely(!kernel_args_ptr
))
671 kernel_args
= (uint32_t*)kernel_args_ptr
;
672 kernel_args_va
= input_buffer
->gpu_address
+ kernel_args_offset
;
675 for (i
= 0; i
< 3; i
++) {
676 kernel_args
[i
] = util_cpu_to_le32(info
->grid
[i
]);
677 kernel_args
[i
+ 3] = util_cpu_to_le32(info
->grid
[i
] * info
->block
[i
]);
678 kernel_args
[i
+ 6] = util_cpu_to_le32(info
->block
[i
]);
682 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), info
->input
,
683 program
->input_size
);
686 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
687 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
692 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, input_buffer
,
693 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
696 si_setup_user_sgprs_co_v2(sctx
, code_object
, info
, kernel_args_va
);
698 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
699 radeon_emit(cs
, kernel_args_va
);
700 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
704 si_resource_reference(&input_buffer
, NULL
);
709 static void si_setup_tgsi_user_data(struct si_context
*sctx
,
710 const struct pipe_grid_info
*info
)
712 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
713 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
714 unsigned grid_size_reg
= R_00B900_COMPUTE_USER_DATA_0
+
715 4 * SI_NUM_RESOURCE_SGPRS
;
716 unsigned block_size_reg
= grid_size_reg
+
717 /* 12 bytes = 3 dwords. */
718 12 * program
->uses_grid_size
;
719 unsigned cs_user_data_reg
= block_size_reg
+
720 12 * program
->reads_variable_block_size
;
722 if (info
->indirect
) {
723 if (program
->uses_grid_size
) {
724 for (unsigned i
= 0; i
< 3; ++i
) {
725 si_cp_copy_data(sctx
,
726 COPY_DATA_REG
, NULL
, (grid_size_reg
>> 2) + i
,
727 COPY_DATA_SRC_MEM
, si_resource(info
->indirect
),
728 info
->indirect_offset
+ 4 * i
);
732 if (program
->uses_grid_size
) {
733 radeon_set_sh_reg_seq(cs
, grid_size_reg
, 3);
734 radeon_emit(cs
, info
->grid
[0]);
735 radeon_emit(cs
, info
->grid
[1]);
736 radeon_emit(cs
, info
->grid
[2]);
738 if (program
->reads_variable_block_size
) {
739 radeon_set_sh_reg_seq(cs
, block_size_reg
, 3);
740 radeon_emit(cs
, info
->block
[0]);
741 radeon_emit(cs
, info
->block
[1]);
742 radeon_emit(cs
, info
->block
[2]);
746 if (program
->num_cs_user_data_dwords
) {
747 radeon_set_sh_reg_seq(cs
, cs_user_data_reg
, program
->num_cs_user_data_dwords
);
748 radeon_emit_array(cs
, sctx
->cs_user_data
, program
->num_cs_user_data_dwords
);
752 unsigned si_get_compute_resource_limits(struct si_screen
*sscreen
,
753 unsigned waves_per_threadgroup
,
754 unsigned max_waves_per_sh
)
756 unsigned compute_resource_limits
=
757 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
759 if (sscreen
->info
.chip_class
>= GFX7
) {
760 unsigned num_cu_per_se
= sscreen
->info
.num_good_compute_units
/
761 sscreen
->info
.max_se
;
763 /* Force even distribution on all SIMDs in CU if the workgroup
764 * size is 64. This has shown some good improvements if # of CUs
765 * per SE is not a multiple of 4.
767 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
768 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
770 compute_resource_limits
|= S_00B854_WAVES_PER_SH(max_waves_per_sh
);
773 if (max_waves_per_sh
) {
774 unsigned limit_div16
= DIV_ROUND_UP(max_waves_per_sh
, 16);
775 compute_resource_limits
|= S_00B854_WAVES_PER_SH_SI(limit_div16
);
778 return compute_resource_limits
;
781 static void si_emit_dispatch_packets(struct si_context
*sctx
,
782 const struct pipe_grid_info
*info
)
784 struct si_screen
*sscreen
= sctx
->screen
;
785 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
786 bool render_cond_bit
= sctx
->render_cond
&& !sctx
->render_cond_force_off
;
787 unsigned waves_per_threadgroup
=
788 DIV_ROUND_UP(info
->block
[0] * info
->block
[1] * info
->block
[2], 64);
790 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
791 si_get_compute_resource_limits(sscreen
, waves_per_threadgroup
,
792 sctx
->cs_max_waves_per_sh
));
794 unsigned dispatch_initiator
=
795 S_00B800_COMPUTE_SHADER_EN(1) |
796 S_00B800_FORCE_START_AT_000(1) |
797 /* If the KMD allows it (there is a KMD hw register for it),
798 * allow launching waves out-of-order. (same as Vulkan) */
799 S_00B800_ORDER_MODE(sctx
->chip_class
>= GFX7
);
801 const uint
*last_block
= info
->last_block
;
802 bool partial_block_en
= last_block
[0] || last_block
[1] || last_block
[2];
804 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
806 if (partial_block_en
) {
809 /* If no partial_block, these should be an entire block size, not 0. */
810 partial
[0] = last_block
[0] ? last_block
[0] : info
->block
[0];
811 partial
[1] = last_block
[1] ? last_block
[1] : info
->block
[1];
812 partial
[2] = last_block
[2] ? last_block
[2] : info
->block
[2];
814 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]) |
815 S_00B81C_NUM_THREAD_PARTIAL(partial
[0]));
816 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]) |
817 S_00B820_NUM_THREAD_PARTIAL(partial
[1]));
818 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]) |
819 S_00B824_NUM_THREAD_PARTIAL(partial
[2]));
821 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
823 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]));
824 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]));
825 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]));
828 if (info
->indirect
) {
829 uint64_t base_va
= si_resource(info
->indirect
)->gpu_address
;
831 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
832 si_resource(info
->indirect
),
833 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
835 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
836 PKT3_SHADER_TYPE_S(1));
838 radeon_emit(cs
, base_va
);
839 radeon_emit(cs
, base_va
>> 32);
841 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, render_cond_bit
) |
842 PKT3_SHADER_TYPE_S(1));
843 radeon_emit(cs
, info
->indirect_offset
);
844 radeon_emit(cs
, dispatch_initiator
);
846 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, render_cond_bit
) |
847 PKT3_SHADER_TYPE_S(1));
848 radeon_emit(cs
, info
->grid
[0]);
849 radeon_emit(cs
, info
->grid
[1]);
850 radeon_emit(cs
, info
->grid
[2]);
851 radeon_emit(cs
, dispatch_initiator
);
856 static void si_launch_grid(
857 struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
859 struct si_context
*sctx
= (struct si_context
*)ctx
;
860 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
861 const amd_kernel_code_t
*code_object
=
862 si_compute_get_code_object(program
, info
->pc
);
864 /* HW bug workaround when CS threadgroups > 256 threads and async
865 * compute isn't used, i.e. only one compute job can run at a time.
866 * If async compute is possible, the threadgroup size must be limited
867 * to 256 threads on all queues to avoid the bug.
868 * Only GFX6 and certain GFX7 chips are affected.
870 bool cs_regalloc_hang
=
871 (sctx
->chip_class
== GFX6
||
872 sctx
->family
== CHIP_BONAIRE
||
873 sctx
->family
== CHIP_KABINI
) &&
874 info
->block
[0] * info
->block
[1] * info
->block
[2] > 256;
876 if (cs_regalloc_hang
)
877 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
878 SI_CONTEXT_CS_PARTIAL_FLUSH
;
880 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
&&
881 program
->shader
.compilation_failed
)
884 if (sctx
->has_graphics
) {
885 if (sctx
->last_num_draw_calls
!= sctx
->num_draw_calls
) {
886 si_update_fb_dirtiness_after_rendering(sctx
);
887 sctx
->last_num_draw_calls
= sctx
->num_draw_calls
;
890 si_decompress_textures(sctx
, 1 << PIPE_SHADER_COMPUTE
);
893 /* Add buffer sizes for memory checking in need_cs_space. */
894 si_context_add_resource_size(sctx
, &program
->shader
.bo
->b
.b
);
895 /* TODO: add the scratch buffer */
897 if (info
->indirect
) {
898 si_context_add_resource_size(sctx
, info
->indirect
);
900 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
901 if (sctx
->chip_class
<= GFX8
&&
902 si_resource(info
->indirect
)->TC_L2_dirty
) {
903 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
904 si_resource(info
->indirect
)->TC_L2_dirty
= false;
908 si_need_gfx_cs_space(sctx
);
910 if (sctx
->bo_list_add_all_compute_resources
)
911 si_compute_resources_add_all_to_bo_list(sctx
);
913 if (!sctx
->cs_shader_state
.initialized
) {
914 si_emit_initial_compute_regs(sctx
, sctx
->gfx_cs
);
916 sctx
->cs_shader_state
.emitted_program
= NULL
;
917 sctx
->cs_shader_state
.initialized
= true;
921 si_emit_cache_flush(sctx
);
923 if (!si_switch_compute_shader(sctx
, program
, &program
->shader
,
924 code_object
, info
->pc
))
927 si_upload_compute_shader_descriptors(sctx
);
928 si_emit_compute_shader_pointers(sctx
);
930 if (sctx
->has_graphics
&&
931 si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.render_cond
)) {
932 sctx
->atoms
.s
.render_cond
.emit(sctx
);
933 si_set_atom_dirty(sctx
, &sctx
->atoms
.s
.render_cond
, false);
936 if ((program
->input_size
||
937 program
->ir_type
== PIPE_SHADER_IR_NATIVE
) &&
938 unlikely(!si_upload_compute_input(sctx
, code_object
, info
))) {
943 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
944 struct si_resource
*buffer
=
945 si_resource(program
->global_buffers
[i
]);
949 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, buffer
,
950 RADEON_USAGE_READWRITE
,
951 RADEON_PRIO_COMPUTE_GLOBAL
);
954 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
)
955 si_setup_tgsi_user_data(sctx
, info
);
957 si_emit_dispatch_packets(sctx
, info
);
959 if (unlikely(sctx
->current_saved_cs
)) {
961 si_log_compute_state(sctx
, sctx
->log
);
964 sctx
->compute_is_busy
= true;
965 sctx
->num_compute_calls
++;
966 if (sctx
->cs_shader_state
.uses_scratch
)
967 sctx
->num_spill_compute_calls
++;
969 if (cs_regalloc_hang
)
970 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
973 void si_destroy_compute(struct si_compute
*program
)
975 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
976 util_queue_drop_job(&program
->screen
->shader_compiler_queue
,
978 util_queue_fence_destroy(&program
->ready
);
981 si_shader_destroy(&program
->shader
);
985 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
986 struct si_compute
*program
= (struct si_compute
*)state
;
987 struct si_context
*sctx
= (struct si_context
*)ctx
;
992 if (program
== sctx
->cs_shader_state
.program
)
993 sctx
->cs_shader_state
.program
= NULL
;
995 if (program
== sctx
->cs_shader_state
.emitted_program
)
996 sctx
->cs_shader_state
.emitted_program
= NULL
;
998 si_compute_reference(&program
, NULL
);
1001 static void si_set_compute_resources(struct pipe_context
* ctx_
,
1002 unsigned start
, unsigned count
,
1003 struct pipe_surface
** surfaces
) { }
1005 void si_init_compute_functions(struct si_context
*sctx
)
1007 sctx
->b
.create_compute_state
= si_create_compute_state
;
1008 sctx
->b
.delete_compute_state
= si_delete_compute_state
;
1009 sctx
->b
.bind_compute_state
= si_bind_compute_state
;
1010 sctx
->b
.set_compute_resources
= si_set_compute_resources
;
1011 sctx
->b
.set_global_binding
= si_set_global_binding
;
1012 sctx
->b
.launch_grid
= si_launch_grid
;