2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
31 #include "amd_kernel_code_t.h"
32 #include "radeon/r600_cs.h"
34 #include "si_compute.h"
37 #define COMPUTE_DBG(rscreen, fmt, args...) \
39 if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
42 struct dispatch_packet
{
45 uint16_t workgroup_size_x
;
46 uint16_t workgroup_size_y
;
47 uint16_t workgroup_size_z
;
52 uint32_t private_segment_size
;
53 uint32_t group_segment_size
;
54 uint64_t kernel_object
;
55 uint64_t kernarg_address
;
59 static const amd_kernel_code_t
*si_compute_get_code_object(
60 const struct si_compute
*program
,
61 uint64_t symbol_offset
)
63 if (!program
->use_code_object_v2
) {
66 return (const amd_kernel_code_t
*)
67 (program
->shader
.binary
.code
+ symbol_offset
);
70 static void code_object_to_config(const amd_kernel_code_t
*code_object
,
71 struct si_shader_config
*out_config
) {
73 uint32_t rsrc1
= code_object
->compute_pgm_resource_registers
;
74 uint32_t rsrc2
= code_object
->compute_pgm_resource_registers
>> 32;
75 out_config
->num_sgprs
= code_object
->wavefront_sgpr_count
;
76 out_config
->num_vgprs
= code_object
->workitem_vgpr_count
;
77 out_config
->float_mode
= G_00B028_FLOAT_MODE(rsrc1
);
78 out_config
->rsrc1
= rsrc1
;
79 out_config
->lds_size
= MAX2(out_config
->lds_size
, G_00B84C_LDS_SIZE(rsrc2
));
80 out_config
->rsrc2
= rsrc2
;
81 out_config
->scratch_bytes_per_wave
=
82 align(code_object
->workitem_private_segment_byte_size
* 64, 1024);
85 /* Asynchronous compute shader compilation. */
86 static void si_create_compute_state_async(void *job
, int thread_index
)
88 struct si_compute
*program
= (struct si_compute
*)job
;
89 struct si_shader
*shader
= &program
->shader
;
90 struct si_shader_selector sel
;
91 LLVMTargetMachineRef tm
;
92 struct pipe_debug_callback
*debug
= &program
->compiler_ctx_state
.debug
;
94 assert(!debug
->debug_message
|| debug
->async
);
95 assert(thread_index
>= 0);
96 assert(thread_index
< ARRAY_SIZE(program
->screen
->tm
));
97 tm
= program
->screen
->tm
[thread_index
];
99 memset(&sel
, 0, sizeof(sel
));
101 sel
.screen
= program
->screen
;
103 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
) {
104 tgsi_scan_shader(program
->ir
.tgsi
, &sel
.info
);
105 sel
.tokens
= program
->ir
.tgsi
;
107 assert(program
->ir_type
== PIPE_SHADER_IR_NIR
);
108 sel
.nir
= program
->ir
.nir
;
110 si_nir_scan_shader(sel
.nir
, &sel
.info
);
115 sel
.type
= PIPE_SHADER_COMPUTE
;
116 sel
.local_size
= program
->local_size
;
117 si_get_active_slot_masks(&sel
.info
,
118 &program
->active_const_and_shader_buffers
,
119 &program
->active_samplers_and_images
);
121 program
->shader
.selector
= &sel
;
122 program
->shader
.is_monolithic
= true;
123 program
->uses_grid_size
= sel
.info
.uses_grid_size
;
124 program
->uses_block_size
= sel
.info
.uses_block_size
;
125 program
->uses_bindless_samplers
= sel
.info
.uses_bindless_samplers
;
126 program
->uses_bindless_images
= sel
.info
.uses_bindless_images
;
128 if (si_shader_create(program
->screen
, tm
, &program
->shader
, debug
)) {
129 program
->shader
.compilation_failed
= true;
131 bool scratch_enabled
= shader
->config
.scratch_bytes_per_wave
> 0;
132 unsigned user_sgprs
= SI_NUM_RESOURCE_SGPRS
+
133 (sel
.info
.uses_grid_size
? 3 : 0) +
134 (sel
.info
.uses_block_size
? 3 : 0);
136 shader
->config
.rsrc1
=
137 S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
138 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
139 S_00B848_DX10_CLAMP(1) |
140 S_00B848_FLOAT_MODE(shader
->config
.float_mode
);
142 shader
->config
.rsrc2
=
143 S_00B84C_USER_SGPR(user_sgprs
) |
144 S_00B84C_SCRATCH_EN(scratch_enabled
) |
145 S_00B84C_TGID_X_EN(sel
.info
.uses_block_id
[0]) |
146 S_00B84C_TGID_Y_EN(sel
.info
.uses_block_id
[1]) |
147 S_00B84C_TGID_Z_EN(sel
.info
.uses_block_id
[2]) |
148 S_00B84C_TIDIG_COMP_CNT(sel
.info
.uses_thread_id
[2] ? 2 :
149 sel
.info
.uses_thread_id
[1] ? 1 : 0) |
150 S_00B84C_LDS_SIZE(shader
->config
.lds_size
);
152 program
->variable_group_size
=
153 sel
.info
.properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0;
156 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
157 FREE(program
->ir
.tgsi
);
159 program
->shader
.selector
= NULL
;
162 static void *si_create_compute_state(
163 struct pipe_context
*ctx
,
164 const struct pipe_compute_state
*cso
)
166 struct si_context
*sctx
= (struct si_context
*)ctx
;
167 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
168 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
170 pipe_reference_init(&program
->reference
, 1);
171 program
->screen
= (struct si_screen
*)ctx
->screen
;
172 program
->ir_type
= cso
->ir_type
;
173 program
->local_size
= cso
->req_local_mem
;
174 program
->private_size
= cso
->req_private_mem
;
175 program
->input_size
= cso
->req_input_mem
;
176 program
->use_code_object_v2
= cso
->ir_type
== PIPE_SHADER_IR_NATIVE
;
178 if (cso
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
179 if (cso
->ir_type
== PIPE_SHADER_IR_TGSI
) {
180 program
->ir
.tgsi
= tgsi_dup_tokens(cso
->prog
);
181 if (!program
->ir
.tgsi
) {
186 assert(cso
->ir_type
== PIPE_SHADER_IR_NIR
);
187 program
->ir
.nir
= (struct nir_shader
*) cso
->prog
;
190 program
->compiler_ctx_state
.debug
= sctx
->debug
;
191 program
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
192 p_atomic_inc(&sscreen
->num_shaders_created
);
193 util_queue_fence_init(&program
->ready
);
195 struct util_async_debug_callback async_debug
;
197 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
199 si_can_dump_shader(sscreen
, PIPE_SHADER_COMPUTE
);
202 u_async_debug_init(&async_debug
);
203 program
->compiler_ctx_state
.debug
= async_debug
.base
;
206 util_queue_add_job(&sscreen
->shader_compiler_queue
,
207 program
, &program
->ready
,
208 si_create_compute_state_async
, NULL
);
211 util_queue_fence_wait(&program
->ready
);
212 u_async_debug_drain(&async_debug
, &sctx
->debug
);
213 u_async_debug_cleanup(&async_debug
);
216 const struct pipe_llvm_program_header
*header
;
219 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
221 ac_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
222 if (program
->use_code_object_v2
) {
223 const amd_kernel_code_t
*code_object
=
224 si_compute_get_code_object(program
, 0);
225 code_object_to_config(code_object
, &program
->shader
.config
);
227 si_shader_binary_read_config(&program
->shader
.binary
,
228 &program
->shader
.config
, 0);
230 si_shader_dump(sctx
->screen
, &program
->shader
, &sctx
->debug
,
231 PIPE_SHADER_COMPUTE
, stderr
, true);
232 if (si_shader_binary_upload(sctx
->screen
, &program
->shader
) < 0) {
233 fprintf(stderr
, "LLVM failed to upload shader\n");
242 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
244 struct si_context
*sctx
= (struct si_context
*)ctx
;
245 struct si_compute
*program
= (struct si_compute
*)state
;
247 sctx
->cs_shader_state
.program
= program
;
251 /* Wait because we need active slot usage masks. */
252 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
)
253 util_queue_fence_wait(&program
->ready
);
255 si_set_active_descriptors(sctx
,
256 SI_DESCS_FIRST_COMPUTE
+
257 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
258 program
->active_const_and_shader_buffers
);
259 si_set_active_descriptors(sctx
,
260 SI_DESCS_FIRST_COMPUTE
+
261 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
262 program
->active_samplers_and_images
);
265 static void si_set_global_binding(
266 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
267 struct pipe_resource
**resources
,
271 struct si_context
*sctx
= (struct si_context
*)ctx
;
272 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
274 assert(first
+ n
<= MAX_GLOBAL_BUFFERS
);
277 for (i
= 0; i
< n
; i
++) {
278 pipe_resource_reference(&program
->global_buffers
[first
+ i
], NULL
);
283 for (i
= 0; i
< n
; i
++) {
286 pipe_resource_reference(&program
->global_buffers
[first
+ i
], resources
[i
]);
287 va
= r600_resource(resources
[i
])->gpu_address
;
288 offset
= util_le32_to_cpu(*handles
[i
]);
290 va
= util_cpu_to_le64(va
);
291 memcpy(handles
[i
], &va
, sizeof(va
));
295 static void si_initialize_compute(struct si_context
*sctx
)
297 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
300 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
301 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
302 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
303 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
305 if (sctx
->b
.chip_class
>= CIK
) {
306 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
307 radeon_set_sh_reg_seq(cs
,
308 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
309 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
310 S_00B864_SH1_CU_EN(0xffff));
311 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
312 S_00B868_SH1_CU_EN(0xffff));
315 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
316 * and is now per pipe, so it should be handled in the
317 * kernel if we want to use something other than the default value,
318 * which is now 0x22f.
320 if (sctx
->b
.chip_class
<= SI
) {
321 /* XXX: This should be:
322 * (number of compute units) * 4 * (waves per simd) - 1 */
324 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
325 0x190 /* Default value */);
328 /* Set the pointer to border colors. */
329 bc_va
= sctx
->border_color_buffer
->gpu_address
;
331 if (sctx
->b
.chip_class
>= CIK
) {
332 radeon_set_uconfig_reg_seq(cs
, R_030E00_TA_CS_BC_BASE_ADDR
, 2);
333 radeon_emit(cs
, bc_va
>> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
334 radeon_emit(cs
, S_030E04_ADDRESS(bc_va
>> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
336 if (sctx
->screen
->info
.drm_major
== 3 ||
337 (sctx
->screen
->info
.drm_major
== 2 &&
338 sctx
->screen
->info
.drm_minor
>= 48)) {
339 radeon_set_config_reg(cs
, R_00950C_TA_CS_BC_BASE_ADDR
,
344 sctx
->cs_shader_state
.emitted_program
= NULL
;
345 sctx
->cs_shader_state
.initialized
= true;
348 static bool si_setup_compute_scratch_buffer(struct si_context
*sctx
,
349 struct si_shader
*shader
,
350 struct si_shader_config
*config
)
352 uint64_t scratch_bo_size
, scratch_needed
;
354 scratch_needed
= config
->scratch_bytes_per_wave
* sctx
->scratch_waves
;
355 if (sctx
->compute_scratch_buffer
)
356 scratch_bo_size
= sctx
->compute_scratch_buffer
->b
.b
.width0
;
358 if (scratch_bo_size
< scratch_needed
) {
359 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
361 sctx
->compute_scratch_buffer
= (struct r600_resource
*)
362 si_aligned_buffer_create(&sctx
->screen
->b
,
363 SI_RESOURCE_FLAG_UNMAPPABLE
,
365 scratch_needed
, 256);
367 if (!sctx
->compute_scratch_buffer
)
371 if (sctx
->compute_scratch_buffer
!= shader
->scratch_bo
&& scratch_needed
) {
372 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
374 si_shader_apply_scratch_relocs(shader
, scratch_va
);
376 if (si_shader_binary_upload(sctx
->screen
, shader
))
379 r600_resource_reference(&shader
->scratch_bo
,
380 sctx
->compute_scratch_buffer
);
386 static bool si_switch_compute_shader(struct si_context
*sctx
,
387 struct si_compute
*program
,
388 struct si_shader
*shader
,
389 const amd_kernel_code_t
*code_object
,
392 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
393 struct si_shader_config inline_config
= {0};
394 struct si_shader_config
*config
;
397 if (sctx
->cs_shader_state
.emitted_program
== program
&&
398 sctx
->cs_shader_state
.offset
== offset
)
401 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
402 config
= &shader
->config
;
406 config
= &inline_config
;
408 code_object_to_config(code_object
, config
);
410 si_shader_binary_read_config(&shader
->binary
, config
, offset
);
413 lds_blocks
= config
->lds_size
;
414 /* XXX: We are over allocating LDS. For SI, the shader reports
415 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
416 * allocated in the shader and 4 bytes allocated by the state
417 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
419 if (sctx
->b
.chip_class
<= SI
) {
420 lds_blocks
+= align(program
->local_size
, 256) >> 8;
422 lds_blocks
+= align(program
->local_size
, 512) >> 9;
425 /* TODO: use si_multiwave_lds_size_workaround */
426 assert(lds_blocks
<= 0xFF);
428 config
->rsrc2
&= C_00B84C_LDS_SIZE
;
429 config
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
432 if (!si_setup_compute_scratch_buffer(sctx
, shader
, config
))
435 if (shader
->scratch_bo
) {
436 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
437 "Total Scratch: %u bytes\n", sctx
->scratch_waves
,
438 config
->scratch_bytes_per_wave
,
439 config
->scratch_bytes_per_wave
*
440 sctx
->scratch_waves
);
442 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
443 shader
->scratch_bo
, RADEON_USAGE_READWRITE
,
444 RADEON_PRIO_SCRATCH_BUFFER
);
447 /* Prefetch the compute shader to TC L2.
449 * We should also prefetch graphics shaders if a compute dispatch was
450 * the last command, and the compute shader if a draw call was the last
451 * command. However, that would add more complexity and we're likely
452 * to get a shader state change in that case anyway.
454 if (sctx
->b
.chip_class
>= CIK
) {
455 cik_prefetch_TC_L2_async(sctx
, &program
->shader
.bo
->b
.b
,
456 0, program
->shader
.bo
->b
.b
.width0
);
459 shader_va
= shader
->bo
->gpu_address
+ offset
;
460 if (program
->use_code_object_v2
) {
461 /* Shader code is placed after the amd_kernel_code_t
463 shader_va
+= sizeof(amd_kernel_code_t
);
466 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
, shader
->bo
,
467 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
469 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
470 radeon_emit(cs
, shader_va
>> 8);
471 radeon_emit(cs
, S_00B834_DATA(shader_va
>> 40));
473 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
474 radeon_emit(cs
, config
->rsrc1
);
475 radeon_emit(cs
, config
->rsrc2
);
477 COMPUTE_DBG(sctx
->screen
, "COMPUTE_PGM_RSRC1: 0x%08x "
478 "COMPUTE_PGM_RSRC2: 0x%08x\n", config
->rsrc1
, config
->rsrc2
);
480 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
481 S_00B860_WAVES(sctx
->scratch_waves
)
482 | S_00B860_WAVESIZE(config
->scratch_bytes_per_wave
>> 10));
484 sctx
->cs_shader_state
.emitted_program
= program
;
485 sctx
->cs_shader_state
.offset
= offset
;
486 sctx
->cs_shader_state
.uses_scratch
=
487 config
->scratch_bytes_per_wave
!= 0;
492 static void setup_scratch_rsrc_user_sgprs(struct si_context
*sctx
,
493 const amd_kernel_code_t
*code_object
,
496 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
497 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
499 unsigned max_private_element_size
= AMD_HSA_BITS_GET(
500 code_object
->code_properties
,
501 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
);
503 uint32_t scratch_dword0
= scratch_va
& 0xffffffff;
504 uint32_t scratch_dword1
=
505 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
506 S_008F04_SWIZZLE_ENABLE(1);
508 /* Disable address clamping */
509 uint32_t scratch_dword2
= 0xffffffff;
510 uint32_t scratch_dword3
=
511 S_008F0C_INDEX_STRIDE(3) |
512 S_008F0C_ADD_TID_ENABLE(1);
514 if (sctx
->b
.chip_class
>= GFX9
) {
515 assert(max_private_element_size
== 1); /* always 4 bytes on GFX9 */
517 scratch_dword3
|= S_008F0C_ELEMENT_SIZE(max_private_element_size
);
519 if (sctx
->b
.chip_class
< VI
) {
520 /* BUF_DATA_FORMAT is ignored, but it cannot be
521 * BUF_DATA_FORMAT_INVALID. */
523 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8
);
527 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
529 radeon_emit(cs
, scratch_dword0
);
530 radeon_emit(cs
, scratch_dword1
);
531 radeon_emit(cs
, scratch_dword2
);
532 radeon_emit(cs
, scratch_dword3
);
535 static void si_setup_user_sgprs_co_v2(struct si_context
*sctx
,
536 const amd_kernel_code_t
*code_object
,
537 const struct pipe_grid_info
*info
,
538 uint64_t kernel_args_va
)
540 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
541 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
543 static const enum amd_code_property_mask_t workgroup_count_masks
[] = {
544 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X
,
545 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y
,
546 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
549 unsigned i
, user_sgpr
= 0;
550 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
551 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
)) {
552 if (code_object
->workitem_private_segment_byte_size
> 0) {
553 setup_scratch_rsrc_user_sgprs(sctx
, code_object
,
559 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
560 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
)) {
561 struct dispatch_packet dispatch
;
562 unsigned dispatch_offset
;
563 struct r600_resource
*dispatch_buf
= NULL
;
564 uint64_t dispatch_va
;
566 /* Upload dispatch ptr */
567 memset(&dispatch
, 0, sizeof(dispatch
));
569 dispatch
.workgroup_size_x
= info
->block
[0];
570 dispatch
.workgroup_size_y
= info
->block
[1];
571 dispatch
.workgroup_size_z
= info
->block
[2];
573 dispatch
.grid_size_x
= info
->grid
[0] * info
->block
[0];
574 dispatch
.grid_size_y
= info
->grid
[1] * info
->block
[1];
575 dispatch
.grid_size_z
= info
->grid
[2] * info
->block
[2];
577 dispatch
.private_segment_size
= program
->private_size
;
578 dispatch
.group_segment_size
= program
->local_size
;
580 dispatch
.kernarg_address
= kernel_args_va
;
582 u_upload_data(sctx
->b
.b
.const_uploader
, 0, sizeof(dispatch
),
583 256, &dispatch
, &dispatch_offset
,
584 (struct pipe_resource
**)&dispatch_buf
);
587 fprintf(stderr
, "Error: Failed to allocate dispatch "
590 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
, dispatch_buf
,
591 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
593 dispatch_va
= dispatch_buf
->gpu_address
+ dispatch_offset
;
595 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
597 radeon_emit(cs
, dispatch_va
);
598 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(dispatch_va
>> 32) |
601 r600_resource_reference(&dispatch_buf
, NULL
);
605 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
606 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
)) {
607 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
609 radeon_emit(cs
, kernel_args_va
);
610 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
615 for (i
= 0; i
< 3 && user_sgpr
< 16; i
++) {
616 if (code_object
->code_properties
& workgroup_count_masks
[i
]) {
617 radeon_set_sh_reg_seq(cs
,
618 R_00B900_COMPUTE_USER_DATA_0
+
620 radeon_emit(cs
, info
->grid
[i
]);
626 static bool si_upload_compute_input(struct si_context
*sctx
,
627 const amd_kernel_code_t
*code_object
,
628 const struct pipe_grid_info
*info
)
630 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
631 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
632 struct r600_resource
*input_buffer
= NULL
;
633 unsigned kernel_args_size
;
634 unsigned num_work_size_bytes
= program
->use_code_object_v2
? 0 : 36;
635 uint32_t kernel_args_offset
= 0;
636 uint32_t *kernel_args
;
637 void *kernel_args_ptr
;
638 uint64_t kernel_args_va
;
641 /* The extra num_work_size_bytes are for work group / work item size information */
642 kernel_args_size
= program
->input_size
+ num_work_size_bytes
;
644 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, kernel_args_size
,
645 sctx
->screen
->info
.tcc_cache_line_size
,
647 (struct pipe_resource
**)&input_buffer
, &kernel_args_ptr
);
649 if (unlikely(!kernel_args_ptr
))
652 kernel_args
= (uint32_t*)kernel_args_ptr
;
653 kernel_args_va
= input_buffer
->gpu_address
+ kernel_args_offset
;
656 for (i
= 0; i
< 3; i
++) {
657 kernel_args
[i
] = info
->grid
[i
];
658 kernel_args
[i
+ 3] = info
->grid
[i
] * info
->block
[i
];
659 kernel_args
[i
+ 6] = info
->block
[i
];
663 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), info
->input
,
664 program
->input_size
);
667 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
668 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
673 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
, input_buffer
,
674 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
677 si_setup_user_sgprs_co_v2(sctx
, code_object
, info
, kernel_args_va
);
679 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
680 radeon_emit(cs
, kernel_args_va
);
681 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
685 r600_resource_reference(&input_buffer
, NULL
);
690 static void si_setup_tgsi_grid(struct si_context
*sctx
,
691 const struct pipe_grid_info
*info
)
693 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
694 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
695 unsigned grid_size_reg
= R_00B900_COMPUTE_USER_DATA_0
+
696 4 * SI_NUM_RESOURCE_SGPRS
;
697 unsigned block_size_reg
= grid_size_reg
+
698 /* 12 bytes = 3 dwords. */
699 12 * program
->uses_grid_size
;
701 if (info
->indirect
) {
702 if (program
->uses_grid_size
) {
703 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
704 uint64_t va
= base_va
+ info
->indirect_offset
;
707 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
708 (struct r600_resource
*)info
->indirect
,
709 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
711 for (i
= 0; i
< 3; ++i
) {
712 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
713 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
714 COPY_DATA_DST_SEL(COPY_DATA_REG
));
715 radeon_emit(cs
, (va
+ 4 * i
));
716 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
717 radeon_emit(cs
, (grid_size_reg
>> 2) + i
);
722 if (program
->uses_grid_size
) {
723 radeon_set_sh_reg_seq(cs
, grid_size_reg
, 3);
724 radeon_emit(cs
, info
->grid
[0]);
725 radeon_emit(cs
, info
->grid
[1]);
726 radeon_emit(cs
, info
->grid
[2]);
728 if (program
->variable_group_size
&& program
->uses_block_size
) {
729 radeon_set_sh_reg_seq(cs
, block_size_reg
, 3);
730 radeon_emit(cs
, info
->block
[0]);
731 radeon_emit(cs
, info
->block
[1]);
732 radeon_emit(cs
, info
->block
[2]);
737 static void si_emit_dispatch_packets(struct si_context
*sctx
,
738 const struct pipe_grid_info
*info
)
740 struct si_screen
*sscreen
= sctx
->screen
;
741 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
742 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
743 unsigned waves_per_threadgroup
=
744 DIV_ROUND_UP(info
->block
[0] * info
->block
[1] * info
->block
[2], 64);
745 unsigned compute_resource_limits
=
746 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
748 if (sctx
->b
.chip_class
>= CIK
) {
749 unsigned num_cu_per_se
= sscreen
->info
.num_good_compute_units
/
750 sscreen
->info
.max_se
;
752 /* Force even distribution on all SIMDs in CU if the workgroup
753 * size is 64. This has shown some good improvements if # of CUs
754 * per SE is not a multiple of 4.
756 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
757 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
760 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
761 compute_resource_limits
);
763 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
764 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]));
765 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]));
766 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]));
768 unsigned dispatch_initiator
=
769 S_00B800_COMPUTE_SHADER_EN(1) |
770 S_00B800_FORCE_START_AT_000(1) |
771 /* If the KMD allows it (there is a KMD hw register for it),
772 * allow launching waves out-of-order. (same as Vulkan) */
773 S_00B800_ORDER_MODE(sctx
->b
.chip_class
>= CIK
);
775 if (info
->indirect
) {
776 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
778 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
779 (struct r600_resource
*)info
->indirect
,
780 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
782 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
783 PKT3_SHADER_TYPE_S(1));
785 radeon_emit(cs
, base_va
);
786 radeon_emit(cs
, base_va
>> 32);
788 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, render_cond_bit
) |
789 PKT3_SHADER_TYPE_S(1));
790 radeon_emit(cs
, info
->indirect_offset
);
791 radeon_emit(cs
, dispatch_initiator
);
793 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, render_cond_bit
) |
794 PKT3_SHADER_TYPE_S(1));
795 radeon_emit(cs
, info
->grid
[0]);
796 radeon_emit(cs
, info
->grid
[1]);
797 radeon_emit(cs
, info
->grid
[2]);
798 radeon_emit(cs
, dispatch_initiator
);
803 static void si_launch_grid(
804 struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
806 struct si_context
*sctx
= (struct si_context
*)ctx
;
807 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
808 const amd_kernel_code_t
*code_object
=
809 si_compute_get_code_object(program
, info
->pc
);
811 /* HW bug workaround when CS threadgroups > 256 threads and async
812 * compute isn't used, i.e. only one compute job can run at a time.
813 * If async compute is possible, the threadgroup size must be limited
814 * to 256 threads on all queues to avoid the bug.
815 * Only SI and certain CIK chips are affected.
817 bool cs_regalloc_hang
=
818 (sctx
->b
.chip_class
== SI
||
819 sctx
->b
.family
== CHIP_BONAIRE
||
820 sctx
->b
.family
== CHIP_KABINI
) &&
821 info
->block
[0] * info
->block
[1] * info
->block
[2] > 256;
823 if (cs_regalloc_hang
)
824 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
825 SI_CONTEXT_CS_PARTIAL_FLUSH
;
827 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
&&
828 program
->shader
.compilation_failed
)
831 if (sctx
->b
.last_num_draw_calls
!= sctx
->b
.num_draw_calls
) {
832 si_update_fb_dirtiness_after_rendering(sctx
);
833 sctx
->b
.last_num_draw_calls
= sctx
->b
.num_draw_calls
;
836 si_decompress_textures(sctx
, 1 << PIPE_SHADER_COMPUTE
);
838 /* Add buffer sizes for memory checking in need_cs_space. */
839 si_context_add_resource_size(sctx
, &program
->shader
.bo
->b
.b
);
840 /* TODO: add the scratch buffer */
842 if (info
->indirect
) {
843 si_context_add_resource_size(sctx
, info
->indirect
);
845 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
846 if (sctx
->b
.chip_class
<= VI
&&
847 r600_resource(info
->indirect
)->TC_L2_dirty
) {
848 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
849 r600_resource(info
->indirect
)->TC_L2_dirty
= false;
853 si_need_gfx_cs_space(sctx
);
855 if (!sctx
->cs_shader_state
.initialized
)
856 si_initialize_compute(sctx
);
859 si_emit_cache_flush(sctx
);
861 if (!si_switch_compute_shader(sctx
, program
, &program
->shader
,
862 code_object
, info
->pc
))
865 si_upload_compute_shader_descriptors(sctx
);
866 si_emit_compute_shader_pointers(sctx
);
868 if (si_is_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
)) {
869 sctx
->atoms
.s
.render_cond
->emit(sctx
,
870 sctx
->atoms
.s
.render_cond
);
871 si_set_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
, false);
874 if ((program
->input_size
||
875 program
->ir_type
== PIPE_SHADER_IR_NATIVE
) &&
876 unlikely(!si_upload_compute_input(sctx
, code_object
, info
))) {
881 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
882 struct r600_resource
*buffer
=
883 (struct r600_resource
*)program
->global_buffers
[i
];
887 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
, buffer
,
888 RADEON_USAGE_READWRITE
,
889 RADEON_PRIO_COMPUTE_GLOBAL
);
892 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
)
893 si_setup_tgsi_grid(sctx
, info
);
895 si_emit_dispatch_packets(sctx
, info
);
897 if (unlikely(sctx
->current_saved_cs
)) {
899 si_log_compute_state(sctx
, sctx
->b
.log
);
902 sctx
->compute_is_busy
= true;
903 sctx
->b
.num_compute_calls
++;
904 if (sctx
->cs_shader_state
.uses_scratch
)
905 sctx
->b
.num_spill_compute_calls
++;
907 if (cs_regalloc_hang
)
908 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
911 void si_destroy_compute(struct si_compute
*program
)
913 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
914 util_queue_drop_job(&program
->screen
->shader_compiler_queue
,
916 util_queue_fence_destroy(&program
->ready
);
919 si_shader_destroy(&program
->shader
);
923 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
924 struct si_compute
*program
= (struct si_compute
*)state
;
925 struct si_context
*sctx
= (struct si_context
*)ctx
;
930 if (program
== sctx
->cs_shader_state
.program
)
931 sctx
->cs_shader_state
.program
= NULL
;
933 if (program
== sctx
->cs_shader_state
.emitted_program
)
934 sctx
->cs_shader_state
.emitted_program
= NULL
;
936 si_compute_reference(&program
, NULL
);
939 static void si_set_compute_resources(struct pipe_context
* ctx_
,
940 unsigned start
, unsigned count
,
941 struct pipe_surface
** surfaces
) { }
943 void si_init_compute_functions(struct si_context
*sctx
)
945 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
946 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
947 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
948 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
949 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
950 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
951 sctx
->b
.b
.launch_grid
= si_launch_grid
;