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[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "ac_rtld.h"
32 #include "amd_kernel_code_t.h"
33 #include "si_build_pm4.h"
34 #include "si_compute.h"
35
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
37 do { \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
39 } while (0);
40
41 struct dispatch_packet {
42 uint16_t header;
43 uint16_t setup;
44 uint16_t workgroup_size_x;
45 uint16_t workgroup_size_y;
46 uint16_t workgroup_size_z;
47 uint16_t reserved0;
48 uint32_t grid_size_x;
49 uint32_t grid_size_y;
50 uint32_t grid_size_z;
51 uint32_t private_segment_size;
52 uint32_t group_segment_size;
53 uint64_t kernel_object;
54 uint64_t kernarg_address;
55 uint64_t reserved2;
56 };
57
58 static const amd_kernel_code_t *si_compute_get_code_object(
59 const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 const struct si_shader_selector *sel = &program->sel;
63
64 if (!program->use_code_object_v2) {
65 return NULL;
66 }
67
68 struct ac_rtld_binary rtld;
69 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
70 .info = &sel->screen->info,
71 .shader_type = MESA_SHADER_COMPUTE,
72 .num_parts = 1,
73 .elf_ptrs = &program->shader.binary.elf_buffer,
74 .elf_sizes = &program->shader.binary.elf_size }))
75 return NULL;
76
77 const amd_kernel_code_t *result = NULL;
78 const char *text;
79 size_t size;
80 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
81 goto out;
82
83 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
84 goto out;
85
86 result = (const amd_kernel_code_t*)(text + symbol_offset);
87
88 out:
89 ac_rtld_close(&rtld);
90 return result;
91 }
92
93 static void code_object_to_config(const amd_kernel_code_t *code_object,
94 struct ac_shader_config *out_config) {
95
96 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
97 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
98 out_config->num_sgprs = code_object->wavefront_sgpr_count;
99 out_config->num_vgprs = code_object->workitem_vgpr_count;
100 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
101 out_config->rsrc1 = rsrc1;
102 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
103 out_config->rsrc2 = rsrc2;
104 out_config->scratch_bytes_per_wave =
105 align(code_object->workitem_private_segment_byte_size * 64, 1024);
106 }
107
108 /* Asynchronous compute shader compilation. */
109 static void si_create_compute_state_async(void *job, int thread_index)
110 {
111 struct si_compute *program = (struct si_compute *)job;
112 struct si_shader_selector *sel = &program->sel;
113 struct si_shader *shader = &program->shader;
114 struct ac_llvm_compiler *compiler;
115 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
116 struct si_screen *sscreen = sel->screen;
117
118 assert(!debug->debug_message || debug->async);
119 assert(thread_index >= 0);
120 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
121 compiler = &sscreen->compiler[thread_index];
122
123 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
124 tgsi_scan_shader(sel->tokens, &sel->info);
125 } else {
126 assert(program->ir_type == PIPE_SHADER_IR_NIR);
127
128 si_nir_opts(sel->nir);
129 si_nir_scan_shader(sel->nir, &sel->info);
130 si_lower_nir(sel);
131 }
132
133 /* Store the declared LDS size into tgsi_shader_info for the shader
134 * cache to include it.
135 */
136 sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
137
138 si_get_active_slot_masks(&sel->info,
139 &sel->active_const_and_shader_buffers,
140 &sel->active_samplers_and_images);
141
142 program->shader.is_monolithic = true;
143 program->reads_variable_block_size =
144 sel->info.uses_block_size &&
145 sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
146 program->num_cs_user_data_dwords =
147 sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
148
149 void *ir_binary = si_get_ir_binary(sel);
150
151 /* Try to load the shader from the shader cache. */
152 mtx_lock(&sscreen->shader_cache_mutex);
153
154 if (ir_binary &&
155 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
156 mtx_unlock(&sscreen->shader_cache_mutex);
157
158 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
159 si_shader_dump(sscreen, shader, debug, stderr, true);
160
161 if (!si_shader_binary_upload(sscreen, shader, 0))
162 program->shader.compilation_failed = true;
163 } else {
164 mtx_unlock(&sscreen->shader_cache_mutex);
165
166 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
167 program->shader.compilation_failed = true;
168
169 if (program->ir_type == PIPE_SHADER_IR_TGSI)
170 FREE(sel->tokens);
171 return;
172 }
173
174 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
175 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
176 (sel->info.uses_grid_size ? 3 : 0) +
177 (program->reads_variable_block_size ? 3 : 0) +
178 program->num_cs_user_data_dwords;
179
180 shader->config.rsrc1 =
181 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
182 S_00B848_DX10_CLAMP(1) |
183 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
184 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
185 S_00B848_FLOAT_MODE(shader->config.float_mode);
186
187 if (sscreen->info.chip_class < GFX10) {
188 shader->config.rsrc1 |=
189 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
190 }
191
192 shader->config.rsrc2 =
193 S_00B84C_USER_SGPR(user_sgprs) |
194 S_00B84C_SCRATCH_EN(scratch_enabled) |
195 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
196 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
197 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
198 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2] ? 2 :
199 sel->info.uses_thread_id[1] ? 1 : 0) |
200 S_00B84C_LDS_SIZE(shader->config.lds_size);
201
202 if (ir_binary) {
203 mtx_lock(&sscreen->shader_cache_mutex);
204 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
205 FREE(ir_binary);
206 mtx_unlock(&sscreen->shader_cache_mutex);
207 }
208 }
209
210 if (program->ir_type == PIPE_SHADER_IR_TGSI)
211 FREE(sel->tokens);
212 }
213
214 static void *si_create_compute_state(
215 struct pipe_context *ctx,
216 const struct pipe_compute_state *cso)
217 {
218 struct si_context *sctx = (struct si_context *)ctx;
219 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
220 struct si_compute *program = CALLOC_STRUCT(si_compute);
221 struct si_shader_selector *sel = &program->sel;
222
223 pipe_reference_init(&sel->reference, 1);
224 sel->type = PIPE_SHADER_COMPUTE;
225 sel->screen = sscreen;
226 program->shader.selector = &program->sel;
227 program->ir_type = cso->ir_type;
228 program->local_size = cso->req_local_mem;
229 program->private_size = cso->req_private_mem;
230 program->input_size = cso->req_input_mem;
231 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
232
233 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
234 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
235 sel->tokens = tgsi_dup_tokens(cso->prog);
236 if (!sel->tokens) {
237 FREE(program);
238 return NULL;
239 }
240 } else {
241 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
242 sel->nir = (struct nir_shader *) cso->prog;
243 }
244
245 sel->compiler_ctx_state.debug = sctx->debug;
246 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
247 p_atomic_inc(&sscreen->num_shaders_created);
248
249 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
250 &sel->ready,
251 &sel->compiler_ctx_state,
252 program, si_create_compute_state_async);
253 } else {
254 const struct pipe_llvm_program_header *header;
255 const char *code;
256 header = cso->prog;
257 code = cso->prog + sizeof(struct pipe_llvm_program_header);
258
259 program->shader.binary.elf_size = header->num_bytes;
260 program->shader.binary.elf_buffer = malloc(header->num_bytes);
261 if (!program->shader.binary.elf_buffer) {
262 FREE(program);
263 return NULL;
264 }
265 memcpy((void *)program->shader.binary.elf_buffer, code, header->num_bytes);
266
267 const amd_kernel_code_t *code_object =
268 si_compute_get_code_object(program, 0);
269 code_object_to_config(code_object, &program->shader.config);
270
271 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
272 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
273 fprintf(stderr, "LLVM failed to upload shader\n");
274 free((void *)program->shader.binary.elf_buffer);
275 FREE(program);
276 return NULL;
277 }
278 }
279
280 return program;
281 }
282
283 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
284 {
285 struct si_context *sctx = (struct si_context*)ctx;
286 struct si_compute *program = (struct si_compute*)state;
287 struct si_shader_selector *sel = &program->sel;
288
289 sctx->cs_shader_state.program = program;
290 if (!program)
291 return;
292
293 /* Wait because we need active slot usage masks. */
294 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
295 util_queue_fence_wait(&sel->ready);
296
297 si_set_active_descriptors(sctx,
298 SI_DESCS_FIRST_COMPUTE +
299 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
300 sel->active_const_and_shader_buffers);
301 si_set_active_descriptors(sctx,
302 SI_DESCS_FIRST_COMPUTE +
303 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
304 sel->active_samplers_and_images);
305 }
306
307 static void si_set_global_binding(
308 struct pipe_context *ctx, unsigned first, unsigned n,
309 struct pipe_resource **resources,
310 uint32_t **handles)
311 {
312 unsigned i;
313 struct si_context *sctx = (struct si_context*)ctx;
314 struct si_compute *program = sctx->cs_shader_state.program;
315
316 assert(first + n <= MAX_GLOBAL_BUFFERS);
317
318 if (!resources) {
319 for (i = 0; i < n; i++) {
320 pipe_resource_reference(&program->global_buffers[first + i], NULL);
321 }
322 return;
323 }
324
325 for (i = 0; i < n; i++) {
326 uint64_t va;
327 uint32_t offset;
328 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
329 va = si_resource(resources[i])->gpu_address;
330 offset = util_le32_to_cpu(*handles[i]);
331 va += offset;
332 va = util_cpu_to_le64(va);
333 memcpy(handles[i], &va, sizeof(va));
334 }
335 }
336
337 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
338 {
339 uint64_t bc_va;
340
341 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
342 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
343 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
344 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
345 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
346
347 if (sctx->chip_class >= GFX7) {
348 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
349 radeon_set_sh_reg_seq(cs,
350 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
351 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
352 S_00B858_SH1_CU_EN(0xffff));
353 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
354 S_00B858_SH1_CU_EN(0xffff));
355 }
356
357 if (sctx->chip_class >= GFX10)
358 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
359
360 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
361 * and is now per pipe, so it should be handled in the
362 * kernel if we want to use something other than the default value,
363 * which is now 0x22f.
364 */
365 if (sctx->chip_class <= GFX6) {
366 /* XXX: This should be:
367 * (number of compute units) * 4 * (waves per simd) - 1 */
368
369 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
370 0x190 /* Default value */);
371 }
372
373 /* Set the pointer to border colors. */
374 bc_va = sctx->border_color_buffer->gpu_address;
375
376 if (sctx->chip_class >= GFX7) {
377 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
378 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
379 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
380 } else {
381 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
382 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
383 bc_va >> 8);
384 }
385 }
386 }
387
388 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
389 struct si_shader *shader,
390 struct ac_shader_config *config)
391 {
392 uint64_t scratch_bo_size, scratch_needed;
393 scratch_bo_size = 0;
394 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
395 if (sctx->compute_scratch_buffer)
396 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
397
398 if (scratch_bo_size < scratch_needed) {
399 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
400
401 sctx->compute_scratch_buffer =
402 si_aligned_buffer_create(&sctx->screen->b,
403 SI_RESOURCE_FLAG_UNMAPPABLE,
404 PIPE_USAGE_DEFAULT,
405 scratch_needed, 256);
406
407 if (!sctx->compute_scratch_buffer)
408 return false;
409 }
410
411 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
412 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
413
414 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
415 return false;
416
417 si_resource_reference(&shader->scratch_bo,
418 sctx->compute_scratch_buffer);
419 }
420
421 return true;
422 }
423
424 static bool si_switch_compute_shader(struct si_context *sctx,
425 struct si_compute *program,
426 struct si_shader *shader,
427 const amd_kernel_code_t *code_object,
428 unsigned offset)
429 {
430 struct radeon_cmdbuf *cs = sctx->gfx_cs;
431 struct ac_shader_config inline_config = {0};
432 struct ac_shader_config *config;
433 uint64_t shader_va;
434
435 if (sctx->cs_shader_state.emitted_program == program &&
436 sctx->cs_shader_state.offset == offset)
437 return true;
438
439 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
440 config = &shader->config;
441 } else {
442 unsigned lds_blocks;
443
444 config = &inline_config;
445 code_object_to_config(code_object, config);
446
447 lds_blocks = config->lds_size;
448 /* XXX: We are over allocating LDS. For GFX6, the shader reports
449 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
450 * allocated in the shader and 4 bytes allocated by the state
451 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
452 */
453 if (sctx->chip_class <= GFX6) {
454 lds_blocks += align(program->local_size, 256) >> 8;
455 } else {
456 lds_blocks += align(program->local_size, 512) >> 9;
457 }
458
459 /* TODO: use si_multiwave_lds_size_workaround */
460 assert(lds_blocks <= 0xFF);
461
462 config->rsrc2 &= C_00B84C_LDS_SIZE;
463 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
464 }
465
466 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
467 return false;
468
469 if (shader->scratch_bo) {
470 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
471 "Total Scratch: %u bytes\n", sctx->scratch_waves,
472 config->scratch_bytes_per_wave,
473 config->scratch_bytes_per_wave *
474 sctx->scratch_waves);
475
476 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
477 shader->scratch_bo, RADEON_USAGE_READWRITE,
478 RADEON_PRIO_SCRATCH_BUFFER);
479 }
480
481 /* Prefetch the compute shader to TC L2.
482 *
483 * We should also prefetch graphics shaders if a compute dispatch was
484 * the last command, and the compute shader if a draw call was the last
485 * command. However, that would add more complexity and we're likely
486 * to get a shader state change in that case anyway.
487 */
488 if (sctx->chip_class >= GFX7) {
489 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
490 0, program->shader.bo->b.b.width0);
491 }
492
493 shader_va = shader->bo->gpu_address + offset;
494 if (program->use_code_object_v2) {
495 /* Shader code is placed after the amd_kernel_code_t
496 * struct. */
497 shader_va += sizeof(amd_kernel_code_t);
498 }
499
500 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
501 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
502
503 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
504 radeon_emit(cs, shader_va >> 8);
505 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
506
507 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
508 radeon_emit(cs, config->rsrc1);
509 radeon_emit(cs, config->rsrc2);
510
511 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
512 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
513
514 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
515 S_00B860_WAVES(sctx->scratch_waves)
516 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
517
518 sctx->cs_shader_state.emitted_program = program;
519 sctx->cs_shader_state.offset = offset;
520 sctx->cs_shader_state.uses_scratch =
521 config->scratch_bytes_per_wave != 0;
522
523 return true;
524 }
525
526 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
527 const amd_kernel_code_t *code_object,
528 unsigned user_sgpr)
529 {
530 struct radeon_cmdbuf *cs = sctx->gfx_cs;
531 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
532
533 unsigned max_private_element_size = AMD_HSA_BITS_GET(
534 code_object->code_properties,
535 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
536
537 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
538 uint32_t scratch_dword1 =
539 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
540 S_008F04_SWIZZLE_ENABLE(1);
541
542 /* Disable address clamping */
543 uint32_t scratch_dword2 = 0xffffffff;
544 uint32_t scratch_dword3 =
545 S_008F0C_INDEX_STRIDE(3) |
546 S_008F0C_ADD_TID_ENABLE(1);
547
548 if (sctx->chip_class >= GFX9) {
549 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
550 } else {
551 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
552
553 if (sctx->chip_class < GFX8) {
554 /* BUF_DATA_FORMAT is ignored, but it cannot be
555 * BUF_DATA_FORMAT_INVALID. */
556 scratch_dword3 |=
557 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
558 }
559 }
560
561 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
562 (user_sgpr * 4), 4);
563 radeon_emit(cs, scratch_dword0);
564 radeon_emit(cs, scratch_dword1);
565 radeon_emit(cs, scratch_dword2);
566 radeon_emit(cs, scratch_dword3);
567 }
568
569 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
570 const amd_kernel_code_t *code_object,
571 const struct pipe_grid_info *info,
572 uint64_t kernel_args_va)
573 {
574 struct si_compute *program = sctx->cs_shader_state.program;
575 struct radeon_cmdbuf *cs = sctx->gfx_cs;
576
577 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
578 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
579 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
580 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
581 };
582
583 unsigned i, user_sgpr = 0;
584 if (AMD_HSA_BITS_GET(code_object->code_properties,
585 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
586 if (code_object->workitem_private_segment_byte_size > 0) {
587 setup_scratch_rsrc_user_sgprs(sctx, code_object,
588 user_sgpr);
589 }
590 user_sgpr += 4;
591 }
592
593 if (AMD_HSA_BITS_GET(code_object->code_properties,
594 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
595 struct dispatch_packet dispatch;
596 unsigned dispatch_offset;
597 struct si_resource *dispatch_buf = NULL;
598 uint64_t dispatch_va;
599
600 /* Upload dispatch ptr */
601 memset(&dispatch, 0, sizeof(dispatch));
602
603 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
604 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
605 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
606
607 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
608 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
609 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
610
611 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
612 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
613
614 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
615
616 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
617 256, &dispatch, &dispatch_offset,
618 (struct pipe_resource**)&dispatch_buf);
619
620 if (!dispatch_buf) {
621 fprintf(stderr, "Error: Failed to allocate dispatch "
622 "packet.");
623 }
624 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
625 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
626
627 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
628
629 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
630 (user_sgpr * 4), 2);
631 radeon_emit(cs, dispatch_va);
632 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
633 S_008F04_STRIDE(0));
634
635 si_resource_reference(&dispatch_buf, NULL);
636 user_sgpr += 2;
637 }
638
639 if (AMD_HSA_BITS_GET(code_object->code_properties,
640 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
641 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
642 (user_sgpr * 4), 2);
643 radeon_emit(cs, kernel_args_va);
644 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
645 S_008F04_STRIDE(0));
646 user_sgpr += 2;
647 }
648
649 for (i = 0; i < 3 && user_sgpr < 16; i++) {
650 if (code_object->code_properties & workgroup_count_masks[i]) {
651 radeon_set_sh_reg_seq(cs,
652 R_00B900_COMPUTE_USER_DATA_0 +
653 (user_sgpr * 4), 1);
654 radeon_emit(cs, info->grid[i]);
655 user_sgpr += 1;
656 }
657 }
658 }
659
660 static bool si_upload_compute_input(struct si_context *sctx,
661 const amd_kernel_code_t *code_object,
662 const struct pipe_grid_info *info)
663 {
664 struct radeon_cmdbuf *cs = sctx->gfx_cs;
665 struct si_compute *program = sctx->cs_shader_state.program;
666 struct si_resource *input_buffer = NULL;
667 unsigned kernel_args_size;
668 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
669 uint32_t kernel_args_offset = 0;
670 uint32_t *kernel_args;
671 void *kernel_args_ptr;
672 uint64_t kernel_args_va;
673 unsigned i;
674
675 /* The extra num_work_size_bytes are for work group / work item size information */
676 kernel_args_size = program->input_size + num_work_size_bytes;
677
678 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
679 sctx->screen->info.tcc_cache_line_size,
680 &kernel_args_offset,
681 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
682
683 if (unlikely(!kernel_args_ptr))
684 return false;
685
686 kernel_args = (uint32_t*)kernel_args_ptr;
687 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
688
689 if (!code_object) {
690 for (i = 0; i < 3; i++) {
691 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
692 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
693 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
694 }
695 }
696
697 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
698 program->input_size);
699
700
701 for (i = 0; i < (kernel_args_size / 4); i++) {
702 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
703 kernel_args[i]);
704 }
705
706
707 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
708 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
709
710 if (code_object) {
711 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
712 } else {
713 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
714 radeon_emit(cs, kernel_args_va);
715 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
716 S_008F04_STRIDE(0));
717 }
718
719 si_resource_reference(&input_buffer, NULL);
720
721 return true;
722 }
723
724 static void si_setup_tgsi_user_data(struct si_context *sctx,
725 const struct pipe_grid_info *info)
726 {
727 struct si_compute *program = sctx->cs_shader_state.program;
728 struct si_shader_selector *sel = &program->sel;
729 struct radeon_cmdbuf *cs = sctx->gfx_cs;
730 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
731 4 * SI_NUM_RESOURCE_SGPRS;
732 unsigned block_size_reg = grid_size_reg +
733 /* 12 bytes = 3 dwords. */
734 12 * sel->info.uses_grid_size;
735 unsigned cs_user_data_reg = block_size_reg +
736 12 * program->reads_variable_block_size;
737
738 if (info->indirect) {
739 if (sel->info.uses_grid_size) {
740 for (unsigned i = 0; i < 3; ++i) {
741 si_cp_copy_data(sctx, sctx->gfx_cs,
742 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
743 COPY_DATA_SRC_MEM, si_resource(info->indirect),
744 info->indirect_offset + 4 * i);
745 }
746 }
747 } else {
748 if (sel->info.uses_grid_size) {
749 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
750 radeon_emit(cs, info->grid[0]);
751 radeon_emit(cs, info->grid[1]);
752 radeon_emit(cs, info->grid[2]);
753 }
754 if (program->reads_variable_block_size) {
755 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
756 radeon_emit(cs, info->block[0]);
757 radeon_emit(cs, info->block[1]);
758 radeon_emit(cs, info->block[2]);
759 }
760 }
761
762 if (program->num_cs_user_data_dwords) {
763 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
764 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
765 }
766 }
767
768 static void si_emit_dispatch_packets(struct si_context *sctx,
769 const struct pipe_grid_info *info)
770 {
771 struct si_screen *sscreen = sctx->screen;
772 struct radeon_cmdbuf *cs = sctx->gfx_cs;
773 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
774 unsigned threads_per_threadgroup =
775 info->block[0] * info->block[1] * info->block[2];
776 unsigned waves_per_threadgroup =
777 DIV_ROUND_UP(threads_per_threadgroup, 64);
778 unsigned threadgroups_per_cu = 1;
779
780 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
781 threadgroups_per_cu = 2;
782
783 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
784 ac_get_compute_resource_limits(&sscreen->info,
785 waves_per_threadgroup,
786 sctx->cs_max_waves_per_sh,
787 threadgroups_per_cu));
788
789 unsigned dispatch_initiator =
790 S_00B800_COMPUTE_SHADER_EN(1) |
791 S_00B800_FORCE_START_AT_000(1) |
792 /* If the KMD allows it (there is a KMD hw register for it),
793 * allow launching waves out-of-order. (same as Vulkan) */
794 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7);
795
796 const uint *last_block = info->last_block;
797 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
798
799 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
800
801 if (partial_block_en) {
802 unsigned partial[3];
803
804 /* If no partial_block, these should be an entire block size, not 0. */
805 partial[0] = last_block[0] ? last_block[0] : info->block[0];
806 partial[1] = last_block[1] ? last_block[1] : info->block[1];
807 partial[2] = last_block[2] ? last_block[2] : info->block[2];
808
809 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
810 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
811 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
812 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
813 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
814 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
815
816 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
817 } else {
818 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
819 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
820 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
821 }
822
823 if (info->indirect) {
824 uint64_t base_va = si_resource(info->indirect)->gpu_address;
825
826 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
827 si_resource(info->indirect),
828 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
829
830 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
831 PKT3_SHADER_TYPE_S(1));
832 radeon_emit(cs, 1);
833 radeon_emit(cs, base_va);
834 radeon_emit(cs, base_va >> 32);
835
836 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
837 PKT3_SHADER_TYPE_S(1));
838 radeon_emit(cs, info->indirect_offset);
839 radeon_emit(cs, dispatch_initiator);
840 } else {
841 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
842 PKT3_SHADER_TYPE_S(1));
843 radeon_emit(cs, info->grid[0]);
844 radeon_emit(cs, info->grid[1]);
845 radeon_emit(cs, info->grid[2]);
846 radeon_emit(cs, dispatch_initiator);
847 }
848 }
849
850
851 static void si_launch_grid(
852 struct pipe_context *ctx, const struct pipe_grid_info *info)
853 {
854 struct si_context *sctx = (struct si_context*)ctx;
855 struct si_compute *program = sctx->cs_shader_state.program;
856 const amd_kernel_code_t *code_object =
857 si_compute_get_code_object(program, info->pc);
858 int i;
859 /* HW bug workaround when CS threadgroups > 256 threads and async
860 * compute isn't used, i.e. only one compute job can run at a time.
861 * If async compute is possible, the threadgroup size must be limited
862 * to 256 threads on all queues to avoid the bug.
863 * Only GFX6 and certain GFX7 chips are affected.
864 */
865 bool cs_regalloc_hang =
866 (sctx->chip_class == GFX6 ||
867 sctx->family == CHIP_BONAIRE ||
868 sctx->family == CHIP_KABINI) &&
869 info->block[0] * info->block[1] * info->block[2] > 256;
870
871 if (cs_regalloc_hang)
872 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
873 SI_CONTEXT_CS_PARTIAL_FLUSH;
874
875 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
876 program->shader.compilation_failed)
877 return;
878
879 if (sctx->has_graphics) {
880 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
881 si_update_fb_dirtiness_after_rendering(sctx);
882 sctx->last_num_draw_calls = sctx->num_draw_calls;
883 }
884
885 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
886 }
887
888 /* Add buffer sizes for memory checking in need_cs_space. */
889 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
890 /* TODO: add the scratch buffer */
891
892 if (info->indirect) {
893 si_context_add_resource_size(sctx, info->indirect);
894
895 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
896 if (sctx->chip_class <= GFX8 &&
897 si_resource(info->indirect)->TC_L2_dirty) {
898 sctx->flags |= SI_CONTEXT_WB_L2;
899 si_resource(info->indirect)->TC_L2_dirty = false;
900 }
901 }
902
903 si_need_gfx_cs_space(sctx);
904
905 if (sctx->bo_list_add_all_compute_resources)
906 si_compute_resources_add_all_to_bo_list(sctx);
907
908 if (!sctx->cs_shader_state.initialized) {
909 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
910
911 sctx->cs_shader_state.emitted_program = NULL;
912 sctx->cs_shader_state.initialized = true;
913 }
914
915 if (sctx->flags)
916 sctx->emit_cache_flush(sctx);
917
918 if (!si_switch_compute_shader(sctx, program, &program->shader,
919 code_object, info->pc))
920 return;
921
922 si_upload_compute_shader_descriptors(sctx);
923 si_emit_compute_shader_pointers(sctx);
924
925 if (sctx->has_graphics &&
926 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
927 sctx->atoms.s.render_cond.emit(sctx);
928 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
929 }
930
931 if ((program->input_size ||
932 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
933 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
934 return;
935 }
936
937 /* Global buffers */
938 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
939 struct si_resource *buffer =
940 si_resource(program->global_buffers[i]);
941 if (!buffer) {
942 continue;
943 }
944 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
945 RADEON_USAGE_READWRITE,
946 RADEON_PRIO_COMPUTE_GLOBAL);
947 }
948
949 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
950 si_setup_tgsi_user_data(sctx, info);
951
952 si_emit_dispatch_packets(sctx, info);
953
954 if (unlikely(sctx->current_saved_cs)) {
955 si_trace_emit(sctx);
956 si_log_compute_state(sctx, sctx->log);
957 }
958
959 sctx->compute_is_busy = true;
960 sctx->num_compute_calls++;
961 if (sctx->cs_shader_state.uses_scratch)
962 sctx->num_spill_compute_calls++;
963
964 if (cs_regalloc_hang)
965 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
966 }
967
968 void si_destroy_compute(struct si_compute *program)
969 {
970 struct si_shader_selector *sel = &program->sel;
971
972 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
973 util_queue_drop_job(&sel->screen->shader_compiler_queue,
974 &sel->ready);
975 util_queue_fence_destroy(&sel->ready);
976 }
977
978 si_shader_destroy(&program->shader);
979 FREE(program);
980 }
981
982 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
983 struct si_compute *program = (struct si_compute *)state;
984 struct si_context *sctx = (struct si_context*)ctx;
985
986 if (!state)
987 return;
988
989 if (program == sctx->cs_shader_state.program)
990 sctx->cs_shader_state.program = NULL;
991
992 if (program == sctx->cs_shader_state.emitted_program)
993 sctx->cs_shader_state.emitted_program = NULL;
994
995 ralloc_free(program->sel.nir);
996 si_compute_reference(&program, NULL);
997 }
998
999 static void si_set_compute_resources(struct pipe_context * ctx_,
1000 unsigned start, unsigned count,
1001 struct pipe_surface ** surfaces) { }
1002
1003 void si_init_compute_functions(struct si_context *sctx)
1004 {
1005 sctx->b.create_compute_state = si_create_compute_state;
1006 sctx->b.delete_compute_state = si_delete_compute_state;
1007 sctx->b.bind_compute_state = si_bind_compute_state;
1008 sctx->b.set_compute_resources = si_set_compute_resources;
1009 sctx->b.set_global_binding = si_set_global_binding;
1010 sctx->b.launch_grid = si_launch_grid;
1011 }