2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
27 #include "../radeon/r600_cs.h"
29 #include "si_shader.h"
32 #include "radeon_llvm_util.h"
34 #define MAX_GLOBAL_BUFFERS 20
36 struct si_pipe_compute
{
37 struct si_context
*ctx
;
40 unsigned private_size
;
43 struct si_pipe_shader
*kernels
;
44 unsigned num_user_sgprs
;
46 struct pipe_resource
*global_buffers
[MAX_GLOBAL_BUFFERS
];
48 LLVMContextRef llvm_ctx
;
51 static void *si_create_compute_state(
52 struct pipe_context
*ctx
,
53 const struct pipe_compute_state
*cso
)
55 struct si_context
*sctx
= (struct si_context
*)ctx
;
56 struct si_pipe_compute
*program
=
57 CALLOC_STRUCT(si_pipe_compute
);
58 const struct pipe_llvm_program_header
*header
;
59 const unsigned char *code
;
62 program
->llvm_ctx
= LLVMContextCreate();
65 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
68 program
->local_size
= cso
->req_local_mem
;
69 program
->private_size
= cso
->req_private_mem
;
70 program
->input_size
= cso
->req_input_mem
;
72 program
->num_kernels
= radeon_llvm_get_num_kernels(program
->llvm_ctx
, code
,
74 program
->kernels
= CALLOC(sizeof(struct si_pipe_shader
),
75 program
->num_kernels
);
76 for (i
= 0; i
< program
->num_kernels
; i
++) {
77 LLVMModuleRef mod
= radeon_llvm_get_kernel_module(program
->llvm_ctx
, i
,
78 code
, header
->num_bytes
);
79 si_compile_llvm(sctx
, &program
->kernels
[i
], mod
);
80 LLVMDisposeModule(mod
);
86 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
88 struct si_context
*sctx
= (struct si_context
*)ctx
;
89 sctx
->cs_shader_state
.program
= (struct si_pipe_compute
*)state
;
92 static void si_set_global_binding(
93 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
94 struct pipe_resource
**resources
,
98 struct si_context
*sctx
= (struct si_context
*)ctx
;
99 struct si_pipe_compute
*program
= sctx
->cs_shader_state
.program
;
102 for (i
= first
; i
< first
+ n
; i
++) {
103 program
->global_buffers
[i
] = NULL
;
108 for (i
= first
; i
< first
+ n
; i
++) {
111 program
->global_buffers
[i
] = resources
[i
];
112 va
= r600_resource_va(ctx
->screen
, resources
[i
]);
113 offset
= util_le32_to_cpu(*handles
[i
]);
115 va
= util_cpu_to_le64(va
);
116 memcpy(handles
[i
], &va
, sizeof(va
));
120 static void si_launch_grid(
121 struct pipe_context
*ctx
,
122 const uint
*block_layout
, const uint
*grid_layout
,
123 uint32_t pc
, const void *input
)
125 struct si_context
*sctx
= (struct si_context
*)ctx
;
126 struct si_pipe_compute
*program
= sctx
->cs_shader_state
.program
;
127 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
128 struct r600_resource
*kernel_args_buffer
= NULL
;
129 unsigned kernel_args_size
;
130 unsigned num_work_size_bytes
= 36;
131 uint32_t kernel_args_offset
= 0;
132 uint32_t *kernel_args
;
133 uint64_t kernel_args_va
;
135 unsigned arg_user_sgpr_count
= 2;
137 struct si_pipe_shader
*shader
= &program
->kernels
[pc
];
140 pm4
->compute_pkt
= true;
141 si_cmd_context_control(pm4
);
143 si_pm4_cmd_begin(pm4
, PKT3_EVENT_WRITE
);
144 si_pm4_cmd_add(pm4
, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH
) |
147 si_pm4_cmd_end(pm4
, false);
149 si_pm4_inval_texture_cache(pm4
);
150 si_pm4_inval_shader_cache(pm4
);
151 si_cmd_surface_sync(pm4
, pm4
->cp_coher_cntl
);
153 /* Upload the kernel arguments */
155 /* The extra num_work_size_bytes are for work group / work item size information */
156 kernel_args_size
= program
->input_size
+ num_work_size_bytes
;
157 kernel_args
= MALLOC(kernel_args_size
);
158 for (i
= 0; i
< 3; i
++) {
159 kernel_args
[i
] = grid_layout
[i
];
160 kernel_args
[i
+ 3] = grid_layout
[i
] * block_layout
[i
];
161 kernel_args
[i
+ 6] = block_layout
[i
];
164 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), input
, program
->input_size
);
166 si_upload_const_buffer(sctx
, &kernel_args_buffer
, (uint8_t*)kernel_args
,
167 kernel_args_size
, &kernel_args_offset
);
168 kernel_args_va
= r600_resource_va(ctx
->screen
,
169 (struct pipe_resource
*)kernel_args_buffer
);
170 kernel_args_va
+= kernel_args_offset
;
172 si_pm4_add_bo(pm4
, kernel_args_buffer
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
174 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
, kernel_args_va
);
175 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) | S_008F04_STRIDE(0));
177 si_pm4_set_reg(pm4
, R_00B810_COMPUTE_START_X
, 0);
178 si_pm4_set_reg(pm4
, R_00B814_COMPUTE_START_Y
, 0);
179 si_pm4_set_reg(pm4
, R_00B818_COMPUTE_START_Z
, 0);
181 si_pm4_set_reg(pm4
, R_00B81C_COMPUTE_NUM_THREAD_X
,
182 S_00B81C_NUM_THREAD_FULL(block_layout
[0]));
183 si_pm4_set_reg(pm4
, R_00B820_COMPUTE_NUM_THREAD_Y
,
184 S_00B820_NUM_THREAD_FULL(block_layout
[1]));
185 si_pm4_set_reg(pm4
, R_00B824_COMPUTE_NUM_THREAD_Z
,
186 S_00B824_NUM_THREAD_FULL(block_layout
[2]));
189 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
190 struct r600_resource
*buffer
=
191 (struct r600_resource
*)program
->global_buffers
[i
];
195 si_pm4_add_bo(pm4
, buffer
, RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RESOURCE_RW
);
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
203 if (sctx
->b
.chip_class
<= SI
) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
207 si_pm4_set_reg(pm4
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
208 0x190 /* Default value */);
211 shader_va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
212 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
213 si_pm4_set_reg(pm4
, R_00B830_COMPUTE_PGM_LO
, (shader_va
>> 8) & 0xffffffff);
214 si_pm4_set_reg(pm4
, R_00B834_COMPUTE_PGM_HI
, shader_va
>> 40);
216 si_pm4_set_reg(pm4
, R_00B848_COMPUTE_PGM_RSRC1
,
217 /* We always use at least 3 VGPRS, these come from
219 * XXX: The compiler should account for this.
221 S_00B848_VGPRS((MAX2(3, shader
->num_vgprs
) - 1) / 4)
222 /* We always use at least 4 + arg_user_sgpr_count. The 4 extra
223 * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
224 * XXX: The compiler should account for this.
226 | S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count
,
227 shader
->num_sgprs
)) - 1) / 8))
230 lds_blocks
= shader
->lds_size
;
231 /* XXX: We are over allocating LDS. For SI, the shader reports LDS in
232 * blocks of 256 bytes, so if there are 4 bytes lds allocated in
233 * the shader and 4 bytes allocated by the state tracker, then
234 * we will set LDS_SIZE to 512 bytes rather than 256.
236 if (sctx
->b
.chip_class
<= SI
) {
237 lds_blocks
+= align(program
->local_size
, 256) >> 8;
239 lds_blocks
+= align(program
->local_size
, 512) >> 9;
242 assert(lds_blocks
<= 0xFF);
244 si_pm4_set_reg(pm4
, R_00B84C_COMPUTE_PGM_RSRC2
,
245 S_00B84C_SCRATCH_EN(0)
246 | S_00B84C_USER_SGPR(arg_user_sgpr_count
)
247 | S_00B84C_TGID_X_EN(1)
248 | S_00B84C_TGID_Y_EN(1)
249 | S_00B84C_TGID_Z_EN(1)
250 | S_00B84C_TG_SIZE_EN(1)
251 | S_00B84C_TIDIG_COMP_CNT(2)
252 | S_00B84C_LDS_SIZE(lds_blocks
)
253 | S_00B84C_EXCP_EN(0))
255 si_pm4_set_reg(pm4
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 0);
257 si_pm4_set_reg(pm4
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
,
258 S_00B858_SH0_CU_EN(0xffff /* Default value */)
259 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
262 si_pm4_set_reg(pm4
, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1
,
263 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
264 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
267 si_pm4_cmd_begin(pm4
, PKT3_DISPATCH_DIRECT
);
268 si_pm4_cmd_add(pm4
, grid_layout
[0]); /* Thread groups DIM_X */
269 si_pm4_cmd_add(pm4
, grid_layout
[1]); /* Thread groups DIM_Y */
270 si_pm4_cmd_add(pm4
, grid_layout
[2]); /* Thread gropus DIM_Z */
271 si_pm4_cmd_add(pm4
, 1); /* DISPATCH_INITIATOR */
272 si_pm4_cmd_end(pm4
, false);
274 si_pm4_cmd_begin(pm4
, PKT3_EVENT_WRITE
);
275 si_pm4_cmd_add(pm4
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(0x4)));
276 si_pm4_cmd_end(pm4
, false);
278 si_pm4_inval_texture_cache(pm4
);
279 si_pm4_inval_shader_cache(pm4
);
280 si_cmd_surface_sync(pm4
, pm4
->cp_coher_cntl
);
282 si_pm4_emit(sctx
, pm4
);
285 fprintf(stderr
, "cdw: %i\n", sctx
->cs
->cdw
);
286 for (i
= 0; i
< sctx
->cs
->cdw
; i
++) {
287 fprintf(stderr
, "%4i : 0x%08X\n", i
, sctx
->cs
->buf
[i
]);
296 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
297 struct si_pipe_compute
*program
= (struct si_pipe_compute
*)state
;
303 if (program
->kernels
) {
304 for (int i
= 0; i
< program
->num_kernels
; i
++){
305 if (program
->kernels
[i
].bo
){
306 si_pipe_shader_destroy(ctx
, &program
->kernels
[i
]);
310 FREE(program
->kernels
);
313 if (program
->llvm_ctx
){
314 LLVMContextDispose(program
->llvm_ctx
);
317 //And then free the program itself.
321 static void si_set_compute_resources(struct pipe_context
* ctx_
,
322 unsigned start
, unsigned count
,
323 struct pipe_surface
** surfaces
) { }
325 void si_init_compute_functions(struct si_context
*sctx
)
327 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
328 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
329 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
330 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
331 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
332 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
333 sctx
->b
.b
.launch_grid
= si_launch_grid
;