2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
26 #include "radeon/r600_pipe_common.h"
27 #include "radeon/radeon_elf_util.h"
28 #include "radeon/radeon_llvm_util.h"
30 #include "radeon/r600_cs.h"
32 #include "si_shader.h"
35 #define MAX_GLOBAL_BUFFERS 20
38 struct si_context
*ctx
;
41 unsigned private_size
;
43 struct si_shader shader
;
44 unsigned num_user_sgprs
;
46 struct r600_resource
*input_buffer
;
47 struct pipe_resource
*global_buffers
[MAX_GLOBAL_BUFFERS
];
49 #if HAVE_LLVM < 0x0306
51 struct si_shader
*kernels
;
52 LLVMContextRef llvm_ctx
;
56 static void init_scratch_buffer(struct si_context
*sctx
, struct si_compute
*program
)
58 unsigned scratch_bytes
= 0;
59 uint64_t scratch_buffer_va
;
62 /* Compute the scratch buffer size using the maximum number of waves.
63 * This way we don't need to recompute it for each kernel launch. */
64 unsigned scratch_waves
= 32 * sctx
->screen
->b
.info
.max_compute_units
;
65 for (i
= 0; i
< program
->shader
.binary
.global_symbol_count
; i
++) {
67 program
->shader
.binary
.global_symbol_offsets
[i
];
68 unsigned scratch_bytes_needed
;
70 si_shader_binary_read_config(&program
->shader
.binary
,
71 &program
->shader
.config
, offset
);
72 scratch_bytes_needed
= program
->shader
.config
.scratch_bytes_per_wave
;
73 scratch_bytes
= MAX2(scratch_bytes
, scratch_bytes_needed
);
76 if (scratch_bytes
== 0)
79 program
->shader
.scratch_bo
=
80 si_resource_create_custom(sctx
->b
.b
.screen
,
82 scratch_bytes
* scratch_waves
);
84 scratch_buffer_va
= program
->shader
.scratch_bo
->gpu_address
;
86 /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
87 * to the maximum bytes needed, so it can compute the stride
90 program
->shader
.config
.scratch_bytes_per_wave
= scratch_bytes
;
92 /* Patch the shader with the scratch buffer address. */
93 si_shader_apply_scratch_relocs(sctx
,
94 &program
->shader
, scratch_buffer_va
);
97 static void *si_create_compute_state(
98 struct pipe_context
*ctx
,
99 const struct pipe_compute_state
*cso
)
101 struct si_context
*sctx
= (struct si_context
*)ctx
;
102 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
103 const struct pipe_llvm_program_header
*header
;
107 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
110 program
->local_size
= cso
->req_local_mem
;
111 program
->private_size
= cso
->req_private_mem
;
112 program
->input_size
= cso
->req_input_mem
;
114 #if HAVE_LLVM < 0x0306
117 program
->llvm_ctx
= LLVMContextCreate();
118 program
->num_kernels
= radeon_llvm_get_num_kernels(program
->llvm_ctx
,
119 code
, header
->num_bytes
);
120 program
->kernels
= CALLOC(sizeof(struct si_shader
),
121 program
->num_kernels
);
122 for (i
= 0; i
< program
->num_kernels
; i
++) {
123 LLVMModuleRef mod
= radeon_llvm_get_kernel_module(program
->llvm_ctx
, i
,
124 code
, header
->num_bytes
);
125 si_compile_llvm(sctx
->screen
, &program
->kernels
[i
].binary
,
126 &program
->kernels
[i
].config
, sctx
->tm
,
127 mod
, &sctx
->b
.debug
, TGSI_PROCESSOR_COMPUTE
);
128 si_shader_binary_upload(sctx
->screen
, &program
->kernels
[i
]);
129 LLVMDisposeModule(mod
);
134 radeon_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
136 /* init_scratch_buffer patches the shader code with the scratch address,
137 * so we need to call it before si_shader_binary_read() which uploads
138 * the shader code to the GPU.
140 init_scratch_buffer(sctx
, program
);
141 si_shader_binary_read(&program
->shader
.binary
,
142 &program
->shader
.config
);
143 si_shader_dump(sctx
->screen
, &program
->shader
.binary
,
144 &program
->shader
.config
, &sctx
->b
.debug
,
145 TGSI_PROCESSOR_COMPUTE
);
146 si_shader_binary_upload(sctx
->screen
, &program
->shader
);
149 program
->input_buffer
= si_resource_create_custom(sctx
->b
.b
.screen
,
150 PIPE_USAGE_IMMUTABLE
, program
->input_size
);
155 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
157 struct si_context
*sctx
= (struct si_context
*)ctx
;
158 sctx
->cs_shader_state
.program
= (struct si_compute
*)state
;
161 static void si_set_global_binding(
162 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
163 struct pipe_resource
**resources
,
167 struct si_context
*sctx
= (struct si_context
*)ctx
;
168 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
171 for (i
= first
; i
< first
+ n
; i
++) {
172 pipe_resource_reference(&program
->global_buffers
[i
], NULL
);
177 for (i
= first
; i
< first
+ n
; i
++) {
180 pipe_resource_reference(&program
->global_buffers
[i
], resources
[i
]);
181 va
= r600_resource(resources
[i
])->gpu_address
;
182 offset
= util_le32_to_cpu(*handles
[i
]);
184 va
= util_cpu_to_le64(va
);
185 memcpy(handles
[i
], &va
, sizeof(va
));
190 * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
191 * /p block_layout is the number of threads in each work group.
192 * /p grid layout is the number of work groups.
194 static unsigned compute_num_waves_for_scratch(
195 const struct radeon_info
*info
,
196 const uint
*block_layout
,
197 const uint
*grid_layout
)
199 unsigned num_sh
= MAX2(info
->max_sh_per_se
, 1);
200 unsigned num_se
= MAX2(info
->max_se
, 1);
201 unsigned num_blocks
= 1;
202 unsigned threads_per_block
= 1;
203 unsigned waves_per_block
;
204 unsigned waves_per_sh
;
206 unsigned scratch_waves
;
209 for (i
= 0; i
< 3; i
++) {
210 threads_per_block
*= block_layout
[i
];
211 num_blocks
*= grid_layout
[i
];
214 waves_per_block
= align(threads_per_block
, 64) / 64;
215 waves
= waves_per_block
* num_blocks
;
216 waves_per_sh
= align(waves
, num_sh
* num_se
) / (num_sh
* num_se
);
217 scratch_waves
= waves_per_sh
* num_sh
* num_se
;
219 if (waves_per_block
> waves_per_sh
) {
220 scratch_waves
= waves_per_block
* num_sh
* num_se
;
223 return scratch_waves
;
226 static void si_launch_grid(
227 struct pipe_context
*ctx
,
228 const uint
*block_layout
, const uint
*grid_layout
,
229 uint32_t pc
, const void *input
)
231 struct si_context
*sctx
= (struct si_context
*)ctx
;
232 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
233 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
234 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
235 struct r600_resource
*input_buffer
= program
->input_buffer
;
236 unsigned kernel_args_size
;
237 unsigned num_work_size_bytes
= 36;
238 uint32_t kernel_args_offset
= 0;
239 uint32_t *kernel_args
;
240 uint64_t kernel_args_va
;
241 uint64_t scratch_buffer_va
= 0;
244 struct si_shader
*shader
= &program
->shader
;
246 unsigned num_waves_for_scratch
;
248 #if HAVE_LLVM < 0x0306
249 shader
= &program
->kernels
[pc
];
253 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0) | PKT3_SHADER_TYPE_S(1));
254 radeon_emit(cs
, 0x80000000);
255 radeon_emit(cs
, 0x80000000);
257 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
258 SI_CONTEXT_INV_GLOBAL_L2
|
259 SI_CONTEXT_INV_ICACHE
|
260 SI_CONTEXT_INV_SMEM_L1
|
261 SI_CONTEXT_FLUSH_WITH_INV_L2
|
262 SI_CONTEXT_FLAG_COMPUTE
;
263 si_emit_cache_flush(sctx
, NULL
);
265 pm4
->compute_pkt
= true;
267 #if HAVE_LLVM >= 0x0306
268 /* Read the config information */
269 si_shader_binary_read_config(&shader
->binary
, &shader
->config
, pc
);
272 /* Upload the kernel arguments */
274 /* The extra num_work_size_bytes are for work group / work item size information */
275 kernel_args_size
= program
->input_size
+ num_work_size_bytes
+ 8 /* For scratch va */;
277 kernel_args
= sctx
->b
.ws
->buffer_map(input_buffer
->buf
,
278 sctx
->b
.gfx
.cs
, PIPE_TRANSFER_WRITE
);
279 for (i
= 0; i
< 3; i
++) {
280 kernel_args
[i
] = grid_layout
[i
];
281 kernel_args
[i
+ 3] = grid_layout
[i
] * block_layout
[i
];
282 kernel_args
[i
+ 6] = block_layout
[i
];
285 num_waves_for_scratch
= compute_num_waves_for_scratch(
286 &sctx
->screen
->b
.info
, block_layout
, grid_layout
);
288 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), input
, program
->input_size
);
290 if (shader
->config
.scratch_bytes_per_wave
> 0) {
292 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
293 "Total Scratch: %u bytes\n", num_waves_for_scratch
,
294 shader
->config
.scratch_bytes_per_wave
,
295 shader
->config
.scratch_bytes_per_wave
*
296 num_waves_for_scratch
);
298 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
300 RADEON_USAGE_READWRITE
,
301 RADEON_PRIO_SCRATCH_BUFFER
);
303 scratch_buffer_va
= shader
->scratch_bo
->gpu_address
;
306 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
307 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
311 kernel_args_va
= input_buffer
->gpu_address
;
312 kernel_args_va
+= kernel_args_offset
;
314 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, input_buffer
,
315 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
317 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
, kernel_args_va
);
318 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) | S_008F04_STRIDE(0));
319 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 8, scratch_buffer_va
);
320 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 12,
321 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va
>> 32)
322 | S_008F04_STRIDE(shader
->config
.scratch_bytes_per_wave
/ 64));
324 si_pm4_set_reg(pm4
, R_00B810_COMPUTE_START_X
, 0);
325 si_pm4_set_reg(pm4
, R_00B814_COMPUTE_START_Y
, 0);
326 si_pm4_set_reg(pm4
, R_00B818_COMPUTE_START_Z
, 0);
328 si_pm4_set_reg(pm4
, R_00B81C_COMPUTE_NUM_THREAD_X
,
329 S_00B81C_NUM_THREAD_FULL(block_layout
[0]));
330 si_pm4_set_reg(pm4
, R_00B820_COMPUTE_NUM_THREAD_Y
,
331 S_00B820_NUM_THREAD_FULL(block_layout
[1]));
332 si_pm4_set_reg(pm4
, R_00B824_COMPUTE_NUM_THREAD_Z
,
333 S_00B824_NUM_THREAD_FULL(block_layout
[2]));
336 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
337 struct r600_resource
*buffer
=
338 (struct r600_resource
*)program
->global_buffers
[i
];
342 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, buffer
,
343 RADEON_USAGE_READWRITE
,
344 RADEON_PRIO_COMPUTE_GLOBAL
);
347 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
348 * and is now per pipe, so it should be handled in the
349 * kernel if we want to use something other than the default value,
350 * which is now 0x22f.
352 if (sctx
->b
.chip_class
<= SI
) {
353 /* XXX: This should be:
354 * (number of compute units) * 4 * (waves per simd) - 1 */
356 si_pm4_set_reg(pm4
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
357 0x190 /* Default value */);
360 shader_va
= shader
->bo
->gpu_address
;
362 #if HAVE_LLVM >= 0x0306
365 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, shader
->bo
,
366 RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
367 si_pm4_set_reg(pm4
, R_00B830_COMPUTE_PGM_LO
, shader_va
>> 8);
368 si_pm4_set_reg(pm4
, R_00B834_COMPUTE_PGM_HI
, shader_va
>> 40);
370 si_pm4_set_reg(pm4
, R_00B848_COMPUTE_PGM_RSRC1
, shader
->config
.rsrc1
);
372 lds_blocks
= shader
->config
.lds_size
;
373 /* XXX: We are over allocating LDS. For SI, the shader reports LDS in
374 * blocks of 256 bytes, so if there are 4 bytes lds allocated in
375 * the shader and 4 bytes allocated by the state tracker, then
376 * we will set LDS_SIZE to 512 bytes rather than 256.
378 if (sctx
->b
.chip_class
<= SI
) {
379 lds_blocks
+= align(program
->local_size
, 256) >> 8;
381 lds_blocks
+= align(program
->local_size
, 512) >> 9;
384 assert(lds_blocks
<= 0xFF);
386 shader
->config
.rsrc2
&= C_00B84C_LDS_SIZE
;
387 shader
->config
.rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
389 si_pm4_set_reg(pm4
, R_00B84C_COMPUTE_PGM_RSRC2
, shader
->config
.rsrc2
);
390 si_pm4_set_reg(pm4
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 0);
392 si_pm4_set_reg(pm4
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
,
393 S_00B858_SH0_CU_EN(0xffff /* Default value */)
394 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
397 si_pm4_set_reg(pm4
, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1
,
398 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
399 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
402 num_waves_for_scratch
=
403 MIN2(num_waves_for_scratch
,
404 32 * sctx
->screen
->b
.info
.max_compute_units
);
405 si_pm4_set_reg(pm4
, R_00B860_COMPUTE_TMPRING_SIZE
,
406 /* The maximum value for WAVES is 32 * num CU.
407 * If you program this value incorrectly, the GPU will hang if
408 * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
410 S_00B860_WAVES(num_waves_for_scratch
)
411 | S_00B860_WAVESIZE(shader
->config
.scratch_bytes_per_wave
>> 10))
414 si_pm4_cmd_begin(pm4
, PKT3_DISPATCH_DIRECT
);
415 si_pm4_cmd_add(pm4
, grid_layout
[0]); /* Thread groups DIM_X */
416 si_pm4_cmd_add(pm4
, grid_layout
[1]); /* Thread groups DIM_Y */
417 si_pm4_cmd_add(pm4
, grid_layout
[2]); /* Thread gropus DIM_Z */
418 si_pm4_cmd_add(pm4
, 1); /* DISPATCH_INITIATOR */
419 si_pm4_cmd_end(pm4
, false);
421 si_pm4_emit(sctx
, pm4
);
424 fprintf(stderr
, "cdw: %i\n", sctx
->cs
->cdw
);
425 for (i
= 0; i
< sctx
->cs
->cdw
; i
++) {
426 fprintf(stderr
, "%4i : 0x%08X\n", i
, sctx
->cs
->buf
[i
]);
430 si_pm4_free_state(sctx
, pm4
, ~0);
432 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
|
433 SI_CONTEXT_INV_VMEM_L1
|
434 SI_CONTEXT_INV_GLOBAL_L2
|
435 SI_CONTEXT_INV_ICACHE
|
436 SI_CONTEXT_INV_SMEM_L1
|
437 SI_CONTEXT_FLAG_COMPUTE
;
438 si_emit_cache_flush(sctx
, NULL
);
442 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
443 struct si_compute
*program
= (struct si_compute
*)state
;
449 #if HAVE_LLVM < 0x0306
450 if (program
->kernels
) {
451 for (int i
= 0; i
< program
->num_kernels
; i
++){
452 if (program
->kernels
[i
].bo
){
453 si_shader_destroy(&program
->kernels
[i
]);
456 FREE(program
->kernels
);
459 if (program
->llvm_ctx
){
460 LLVMContextDispose(program
->llvm_ctx
);
463 FREE(program
->shader
.binary
.config
);
464 FREE(program
->shader
.binary
.rodata
);
465 FREE(program
->shader
.binary
.global_symbol_offsets
);
466 si_shader_destroy(&program
->shader
);
469 pipe_resource_reference(
470 (struct pipe_resource
**)&program
->input_buffer
, NULL
);
475 static void si_set_compute_resources(struct pipe_context
* ctx_
,
476 unsigned start
, unsigned count
,
477 struct pipe_surface
** surfaces
) { }
479 void si_init_compute_functions(struct si_context
*sctx
)
481 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
482 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
483 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
484 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
485 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
486 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
487 sctx
->b
.b
.launch_grid
= si_launch_grid
;