src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_memory.h"
  26
  27 #include "../radeon/r600_cs.h"
  28 #include "si_pipe.h"
  29 #include "si_shader.h"
  30 #include "sid.h"
  31
  32 #include "radeon_llvm_util.h"
  33
  34 #define MAX_GLOBAL_BUFFERS 20
  35 #if HAVE_LLVM < 0x0305
  36 #define NUM_USER_SGPRS 2
  37 #else
  38 #define NUM_USER_SGPRS 4
  39 #endif
  40
  41 struct si_pipe_compute {
  42         struct si_context *ctx;
  43
  44         unsigned local_size;
  45         unsigned private_size;
  46         unsigned input_size;
  47         unsigned num_kernels;
  48         struct si_pipe_shader *kernels;
  49         unsigned num_user_sgprs;
  50
  51         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  52
  53         LLVMContextRef llvm_ctx;
  54 };
  55
  56 static void *si_create_compute_state(
  57         struct pipe_context *ctx,
  58         const struct pipe_compute_state *cso)
  59 {
  60         struct si_context *sctx = (struct si_context *)ctx;
  61         struct si_pipe_compute *program =
  62                                         CALLOC_STRUCT(si_pipe_compute);
  63         const struct pipe_llvm_program_header *header;
  64         const unsigned char *code;
  65         unsigned i;
  66
  67         program->llvm_ctx = LLVMContextCreate();
  68
  69         header = cso->prog;
  70         code = cso->prog + sizeof(struct pipe_llvm_program_header);
  71
  72         program->ctx = sctx;
  73         program->local_size = cso->req_local_mem;
  74         program->private_size = cso->req_private_mem;
  75         program->input_size = cso->req_input_mem;
  76
  77         program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx, code,
  78                                                         header->num_bytes);
  79         program->kernels = CALLOC(sizeof(struct si_pipe_shader),
  80                                                         program->num_kernels);
  81         for (i = 0; i < program->num_kernels; i++) {
  82                 LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
  83                                                         code, header->num_bytes);
  84                 si_compile_llvm(sctx, &program->kernels[i], mod);
  85                 LLVMDisposeModule(mod);
  86         }
  87
  88         return program;
  89 }
  90
  91 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
  92 {
  93         struct si_context *sctx = (struct si_context*)ctx;
  94         sctx->cs_shader_state.program = (struct si_pipe_compute*)state;
  95 }
  96
  97 static void si_set_global_binding(
  98         struct pipe_context *ctx, unsigned first, unsigned n,
  99         struct pipe_resource **resources,
 100         uint32_t **handles)
 101 {
 102         unsigned i;
 103         struct si_context *sctx = (struct si_context*)ctx;
 104         struct si_pipe_compute *program = sctx->cs_shader_state.program;
 105
 106         if (!resources) {
 107                 for (i = first; i < first + n; i++) {
 108                         pipe_resource_reference(&program->global_buffers[i], NULL);
 109                 }
 110                 return;
 111         }
 112
 113         for (i = first; i < first + n; i++) {
 114                 uint64_t va;
 115                 uint32_t offset;
 116                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 117                 va = r600_resource(resources[i])->gpu_address;
 118                 offset = util_le32_to_cpu(*handles[i]);
 119                 va += offset;
 120                 va = util_cpu_to_le64(va);
 121                 memcpy(handles[i], &va, sizeof(va));
 122         }
 123 }
 124
 125 /**
 126  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 127  * /p block_layout is the number of threads in each work group.
 128  * /p grid layout is the number of work groups.
 129  */
 130 static unsigned compute_num_waves_for_scratch(
 131                 const struct radeon_info *info,
 132                 const uint *block_layout,
 133                 const uint *grid_layout)
 134 {
 135         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 136         unsigned num_se = MAX2(info->max_se, 1);
 137         unsigned num_blocks = 1;
 138         unsigned threads_per_block = 1;
 139         unsigned waves_per_block;
 140         unsigned waves_per_sh;
 141         unsigned waves;
 142         unsigned scratch_waves;
 143         unsigned i;
 144
 145         for (i = 0; i < 3; i++) {
 146                 threads_per_block *= block_layout[i];
 147                 num_blocks *= grid_layout[i];
 148         }
 149
 150         waves_per_block = align(threads_per_block, 64) / 64;
 151         waves = waves_per_block * num_blocks;
 152         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 153         scratch_waves = waves_per_sh * num_sh * num_se;
 154
 155         if (waves_per_block > waves_per_sh) {
 156                 scratch_waves = waves_per_block * num_sh * num_se;
 157         }
 158
 159         return scratch_waves;
 160 }
 161
 162 static void si_launch_grid(
 163                 struct pipe_context *ctx,
 164                 const uint *block_layout, const uint *grid_layout,
 165                 uint32_t pc, const void *input)
 166 {
 167         struct si_context *sctx = (struct si_context*)ctx;
 168         struct si_pipe_compute *program = sctx->cs_shader_state.program;
 169         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 170         struct r600_resource *kernel_args_buffer = NULL;
 171         unsigned kernel_args_size;
 172         unsigned num_work_size_bytes = 36;
 173         uint32_t kernel_args_offset = 0;
 174         uint32_t *kernel_args;
 175         uint64_t kernel_args_va;
 176         uint64_t scratch_buffer_va = 0;
 177         uint64_t shader_va;
 178         unsigned arg_user_sgpr_count = NUM_USER_SGPRS;
 179         unsigned i;
 180         struct si_pipe_shader *shader = &program->kernels[pc];
 181         unsigned lds_blocks;
 182         unsigned num_waves_for_scratch;
 183
 184         pm4->compute_pkt = true;
 185         si_cmd_context_control(pm4);
 186
 187         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 188         si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
 189                             EVENT_INDEX(0x7) |
 190                             EVENT_WRITE_INV_L2);
 191         si_pm4_cmd_end(pm4, false);
 192
 193         si_pm4_inval_texture_cache(pm4);
 194         si_pm4_inval_shader_cache(pm4);
 195         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 196
 197         /* Upload the kernel arguments */
 198
 199         /* The extra num_work_size_bytes are for work group / work item size information */
 200         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 201
 202         kernel_args = MALLOC(kernel_args_size);
 203         for (i = 0; i < 3; i++) {
 204                 kernel_args[i] = grid_layout[i];
 205                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 206                 kernel_args[i + 6] = block_layout[i];
 207         }
 208
 209         num_waves_for_scratch = compute_num_waves_for_scratch(
 210                 &sctx->screen->b.info, block_layout, grid_layout);
 211
 212         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 213
 214         if (shader->scratch_bytes_per_wave > 0) {
 215                 unsigned scratch_bytes = shader->scratch_bytes_per_wave *
 216                                                 num_waves_for_scratch;
 217
 218                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 219                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 220                             shader->scratch_bytes_per_wave, scratch_bytes);
 221                 if (!shader->scratch_bo) {
 222                         shader->scratch_bo = (struct r600_resource*)
 223                                 si_resource_create_custom(sctx->b.b.screen,
 224                                 PIPE_USAGE_DEFAULT, scratch_bytes);
 225                 }
 226                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 227                 si_pm4_add_bo(pm4, shader->scratch_bo,
 228                                 RADEON_USAGE_READWRITE,
 229                                 RADEON_PRIO_SHADER_RESOURCE_RW);
 230
 231         }
 232
 233         for (i = 0; i < (kernel_args_size / 4); i++) {
 234                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 235                         kernel_args[i]);
 236         }
 237
 238         si_upload_const_buffer(sctx, &kernel_args_buffer, (uint8_t*)kernel_args,
 239                                         kernel_args_size, &kernel_args_offset);
 240         kernel_args_va = kernel_args_buffer->gpu_address;
 241         kernel_args_va += kernel_args_offset;
 242
 243         si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 244
 245         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 246         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 247         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 248         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 249                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 250                 |  S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64));
 251
 252         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 253         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 254         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 255
 256         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 257                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 258         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 259                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 260         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 261                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 262
 263         /* Global buffers */
 264         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 265                 struct r600_resource *buffer =
 266                                 (struct r600_resource*)program->global_buffers[i];
 267                 if (!buffer) {
 268                         continue;
 269                 }
 270                 si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
 271         }
 272
 273         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 274          * and is now per pipe, so it should be handled in the
 275          * kernel if we want to use something other than the default value,
 276          * which is now 0x22f.
 277          */
 278         if (sctx->b.chip_class <= SI) {
 279                 /* XXX: This should be:
 280                  * (number of compute units) * 4 * (waves per simd) - 1 */
 281
 282                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 283                                                 0x190 /* Default value */);
 284         }
 285
 286         shader_va = shader->bo->gpu_address;
 287         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 288         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 289         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 290
 291         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 292                 /* We always use at least 3 VGPRS, these come from
 293                  * TIDIG_COMP_CNT.
 294                  * XXX: The compiler should account for this.
 295                  */
 296                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 297                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 298                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 299                  * XXX: The compiler should account for this.
 300                  */
 301                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 302                                         shader->num_sgprs)) - 1) / 8))
 303                 ;
 304
 305         lds_blocks = shader->lds_size;
 306         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 307          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 308          * the shader and 4 bytes allocated by the state tracker, then
 309          * we will set LDS_SIZE to 512 bytes rather than 256.
 310          */
 311         if (sctx->b.chip_class <= SI) {
 312                 lds_blocks += align(program->local_size, 256) >> 8;
 313         } else {
 314                 lds_blocks += align(program->local_size, 512) >> 9;
 315         }
 316
 317         assert(lds_blocks <= 0xFF);
 318
 319         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 320                 S_00B84C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0)
 321                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 322                 | S_00B84C_TGID_X_EN(1)
 323                 | S_00B84C_TGID_Y_EN(1)
 324                 | S_00B84C_TGID_Z_EN(1)
 325                 | S_00B84C_TG_SIZE_EN(1)
 326                 | S_00B84C_TIDIG_COMP_CNT(2)
 327                 | S_00B84C_LDS_SIZE(lds_blocks)
 328                 | S_00B84C_EXCP_EN(0))
 329                 ;
 330         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 331
 332         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 333                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 334                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 335                 ;
 336
 337         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 338                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 339                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 340                 ;
 341
 342         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 343                 /* The maximum value for WAVES is 32 * num CU.
 344                  * If you program this value incorrectly, the GPU will hang if
 345                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 346                  */
 347                 S_00B860_WAVES(num_waves_for_scratch)
 348                 | S_00B860_WAVESIZE(shader->scratch_bytes_per_wave >> 10))
 349                 ;
 350
 351         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 352         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 353         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 354         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 355         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 356         si_pm4_cmd_end(pm4, false);
 357
 358         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 359         si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
 360         si_pm4_cmd_end(pm4, false);
 361
 362         si_pm4_inval_texture_cache(pm4);
 363         si_pm4_inval_shader_cache(pm4);
 364         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 365
 366         si_pm4_emit(sctx, pm4);
 367
 368 #if 0
 369         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 370         for (i = 0; i < sctx->cs->cdw; i++) {
 371                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 372         }
 373 #endif
 374
 375         FREE(pm4);
 376         FREE(kernel_args);
 377 }
 378
 379
 380 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 381         struct si_pipe_compute *program = (struct si_pipe_compute *)state;
 382
 383         if (!state) {
 384                 return;
 385         }
 386
 387         if (program->kernels) {
 388                 for (int i = 0; i < program->num_kernels; i++){
 389                         if (program->kernels[i].bo){
 390                                 si_pipe_shader_destroy(ctx, &program->kernels[i]);
 391                         }
 392                 }
 393
 394                 FREE(program->kernels);
 395         }
 396
 397         if (program->llvm_ctx){
 398                 LLVMContextDispose(program->llvm_ctx);
 399         }
 400
 401         //And then free the program itself.
 402         FREE(program);
 403 }
 404
 405 static void si_set_compute_resources(struct pipe_context * ctx_,
 406                 unsigned start, unsigned count,
 407                 struct pipe_surface ** surfaces) { }
 408
 409 void si_init_compute_functions(struct si_context *sctx)
 410 {
 411         sctx->b.b.create_compute_state = si_create_compute_state;
 412         sctx->b.b.delete_compute_state = si_delete_compute_state;
 413         sctx->b.b.bind_compute_state = si_bind_compute_state;
 414 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 415         sctx->b.b.set_compute_resources = si_set_compute_resources;
 416         sctx->b.b.set_global_binding = si_set_global_binding;
 417         sctx->b.b.launch_grid = si_launch_grid;
 418 }