src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "tgsi/tgsi_parse.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "radeon/r600_pipe_common.h"
  29 #include "radeon/radeon_elf_util.h"
  30 #include "radeon/radeon_llvm_util.h"
  31
  32 #include "radeon/r600_cs.h"
  33 #include "si_pipe.h"
  34 #include "si_shader.h"
  35 #include "sid.h"
  36
  37 #define MAX_GLOBAL_BUFFERS 20
  38
  39 struct si_compute {
  40         unsigned ir_type;
  41         unsigned local_size;
  42         unsigned private_size;
  43         unsigned input_size;
  44         struct si_shader shader;
  45
  46         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  47 };
  48
  49 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
  50 {
  51         unsigned scratch_bytes = 0;
  52         uint64_t scratch_buffer_va;
  53         unsigned i;
  54
  55         /* Compute the scratch buffer size using the maximum number of waves.
  56          * This way we don't need to recompute it for each kernel launch. */
  57         unsigned scratch_waves = 32 * sctx->screen->b.info.num_good_compute_units;
  58         for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
  59                 unsigned offset =
  60                                 program->shader.binary.global_symbol_offsets[i];
  61                 unsigned scratch_bytes_needed;
  62
  63                 si_shader_binary_read_config(&program->shader.binary,
  64                                              &program->shader.config, offset);
  65                 scratch_bytes_needed = program->shader.config.scratch_bytes_per_wave;
  66                 scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
  67         }
  68
  69         if (scratch_bytes == 0)
  70                 return;
  71
  72         program->shader.scratch_bo =
  73                                 si_resource_create_custom(sctx->b.b.screen,
  74                                 PIPE_USAGE_DEFAULT,
  75                                 scratch_bytes * scratch_waves);
  76
  77         scratch_buffer_va = program->shader.scratch_bo->gpu_address;
  78
  79         /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
  80          * to the maximum bytes needed, so it can compute the stride
  81          * correctly.
  82          */
  83         program->shader.config.scratch_bytes_per_wave = scratch_bytes;
  84
  85         /* Patch the shader with the scratch buffer address. */
  86         si_shader_apply_scratch_relocs(sctx,
  87                                 &program->shader, scratch_buffer_va);
  88 }
  89
  90 static void *si_create_compute_state(
  91         struct pipe_context *ctx,
  92         const struct pipe_compute_state *cso)
  93 {
  94         struct si_context *sctx = (struct si_context *)ctx;
  95         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
  96         struct si_compute *program = CALLOC_STRUCT(si_compute);
  97         struct si_shader *shader = &program->shader;
  98
  99
 100         program->ir_type = cso->ir_type;
 101         program->local_size = cso->req_local_mem;
 102         program->private_size = cso->req_private_mem;
 103         program->input_size = cso->req_input_mem;
 104
 105
 106         if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 107                 struct si_shader_selector sel;
 108                 bool scratch_enabled;
 109
 110                 memset(&sel, 0, sizeof(sel));
 111
 112                 sel.tokens = tgsi_dup_tokens(cso->prog);
 113                 if (!sel.tokens) {
 114                         return NULL;
 115                 }
 116
 117                 tgsi_scan_shader(cso->prog, &sel.info);
 118                 sel.type = PIPE_SHADER_COMPUTE;
 119                 sel.local_size = cso->req_local_mem;
 120
 121                 p_atomic_inc(&sscreen->b.num_shaders_created);
 122
 123                 program->shader.selector = &sel;
 124
 125                 if (si_compile_tgsi_shader(sscreen, sctx->tm, &program->shader,
 126                                            true, &sctx->b.debug)) {
 127                         FREE(sel.tokens);
 128                         return NULL;
 129                 }
 130
 131                 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 132
 133                 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
 134                            S_00B84C_SCRATCH_EN(scratch_enabled) |
 135                            S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 136                            S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 137                            S_00B84C_LDS_SIZE(shader->config.lds_size);
 138
 139                 FREE(sel.tokens);
 140         } else {
 141                 const struct pipe_llvm_program_header *header;
 142                 const char *code;
 143                 header = cso->prog;
 144                 code = cso->prog + sizeof(struct pipe_llvm_program_header);
 145
 146                 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 147                 /* init_scratch_buffer patches the shader code with the scratch address,
 148                 * so we need to call it before si_shader_binary_read() which uploads
 149                 * the shader code to the GPU.
 150                 */
 151                 init_scratch_buffer(sctx, program);
 152                 si_shader_binary_read_config(&program->shader.binary,
 153                              &program->shader.config, 0);
 154         }
 155         si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 156                        TGSI_PROCESSOR_COMPUTE, stderr);
 157         si_shader_binary_upload(sctx->screen, &program->shader);
 158
 159         return program;
 160 }
 161
 162 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 163 {
 164         struct si_context *sctx = (struct si_context*)ctx;
 165         sctx->cs_shader_state.program = (struct si_compute*)state;
 166 }
 167
 168 static void si_set_global_binding(
 169         struct pipe_context *ctx, unsigned first, unsigned n,
 170         struct pipe_resource **resources,
 171         uint32_t **handles)
 172 {
 173         unsigned i;
 174         struct si_context *sctx = (struct si_context*)ctx;
 175         struct si_compute *program = sctx->cs_shader_state.program;
 176
 177         if (!resources) {
 178                 for (i = first; i < first + n; i++) {
 179                         pipe_resource_reference(&program->global_buffers[i], NULL);
 180                 }
 181                 return;
 182         }
 183
 184         for (i = first; i < first + n; i++) {
 185                 uint64_t va;
 186                 uint32_t offset;
 187                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 188                 va = r600_resource(resources[i])->gpu_address;
 189                 offset = util_le32_to_cpu(*handles[i]);
 190                 va += offset;
 191                 va = util_cpu_to_le64(va);
 192                 memcpy(handles[i], &va, sizeof(va));
 193         }
 194 }
 195
 196 /**
 197  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 198  * /p block_layout is the number of threads in each work group.
 199  * /p grid layout is the number of work groups.
 200  */
 201 static unsigned compute_num_waves_for_scratch(
 202                 const struct radeon_info *info,
 203                 const uint *block_layout,
 204                 const uint *grid_layout)
 205 {
 206         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 207         unsigned num_se = MAX2(info->max_se, 1);
 208         unsigned num_blocks = 1;
 209         unsigned threads_per_block = 1;
 210         unsigned waves_per_block;
 211         unsigned waves_per_sh;
 212         unsigned waves;
 213         unsigned scratch_waves;
 214         unsigned i;
 215
 216         for (i = 0; i < 3; i++) {
 217                 threads_per_block *= block_layout[i];
 218                 num_blocks *= grid_layout[i];
 219         }
 220
 221         waves_per_block = align(threads_per_block, 64) / 64;
 222         waves = waves_per_block * num_blocks;
 223         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 224         scratch_waves = waves_per_sh * num_sh * num_se;
 225
 226         if (waves_per_block > waves_per_sh) {
 227                 scratch_waves = waves_per_block * num_sh * num_se;
 228         }
 229
 230         return scratch_waves;
 231 }
 232
 233 static void si_initialize_compute(struct si_context *sctx)
 234 {
 235         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 236
 237         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
 238         radeon_emit(cs, 0);
 239         radeon_emit(cs, 0);
 240         radeon_emit(cs, 0);
 241
 242         radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
 243         radeon_emit(cs, 0);
 244         /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
 245         radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 246         radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
 247
 248         if (sctx->b.chip_class >= CIK) {
 249                 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 250                 radeon_set_sh_reg_seq(cs,
 251                                      R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 252                 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
 253                                 S_00B864_SH1_CU_EN(0xffff));
 254                 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
 255                                 S_00B868_SH1_CU_EN(0xffff));
 256         }
 257
 258         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 259          * and is now per pipe, so it should be handled in the
 260          * kernel if we want to use something other than the default value,
 261          * which is now 0x22f.
 262          */
 263         if (sctx->b.chip_class <= SI) {
 264                 /* XXX: This should be:
 265                  * (number of compute units) * 4 * (waves per simd) - 1 */
 266
 267                 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
 268                                   0x190 /* Default value */);
 269         }
 270
 271         sctx->cs_shader_state.initialized = true;
 272 }
 273
 274 static void si_upload_compute_input(struct si_context *sctx,
 275                                   const struct pipe_grid_info *info)
 276 {
 277         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 278         struct si_compute *program = sctx->cs_shader_state.program;
 279         struct r600_resource *input_buffer = NULL;
 280         unsigned kernel_args_size;
 281         unsigned num_work_size_bytes = 36;
 282         uint32_t kernel_args_offset = 0;
 283         uint32_t *kernel_args;
 284         void *kernel_args_ptr;
 285         uint64_t kernel_args_va;
 286         unsigned i;
 287
 288         /* The extra num_work_size_bytes are for work group / work item size information */
 289         kernel_args_size = program->input_size + num_work_size_bytes;
 290
 291         u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
 292                        &kernel_args_offset,
 293                        (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
 294
 295         kernel_args = (uint32_t*)kernel_args_ptr;
 296         for (i = 0; i < 3; i++) {
 297                 kernel_args[i] = info->grid[i];
 298                 kernel_args[i + 3] = info->grid[i] * info->block[i];
 299                 kernel_args[i + 6] = info->block[i];
 300         }
 301
 302         memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
 303                program->input_size);
 304
 305
 306         for (i = 0; i < (kernel_args_size / 4); i++) {
 307                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 308                         kernel_args[i]);
 309         }
 310
 311         kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 312
 313         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 314                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 315
 316         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
 317         radeon_emit(cs, kernel_args_va);
 318         radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
 319                         S_008F04_STRIDE(0));
 320
 321         pipe_resource_reference((struct pipe_resource**)&input_buffer, NULL);
 322 }
 323
 324 static void si_launch_grid(
 325                 struct pipe_context *ctx, const struct pipe_grid_info *info)
 326 {
 327         struct si_context *sctx = (struct si_context*)ctx;
 328         struct si_compute *program = sctx->cs_shader_state.program;
 329         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 330         uint64_t shader_va;
 331         unsigned i;
 332         struct si_shader *shader = &program->shader;
 333         unsigned lds_blocks;
 334         unsigned num_waves_for_scratch;
 335
 336         si_need_cs_space(sctx);
 337
 338         if (!sctx->cs_shader_state.initialized)
 339                 si_initialize_compute(sctx);
 340
 341         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
 342                          SI_CONTEXT_INV_GLOBAL_L2 |
 343                          SI_CONTEXT_INV_ICACHE |
 344                          SI_CONTEXT_INV_SMEM_L1 |
 345                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 346                          SI_CONTEXT_FLAG_COMPUTE;
 347         si_emit_cache_flush(sctx, NULL);
 348
 349         pm4->compute_pkt = true;
 350
 351         /* Read the config information */
 352         si_shader_binary_read_config(&shader->binary, &shader->config, info->pc);
 353
 354         if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
 355                 si_upload_compute_input(sctx, info);
 356
 357         num_waves_for_scratch = compute_num_waves_for_scratch(
 358                 &sctx->screen->b.info, info->block, info->grid);
 359
 360         if (shader->config.scratch_bytes_per_wave > 0) {
 361
 362                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 363                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 364                             shader->config.scratch_bytes_per_wave,
 365                             shader->config.scratch_bytes_per_wave *
 366                             num_waves_for_scratch);
 367
 368                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 369                                           shader->scratch_bo,
 370                                           RADEON_USAGE_READWRITE,
 371                                           RADEON_PRIO_SCRATCH_BUFFER);
 372         }
 373
 374         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 375                                 S_00B81C_NUM_THREAD_FULL(info->block[0]));
 376         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 377                                 S_00B820_NUM_THREAD_FULL(info->block[1]));
 378         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 379                                 S_00B824_NUM_THREAD_FULL(info->block[2]));
 380
 381         /* Global buffers */
 382         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 383                 struct r600_resource *buffer =
 384                                 (struct r600_resource*)program->global_buffers[i];
 385                 if (!buffer) {
 386                         continue;
 387                 }
 388                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 389                                           RADEON_USAGE_READWRITE,
 390                                           RADEON_PRIO_COMPUTE_GLOBAL);
 391         }
 392
 393         shader_va = shader->bo->gpu_address;
 394         shader_va += info->pc;
 395
 396         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 397                                   RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 398         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
 399         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 400
 401         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->config.rsrc1);
 402
 403         lds_blocks = shader->config.lds_size;
 404         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 405          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 406          * the shader and 4 bytes allocated by the state tracker, then
 407          * we will set LDS_SIZE to 512 bytes rather than 256.
 408          */
 409         if (sctx->b.chip_class <= SI) {
 410                 lds_blocks += align(program->local_size, 256) >> 8;
 411         } else {
 412                 lds_blocks += align(program->local_size, 512) >> 9;
 413         }
 414
 415         assert(lds_blocks <= 0xFF);
 416
 417         shader->config.rsrc2 &= C_00B84C_LDS_SIZE;
 418         shader->config.rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 419
 420         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->config.rsrc2);
 421
 422         num_waves_for_scratch =
 423                 MIN2(num_waves_for_scratch,
 424                      32 * sctx->screen->b.info.num_good_compute_units);
 425         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 426                 /* The maximum value for WAVES is 32 * num CU.
 427                  * If you program this value incorrectly, the GPU will hang if
 428                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 429                  */
 430                 S_00B860_WAVES(num_waves_for_scratch)
 431                 | S_00B860_WAVESIZE(shader->config.scratch_bytes_per_wave >> 10))
 432                 ;
 433
 434         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 435         si_pm4_cmd_add(pm4, info->grid[0]); /* Thread groups DIM_X */
 436         si_pm4_cmd_add(pm4, info->grid[1]); /* Thread groups DIM_Y */
 437         si_pm4_cmd_add(pm4, info->grid[2]); /* Thread gropus DIM_Z */
 438         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 439         si_pm4_cmd_end(pm4, false);
 440
 441         si_pm4_emit(sctx, pm4);
 442
 443 #if 0
 444         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 445         for (i = 0; i < sctx->cs->cdw; i++) {
 446                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 447         }
 448 #endif
 449
 450         si_pm4_free_state(sctx, pm4, ~0);
 451
 452         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 453                          SI_CONTEXT_INV_VMEM_L1 |
 454                          SI_CONTEXT_INV_GLOBAL_L2 |
 455                          SI_CONTEXT_INV_ICACHE |
 456                          SI_CONTEXT_INV_SMEM_L1 |
 457                          SI_CONTEXT_FLAG_COMPUTE;
 458         si_emit_cache_flush(sctx, NULL);
 459 }
 460
 461
 462 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 463         struct si_compute *program = (struct si_compute *)state;
 464
 465         if (!state) {
 466                 return;
 467         }
 468
 469         si_shader_destroy(&program->shader);
 470         FREE(program);
 471 }
 472
 473 static void si_set_compute_resources(struct pipe_context * ctx_,
 474                 unsigned start, unsigned count,
 475                 struct pipe_surface ** surfaces) { }
 476
 477 void si_init_compute_functions(struct si_context *sctx)
 478 {
 479         sctx->b.b.create_compute_state = si_create_compute_state;
 480         sctx->b.b.delete_compute_state = si_delete_compute_state;
 481         sctx->b.b.bind_compute_state = si_bind_compute_state;
 482 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 483         sctx->b.b.set_compute_resources = si_set_compute_resources;
 484         sctx->b.b.set_global_binding = si_set_global_binding;
 485         sctx->b.b.launch_grid = si_launch_grid;
 486 }