src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "tgsi/tgsi_parse.h"
  26 #include "util/u_memory.h"
  27 #include "radeon/r600_pipe_common.h"
  28 #include "radeon/radeon_elf_util.h"
  29 #include "radeon/radeon_llvm_util.h"
  30
  31 #include "radeon/r600_cs.h"
  32 #include "si_pipe.h"
  33 #include "si_shader.h"
  34 #include "sid.h"
  35
  36 #define MAX_GLOBAL_BUFFERS 20
  37
  38 struct si_compute {
  39         unsigned ir_type;
  40         unsigned local_size;
  41         unsigned private_size;
  42         unsigned input_size;
  43         struct si_shader shader;
  44
  45         struct r600_resource *input_buffer;
  46         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  47 };
  48
  49 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
  50 {
  51         unsigned scratch_bytes = 0;
  52         uint64_t scratch_buffer_va;
  53         unsigned i;
  54
  55         /* Compute the scratch buffer size using the maximum number of waves.
  56          * This way we don't need to recompute it for each kernel launch. */
  57         unsigned scratch_waves = 32 * sctx->screen->b.info.num_good_compute_units;
  58         for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
  59                 unsigned offset =
  60                                 program->shader.binary.global_symbol_offsets[i];
  61                 unsigned scratch_bytes_needed;
  62
  63                 si_shader_binary_read_config(&program->shader.binary,
  64                                              &program->shader.config, offset);
  65                 scratch_bytes_needed = program->shader.config.scratch_bytes_per_wave;
  66                 scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
  67         }
  68
  69         if (scratch_bytes == 0)
  70                 return;
  71
  72         program->shader.scratch_bo =
  73                                 si_resource_create_custom(sctx->b.b.screen,
  74                                 PIPE_USAGE_DEFAULT,
  75                                 scratch_bytes * scratch_waves);
  76
  77         scratch_buffer_va = program->shader.scratch_bo->gpu_address;
  78
  79         /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
  80          * to the maximum bytes needed, so it can compute the stride
  81          * correctly.
  82          */
  83         program->shader.config.scratch_bytes_per_wave = scratch_bytes;
  84
  85         /* Patch the shader with the scratch buffer address. */
  86         si_shader_apply_scratch_relocs(sctx,
  87                                 &program->shader, scratch_buffer_va);
  88 }
  89
  90 static void *si_create_compute_state(
  91         struct pipe_context *ctx,
  92         const struct pipe_compute_state *cso)
  93 {
  94         struct si_context *sctx = (struct si_context *)ctx;
  95         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
  96         struct si_compute *program = CALLOC_STRUCT(si_compute);
  97         struct si_shader *shader = &program->shader;
  98
  99
 100         program->ir_type = cso->ir_type;
 101         program->local_size = cso->req_local_mem;
 102         program->private_size = cso->req_private_mem;
 103         program->input_size = cso->req_input_mem;
 104
 105
 106         if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 107                 struct si_shader_selector sel;
 108                 bool scratch_enabled;
 109
 110                 memset(&sel, 0, sizeof(sel));
 111
 112                 sel.tokens = tgsi_dup_tokens(cso->prog);
 113                 if (!sel.tokens) {
 114                         return NULL;
 115                 }
 116
 117                 tgsi_scan_shader(cso->prog, &sel.info);
 118                 sel.type = PIPE_SHADER_COMPUTE;
 119                 sel.local_size = cso->req_local_mem;
 120
 121                 p_atomic_inc(&sscreen->b.num_shaders_created);
 122
 123                 program->shader.selector = &sel;
 124
 125                 if (si_compile_tgsi_shader(sscreen, sctx->tm, &program->shader,
 126                                            true, &sctx->b.debug)) {
 127                         FREE(sel.tokens);
 128                         return NULL;
 129                 }
 130
 131                 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 132
 133                 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
 134                            S_00B84C_SCRATCH_EN(scratch_enabled) |
 135                            S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 136                            S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 137                            S_00B84C_LDS_SIZE(shader->config.lds_size);
 138
 139                 FREE(sel.tokens);
 140         } else {
 141                 const struct pipe_llvm_program_header *header;
 142                 const char *code;
 143                 header = cso->prog;
 144                 code = cso->prog + sizeof(struct pipe_llvm_program_header);
 145
 146                 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 147                 /* init_scratch_buffer patches the shader code with the scratch address,
 148                 * so we need to call it before si_shader_binary_read() which uploads
 149                 * the shader code to the GPU.
 150                 */
 151                 init_scratch_buffer(sctx, program);
 152                 si_shader_binary_read_config(&program->shader.binary,
 153                              &program->shader.config, 0);
 154         }
 155         si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 156                        TGSI_PROCESSOR_COMPUTE, stderr);
 157         si_shader_binary_upload(sctx->screen, &program->shader);
 158
 159         if (program->input_size) {
 160                 program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
 161                         PIPE_USAGE_IMMUTABLE, program->input_size);
 162         }
 163
 164         return program;
 165 }
 166
 167 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 168 {
 169         struct si_context *sctx = (struct si_context*)ctx;
 170         sctx->cs_shader_state.program = (struct si_compute*)state;
 171 }
 172
 173 static void si_set_global_binding(
 174         struct pipe_context *ctx, unsigned first, unsigned n,
 175         struct pipe_resource **resources,
 176         uint32_t **handles)
 177 {
 178         unsigned i;
 179         struct si_context *sctx = (struct si_context*)ctx;
 180         struct si_compute *program = sctx->cs_shader_state.program;
 181
 182         if (!resources) {
 183                 for (i = first; i < first + n; i++) {
 184                         pipe_resource_reference(&program->global_buffers[i], NULL);
 185                 }
 186                 return;
 187         }
 188
 189         for (i = first; i < first + n; i++) {
 190                 uint64_t va;
 191                 uint32_t offset;
 192                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 193                 va = r600_resource(resources[i])->gpu_address;
 194                 offset = util_le32_to_cpu(*handles[i]);
 195                 va += offset;
 196                 va = util_cpu_to_le64(va);
 197                 memcpy(handles[i], &va, sizeof(va));
 198         }
 199 }
 200
 201 /**
 202  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 203  * /p block_layout is the number of threads in each work group.
 204  * /p grid layout is the number of work groups.
 205  */
 206 static unsigned compute_num_waves_for_scratch(
 207                 const struct radeon_info *info,
 208                 const uint *block_layout,
 209                 const uint *grid_layout)
 210 {
 211         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 212         unsigned num_se = MAX2(info->max_se, 1);
 213         unsigned num_blocks = 1;
 214         unsigned threads_per_block = 1;
 215         unsigned waves_per_block;
 216         unsigned waves_per_sh;
 217         unsigned waves;
 218         unsigned scratch_waves;
 219         unsigned i;
 220
 221         for (i = 0; i < 3; i++) {
 222                 threads_per_block *= block_layout[i];
 223                 num_blocks *= grid_layout[i];
 224         }
 225
 226         waves_per_block = align(threads_per_block, 64) / 64;
 227         waves = waves_per_block * num_blocks;
 228         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 229         scratch_waves = waves_per_sh * num_sh * num_se;
 230
 231         if (waves_per_block > waves_per_sh) {
 232                 scratch_waves = waves_per_block * num_sh * num_se;
 233         }
 234
 235         return scratch_waves;
 236 }
 237
 238 static void si_launch_grid(
 239                 struct pipe_context *ctx, const struct pipe_grid_info *info)
 240 {
 241         struct si_context *sctx = (struct si_context*)ctx;
 242         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 243         struct si_compute *program = sctx->cs_shader_state.program;
 244         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 245         struct r600_resource *input_buffer = program->input_buffer;
 246         unsigned kernel_args_size;
 247         unsigned num_work_size_bytes = 36;
 248         uint32_t kernel_args_offset = 0;
 249         uint32_t *kernel_args;
 250         uint64_t kernel_args_va;
 251         uint64_t scratch_buffer_va = 0;
 252         uint64_t shader_va;
 253         unsigned i;
 254         struct si_shader *shader = &program->shader;
 255         unsigned lds_blocks;
 256         unsigned num_waves_for_scratch;
 257
 258         radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 259         radeon_emit(cs, 0x80000000);
 260         radeon_emit(cs, 0x80000000);
 261
 262         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
 263                          SI_CONTEXT_INV_GLOBAL_L2 |
 264                          SI_CONTEXT_INV_ICACHE |
 265                          SI_CONTEXT_INV_SMEM_L1 |
 266                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 267                          SI_CONTEXT_FLAG_COMPUTE;
 268         si_emit_cache_flush(sctx, NULL);
 269
 270         pm4->compute_pkt = true;
 271
 272         /* Read the config information */
 273         si_shader_binary_read_config(&shader->binary, &shader->config, info->pc);
 274
 275         /* Upload the kernel arguments */
 276
 277         /* The extra num_work_size_bytes are for work group / work item size information */
 278         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 279
 280         kernel_args = sctx->b.ws->buffer_map(input_buffer->buf,
 281                         sctx->b.gfx.cs, PIPE_TRANSFER_WRITE);
 282         for (i = 0; i < 3; i++) {
 283                 kernel_args[i] = info->grid[i];
 284                 kernel_args[i + 3] = info->grid[i] * info->block[i];
 285                 kernel_args[i + 6] = info->block[i];
 286         }
 287
 288         num_waves_for_scratch = compute_num_waves_for_scratch(
 289                 &sctx->screen->b.info, info->block, info->grid);
 290
 291         memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
 292           program->input_size);
 293
 294         if (shader->config.scratch_bytes_per_wave > 0) {
 295
 296                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 297                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 298                             shader->config.scratch_bytes_per_wave,
 299                             shader->config.scratch_bytes_per_wave *
 300                             num_waves_for_scratch);
 301
 302                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 303                                           shader->scratch_bo,
 304                                           RADEON_USAGE_READWRITE,
 305                                           RADEON_PRIO_SCRATCH_BUFFER);
 306
 307                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 308         }
 309
 310         for (i = 0; i < (kernel_args_size / 4); i++) {
 311                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 312                         kernel_args[i]);
 313         }
 314
 315         kernel_args_va = input_buffer->gpu_address;
 316         kernel_args_va += kernel_args_offset;
 317
 318         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 319                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 320
 321         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 322         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 323         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 324         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 325                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 326                 |  S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64));
 327
 328         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 329         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 330         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 331
 332         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 333                                 S_00B81C_NUM_THREAD_FULL(info->block[0]));
 334         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 335                                 S_00B820_NUM_THREAD_FULL(info->block[1]));
 336         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 337                                 S_00B824_NUM_THREAD_FULL(info->block[2]));
 338
 339         /* Global buffers */
 340         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 341                 struct r600_resource *buffer =
 342                                 (struct r600_resource*)program->global_buffers[i];
 343                 if (!buffer) {
 344                         continue;
 345                 }
 346                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 347                                           RADEON_USAGE_READWRITE,
 348                                           RADEON_PRIO_COMPUTE_GLOBAL);
 349         }
 350
 351         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 352          * and is now per pipe, so it should be handled in the
 353          * kernel if we want to use something other than the default value,
 354          * which is now 0x22f.
 355          */
 356         if (sctx->b.chip_class <= SI) {
 357                 /* XXX: This should be:
 358                  * (number of compute units) * 4 * (waves per simd) - 1 */
 359
 360                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 361                                                 0x190 /* Default value */);
 362         }
 363
 364         shader_va = shader->bo->gpu_address;
 365         shader_va += info->pc;
 366
 367         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 368                                   RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 369         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
 370         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 371
 372         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->config.rsrc1);
 373
 374         lds_blocks = shader->config.lds_size;
 375         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 376          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 377          * the shader and 4 bytes allocated by the state tracker, then
 378          * we will set LDS_SIZE to 512 bytes rather than 256.
 379          */
 380         if (sctx->b.chip_class <= SI) {
 381                 lds_blocks += align(program->local_size, 256) >> 8;
 382         } else {
 383                 lds_blocks += align(program->local_size, 512) >> 9;
 384         }
 385
 386         assert(lds_blocks <= 0xFF);
 387
 388         shader->config.rsrc2 &= C_00B84C_LDS_SIZE;
 389         shader->config.rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 390
 391         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->config.rsrc2);
 392         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 393
 394         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 395                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 396                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 397                 ;
 398
 399         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 400                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 401                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 402                 ;
 403
 404         num_waves_for_scratch =
 405                 MIN2(num_waves_for_scratch,
 406                      32 * sctx->screen->b.info.num_good_compute_units);
 407         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 408                 /* The maximum value for WAVES is 32 * num CU.
 409                  * If you program this value incorrectly, the GPU will hang if
 410                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 411                  */
 412                 S_00B860_WAVES(num_waves_for_scratch)
 413                 | S_00B860_WAVESIZE(shader->config.scratch_bytes_per_wave >> 10))
 414                 ;
 415
 416         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 417         si_pm4_cmd_add(pm4, info->grid[0]); /* Thread groups DIM_X */
 418         si_pm4_cmd_add(pm4, info->grid[1]); /* Thread groups DIM_Y */
 419         si_pm4_cmd_add(pm4, info->grid[2]); /* Thread gropus DIM_Z */
 420         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 421         si_pm4_cmd_end(pm4, false);
 422
 423         si_pm4_emit(sctx, pm4);
 424
 425 #if 0
 426         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 427         for (i = 0; i < sctx->cs->cdw; i++) {
 428                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 429         }
 430 #endif
 431
 432         si_pm4_free_state(sctx, pm4, ~0);
 433
 434         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 435                          SI_CONTEXT_INV_VMEM_L1 |
 436                          SI_CONTEXT_INV_GLOBAL_L2 |
 437                          SI_CONTEXT_INV_ICACHE |
 438                          SI_CONTEXT_INV_SMEM_L1 |
 439                          SI_CONTEXT_FLAG_COMPUTE;
 440         si_emit_cache_flush(sctx, NULL);
 441 }
 442
 443
 444 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 445         struct si_compute *program = (struct si_compute *)state;
 446
 447         if (!state) {
 448                 return;
 449         }
 450
 451         si_shader_destroy(&program->shader);
 452         pipe_resource_reference(
 453                 (struct pipe_resource **)&program->input_buffer, NULL);
 454         FREE(program);
 455 }
 456
 457 static void si_set_compute_resources(struct pipe_context * ctx_,
 458                 unsigned start, unsigned count,
 459                 struct pipe_surface ** surfaces) { }
 460
 461 void si_init_compute_functions(struct si_context *sctx)
 462 {
 463         sctx->b.b.create_compute_state = si_create_compute_state;
 464         sctx->b.b.delete_compute_state = si_delete_compute_state;
 465         sctx->b.b.bind_compute_state = si_bind_compute_state;
 466 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 467         sctx->b.b.set_compute_resources = si_set_compute_resources;
 468         sctx->b.b.set_global_binding = si_set_global_binding;
 469         sctx->b.b.launch_grid = si_launch_grid;
 470 }