src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_memory.h"
  26 #include "radeon/r600_pipe_common.h"
  27 #include "radeon/radeon_elf_util.h"
  28 #include "radeon/radeon_llvm_util.h"
  29
  30 #include "radeon/r600_cs.h"
  31 #include "si_pipe.h"
  32 #include "si_shader.h"
  33 #include "sid.h"
  34
  35 #define MAX_GLOBAL_BUFFERS 20
  36 #if HAVE_LLVM < 0x0305
  37 #define NUM_USER_SGPRS 2
  38 #else
  39 /* XXX: Even though we don't pass the scratch buffer via user sgprs any more
  40  * LLVM still expects that we specify 4 USER_SGPRS so it can remain compatible
  41  * with older mesa. */
  42 #define NUM_USER_SGPRS 4
  43 #endif
  44
  45 struct si_compute {
  46         struct si_context *ctx;
  47
  48         unsigned local_size;
  49         unsigned private_size;
  50         unsigned input_size;
  51         struct si_shader shader;
  52         unsigned num_user_sgprs;
  53
  54         struct r600_resource *input_buffer;
  55         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  56
  57 #if HAVE_LLVM < 0x0306
  58         unsigned num_kernels;
  59         struct si_shader *kernels;
  60         LLVMContextRef llvm_ctx;
  61 #endif
  62 };
  63
  64 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
  65 {
  66         unsigned scratch_bytes = 0;
  67         uint64_t scratch_buffer_va;
  68         unsigned i;
  69
  70         /* Compute the scratch buffer size using the maximum number of waves.
  71          * This way we don't need to recompute it for each kernel launch. */
  72         unsigned scratch_waves = 32 * sctx->screen->b.info.max_compute_units;
  73         for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
  74                 unsigned offset =
  75                                 program->shader.binary.global_symbol_offsets[i];
  76                 unsigned scratch_bytes_needed;
  77
  78                 si_shader_binary_read_config(sctx->screen,
  79                                                 &program->shader, offset);
  80                 scratch_bytes_needed = program->shader.scratch_bytes_per_wave;
  81                 scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
  82         }
  83
  84         if (scratch_bytes == 0)
  85                 return;
  86
  87         program->shader.scratch_bo = (struct r600_resource*)
  88                                 si_resource_create_custom(sctx->b.b.screen,
  89                                 PIPE_USAGE_DEFAULT,
  90                                 scratch_bytes * scratch_waves);
  91
  92         scratch_buffer_va = program->shader.scratch_bo->gpu_address;
  93
  94         /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
  95          * to the maximum bytes needed, so it can compute the stride
  96          * correctly.
  97          */
  98         program->shader.scratch_bytes_per_wave = scratch_bytes;
  99
 100         /* Patch the shader with the scratch buffer address. */
 101         si_shader_apply_scratch_relocs(sctx,
 102                                 &program->shader, scratch_buffer_va);
 103 }
 104
 105 static void *si_create_compute_state(
 106         struct pipe_context *ctx,
 107         const struct pipe_compute_state *cso)
 108 {
 109         struct si_context *sctx = (struct si_context *)ctx;
 110         struct si_compute *program = CALLOC_STRUCT(si_compute);
 111         const struct pipe_llvm_program_header *header;
 112         const char *code;
 113
 114         header = cso->prog;
 115         code = cso->prog + sizeof(struct pipe_llvm_program_header);
 116
 117         program->ctx = sctx;
 118         program->local_size = cso->req_local_mem;
 119         program->private_size = cso->req_private_mem;
 120         program->input_size = cso->req_input_mem;
 121
 122 #if HAVE_LLVM < 0x0306
 123         {
 124                 unsigned i;
 125                 program->llvm_ctx = LLVMContextCreate();
 126                 program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
 127                                         code, header->num_bytes);
 128                 program->kernels = CALLOC(sizeof(struct si_shader),
 129                                                         program->num_kernels);
 130                 for (i = 0; i < program->num_kernels; i++) {
 131                         LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
 132                                                         code, header->num_bytes);
 133                         si_compile_llvm(sctx->screen, &program->kernels[i], mod);
 134                         LLVMDisposeModule(mod);
 135                 }
 136         }
 137 #else
 138
 139         radeon_elf_read(code, header->num_bytes, &program->shader.binary, true);
 140
 141         /* init_scratch_buffer patches the shader code with the scratch address,
 142          * so we need to call it before si_shader_binary_read() which uploads
 143          * the shader code to the GPU.
 144          */
 145         init_scratch_buffer(sctx, program);
 146         si_shader_binary_read(sctx->screen, &program->shader, &program->shader.binary);
 147
 148 #endif
 149         program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
 150                 PIPE_USAGE_IMMUTABLE, program->input_size);
 151
 152         return program;
 153 }
 154
 155 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 156 {
 157         struct si_context *sctx = (struct si_context*)ctx;
 158         sctx->cs_shader_state.program = (struct si_compute*)state;
 159 }
 160
 161 static void si_set_global_binding(
 162         struct pipe_context *ctx, unsigned first, unsigned n,
 163         struct pipe_resource **resources,
 164         uint32_t **handles)
 165 {
 166         unsigned i;
 167         struct si_context *sctx = (struct si_context*)ctx;
 168         struct si_compute *program = sctx->cs_shader_state.program;
 169
 170         if (!resources) {
 171                 for (i = first; i < first + n; i++) {
 172                         pipe_resource_reference(&program->global_buffers[i], NULL);
 173                 }
 174                 return;
 175         }
 176
 177         for (i = first; i < first + n; i++) {
 178                 uint64_t va;
 179                 uint32_t offset;
 180                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 181                 va = r600_resource(resources[i])->gpu_address;
 182                 offset = util_le32_to_cpu(*handles[i]);
 183                 va += offset;
 184                 va = util_cpu_to_le64(va);
 185                 memcpy(handles[i], &va, sizeof(va));
 186         }
 187 }
 188
 189 /**
 190  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 191  * /p block_layout is the number of threads in each work group.
 192  * /p grid layout is the number of work groups.
 193  */
 194 static unsigned compute_num_waves_for_scratch(
 195                 const struct radeon_info *info,
 196                 const uint *block_layout,
 197                 const uint *grid_layout)
 198 {
 199         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 200         unsigned num_se = MAX2(info->max_se, 1);
 201         unsigned num_blocks = 1;
 202         unsigned threads_per_block = 1;
 203         unsigned waves_per_block;
 204         unsigned waves_per_sh;
 205         unsigned waves;
 206         unsigned scratch_waves;
 207         unsigned i;
 208
 209         for (i = 0; i < 3; i++) {
 210                 threads_per_block *= block_layout[i];
 211                 num_blocks *= grid_layout[i];
 212         }
 213
 214         waves_per_block = align(threads_per_block, 64) / 64;
 215         waves = waves_per_block * num_blocks;
 216         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 217         scratch_waves = waves_per_sh * num_sh * num_se;
 218
 219         if (waves_per_block > waves_per_sh) {
 220                 scratch_waves = waves_per_block * num_sh * num_se;
 221         }
 222
 223         return scratch_waves;
 224 }
 225
 226 static void si_launch_grid(
 227                 struct pipe_context *ctx,
 228                 const uint *block_layout, const uint *grid_layout,
 229                 uint32_t pc, const void *input)
 230 {
 231         struct si_context *sctx = (struct si_context*)ctx;
 232         struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
 233         struct si_compute *program = sctx->cs_shader_state.program;
 234         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 235         struct r600_resource *input_buffer = program->input_buffer;
 236         unsigned kernel_args_size;
 237         unsigned num_work_size_bytes = 36;
 238         uint32_t kernel_args_offset = 0;
 239         uint32_t *kernel_args;
 240         uint64_t kernel_args_va;
 241         uint64_t scratch_buffer_va = 0;
 242         uint64_t shader_va;
 243         unsigned arg_user_sgpr_count = NUM_USER_SGPRS;
 244         unsigned i;
 245         struct si_shader *shader = &program->shader;
 246         unsigned lds_blocks;
 247         unsigned num_waves_for_scratch;
 248
 249 #if HAVE_LLVM < 0x0306
 250         shader = &program->kernels[pc];
 251 #endif
 252
 253
 254         radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 255         radeon_emit(cs, 0x80000000);
 256         radeon_emit(cs, 0x80000000);
 257
 258         sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
 259                          SI_CONTEXT_INV_TC_L2 |
 260                          SI_CONTEXT_INV_ICACHE |
 261                          SI_CONTEXT_INV_KCACHE |
 262                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 263                          SI_CONTEXT_FLAG_COMPUTE;
 264         si_emit_cache_flush(&sctx->b, NULL);
 265
 266         pm4->compute_pkt = true;
 267
 268 #if HAVE_LLVM >= 0x0306
 269         /* Read the config information */
 270         si_shader_binary_read_config(sctx->screen, shader, pc);
 271 #endif
 272
 273         /* Upload the kernel arguments */
 274
 275         /* The extra num_work_size_bytes are for work group / work item size information */
 276         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 277
 278         kernel_args = sctx->b.ws->buffer_map(input_buffer->cs_buf,
 279                         sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
 280         for (i = 0; i < 3; i++) {
 281                 kernel_args[i] = grid_layout[i];
 282                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 283                 kernel_args[i + 6] = block_layout[i];
 284         }
 285
 286         num_waves_for_scratch = compute_num_waves_for_scratch(
 287                 &sctx->screen->b.info, block_layout, grid_layout);
 288
 289         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 290
 291         if (shader->scratch_bytes_per_wave > 0) {
 292
 293                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 294                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 295                             shader->scratch_bytes_per_wave,
 296                             shader->scratch_bytes_per_wave *
 297                             num_waves_for_scratch);
 298
 299                 si_pm4_add_bo(pm4, shader->scratch_bo,
 300                                 RADEON_USAGE_READWRITE,
 301                                 RADEON_PRIO_SHADER_RESOURCE_RW);
 302
 303                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 304         }
 305
 306         for (i = 0; i < (kernel_args_size / 4); i++) {
 307                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 308                         kernel_args[i]);
 309         }
 310
 311         sctx->b.ws->buffer_unmap(input_buffer->cs_buf);
 312
 313         kernel_args_va = input_buffer->gpu_address;
 314         kernel_args_va += kernel_args_offset;
 315
 316         si_pm4_add_bo(pm4, input_buffer, RADEON_USAGE_READ,
 317                 RADEON_PRIO_SHADER_DATA);
 318
 319         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 320         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 321         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 322         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 323                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 324                 |  S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64));
 325
 326         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 327         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 328         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 329
 330         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 331                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 332         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 333                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 334         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 335                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 336
 337         /* Global buffers */
 338         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 339                 struct r600_resource *buffer =
 340                                 (struct r600_resource*)program->global_buffers[i];
 341                 if (!buffer) {
 342                         continue;
 343                 }
 344                 si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
 345         }
 346
 347         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 348          * and is now per pipe, so it should be handled in the
 349          * kernel if we want to use something other than the default value,
 350          * which is now 0x22f.
 351          */
 352         if (sctx->b.chip_class <= SI) {
 353                 /* XXX: This should be:
 354                  * (number of compute units) * 4 * (waves per simd) - 1 */
 355
 356                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 357                                                 0x190 /* Default value */);
 358         }
 359
 360         shader_va = shader->bo->gpu_address;
 361
 362 #if HAVE_LLVM >= 0x0306
 363         shader_va += pc;
 364 #endif
 365         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 366         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 367         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 368
 369         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 370                 /* We always use at least 3 VGPRS, these come from
 371                  * TIDIG_COMP_CNT.
 372                  * XXX: The compiler should account for this.
 373                  */
 374                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 375                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 376                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 377                  * XXX: The compiler should account for this.
 378                  */
 379                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 380                                         shader->num_sgprs)) - 1) / 8)
 381                 |  S_00B028_FLOAT_MODE(shader->float_mode))
 382                 ;
 383
 384         lds_blocks = shader->lds_size;
 385         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 386          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 387          * the shader and 4 bytes allocated by the state tracker, then
 388          * we will set LDS_SIZE to 512 bytes rather than 256.
 389          */
 390         if (sctx->b.chip_class <= SI) {
 391                 lds_blocks += align(program->local_size, 256) >> 8;
 392         } else {
 393                 lds_blocks += align(program->local_size, 512) >> 9;
 394         }
 395
 396         assert(lds_blocks <= 0xFF);
 397
 398         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 399                 S_00B84C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0)
 400                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 401                 | S_00B84C_TGID_X_EN(1)
 402                 | S_00B84C_TGID_Y_EN(1)
 403                 | S_00B84C_TGID_Z_EN(1)
 404                 | S_00B84C_TG_SIZE_EN(1)
 405                 | S_00B84C_TIDIG_COMP_CNT(2)
 406                 | S_00B84C_LDS_SIZE(lds_blocks)
 407                 | S_00B84C_EXCP_EN(0))
 408                 ;
 409         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 410
 411         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 412                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 413                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 414                 ;
 415
 416         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 417                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 418                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 419                 ;
 420
 421         num_waves_for_scratch =
 422                 MIN2(num_waves_for_scratch,
 423                      32 * sctx->screen->b.info.max_compute_units);
 424         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 425                 /* The maximum value for WAVES is 32 * num CU.
 426                  * If you program this value incorrectly, the GPU will hang if
 427                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 428                  */
 429                 S_00B860_WAVES(num_waves_for_scratch)
 430                 | S_00B860_WAVESIZE(shader->scratch_bytes_per_wave >> 10))
 431                 ;
 432
 433         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 434         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 435         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 436         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 437         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 438         si_pm4_cmd_end(pm4, false);
 439
 440         si_pm4_emit(sctx, pm4);
 441
 442 #if 0
 443         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 444         for (i = 0; i < sctx->cs->cdw; i++) {
 445                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 446         }
 447 #endif
 448
 449         si_pm4_free_state(sctx, pm4, ~0);
 450
 451         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 452                          SI_CONTEXT_INV_TC_L1 |
 453                          SI_CONTEXT_INV_TC_L2 |
 454                          SI_CONTEXT_INV_ICACHE |
 455                          SI_CONTEXT_INV_KCACHE |
 456                          SI_CONTEXT_FLAG_COMPUTE;
 457         si_emit_cache_flush(&sctx->b, NULL);
 458 }
 459
 460
 461 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 462         struct si_compute *program = (struct si_compute *)state;
 463
 464         if (!state) {
 465                 return;
 466         }
 467
 468 #if HAVE_LLVM < 0x0306
 469         if (program->kernels) {
 470                 for (int i = 0; i < program->num_kernels; i++){
 471                         if (program->kernels[i].bo){
 472                                 si_shader_destroy(ctx, &program->kernels[i]);
 473                         }
 474                 }
 475                 FREE(program->kernels);
 476         }
 477
 478         if (program->llvm_ctx){
 479                 LLVMContextDispose(program->llvm_ctx);
 480         }
 481 #else
 482         FREE(program->shader.binary.config);
 483         FREE(program->shader.binary.rodata);
 484         FREE(program->shader.binary.global_symbol_offsets);
 485         si_shader_destroy(ctx, &program->shader);
 486 #endif
 487
 488         pipe_resource_reference(
 489                 (struct pipe_resource **)&program->input_buffer, NULL);
 490
 491         FREE(program);
 492 }
 493
 494 static void si_set_compute_resources(struct pipe_context * ctx_,
 495                 unsigned start, unsigned count,
 496                 struct pipe_surface ** surfaces) { }
 497
 498 void si_init_compute_functions(struct si_context *sctx)
 499 {
 500         sctx->b.b.create_compute_state = si_create_compute_state;
 501         sctx->b.b.delete_compute_state = si_delete_compute_state;
 502         sctx->b.b.bind_compute_state = si_bind_compute_state;
 503 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 504         sctx->b.b.set_compute_resources = si_set_compute_resources;
 505         sctx->b.b.set_global_binding = si_set_global_binding;
 506         sctx->b.b.launch_grid = si_launch_grid;
 507 }