src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_memory.h"
  26 #include "radeon/r600_pipe_common.h"
  27 #include "radeon/radeon_elf_util.h"
  28 #include "radeon/radeon_llvm_util.h"
  29
  30 #include "radeon/r600_cs.h"
  31 #include "si_pipe.h"
  32 #include "si_shader.h"
  33 #include "sid.h"
  34
  35 #define MAX_GLOBAL_BUFFERS 20
  36
  37 struct si_compute {
  38         struct si_context *ctx;
  39
  40         unsigned local_size;
  41         unsigned private_size;
  42         unsigned input_size;
  43         struct si_shader shader;
  44         unsigned num_user_sgprs;
  45
  46         struct r600_resource *input_buffer;
  47         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  48
  49 #if HAVE_LLVM < 0x0306
  50         unsigned num_kernels;
  51         struct si_shader *kernels;
  52         LLVMContextRef llvm_ctx;
  53 #endif
  54 };
  55
  56 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
  57 {
  58         unsigned scratch_bytes = 0;
  59         uint64_t scratch_buffer_va;
  60         unsigned i;
  61
  62         /* Compute the scratch buffer size using the maximum number of waves.
  63          * This way we don't need to recompute it for each kernel launch. */
  64         unsigned scratch_waves = 32 * sctx->screen->b.info.num_good_compute_units;
  65         for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
  66                 unsigned offset =
  67                                 program->shader.binary.global_symbol_offsets[i];
  68                 unsigned scratch_bytes_needed;
  69
  70                 si_shader_binary_read_config(&program->shader.binary,
  71                                              &program->shader.config, offset);
  72                 scratch_bytes_needed = program->shader.config.scratch_bytes_per_wave;
  73                 scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
  74         }
  75
  76         if (scratch_bytes == 0)
  77                 return;
  78
  79         program->shader.scratch_bo =
  80                                 si_resource_create_custom(sctx->b.b.screen,
  81                                 PIPE_USAGE_DEFAULT,
  82                                 scratch_bytes * scratch_waves);
  83
  84         scratch_buffer_va = program->shader.scratch_bo->gpu_address;
  85
  86         /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
  87          * to the maximum bytes needed, so it can compute the stride
  88          * correctly.
  89          */
  90         program->shader.config.scratch_bytes_per_wave = scratch_bytes;
  91
  92         /* Patch the shader with the scratch buffer address. */
  93         si_shader_apply_scratch_relocs(sctx,
  94                                 &program->shader, scratch_buffer_va);
  95 }
  96
  97 static void *si_create_compute_state(
  98         struct pipe_context *ctx,
  99         const struct pipe_compute_state *cso)
 100 {
 101         struct si_context *sctx = (struct si_context *)ctx;
 102         struct si_compute *program = CALLOC_STRUCT(si_compute);
 103         const struct pipe_llvm_program_header *header;
 104         const char *code;
 105
 106         header = cso->prog;
 107         code = cso->prog + sizeof(struct pipe_llvm_program_header);
 108
 109         program->ctx = sctx;
 110         program->local_size = cso->req_local_mem;
 111         program->private_size = cso->req_private_mem;
 112         program->input_size = cso->req_input_mem;
 113
 114 #if HAVE_LLVM < 0x0306
 115         {
 116                 unsigned i;
 117                 program->llvm_ctx = LLVMContextCreate();
 118                 program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
 119                                         code, header->num_bytes);
 120                 program->kernels = CALLOC(sizeof(struct si_shader),
 121                                                         program->num_kernels);
 122                 for (i = 0; i < program->num_kernels; i++) {
 123                         LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
 124                                                         code, header->num_bytes);
 125                         si_compile_llvm(sctx->screen, &program->kernels[i].binary,
 126                                         &program->kernels[i].config, sctx->tm,
 127                                         mod, &sctx->b.debug, TGSI_PROCESSOR_COMPUTE,
 128                                         "Compute Shader");
 129                         si_shader_dump(sctx->screen, &program->kernels[i],
 130                                        &sctx->b.debug, TGSI_PROCESSOR_COMPUTE);
 131                         si_shader_binary_upload(sctx->screen, &program->kernels[i]);
 132                         LLVMDisposeModule(mod);
 133                 }
 134         }
 135 #else
 136
 137         radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 138
 139         /* init_scratch_buffer patches the shader code with the scratch address,
 140          * so we need to call it before si_shader_binary_read() which uploads
 141          * the shader code to the GPU.
 142          */
 143         init_scratch_buffer(sctx, program);
 144         si_shader_binary_read_config(&program->shader.binary,
 145                                      &program->shader.config, 0);
 146         si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 147                        TGSI_PROCESSOR_COMPUTE);
 148         si_shader_binary_upload(sctx->screen, &program->shader);
 149
 150 #endif
 151         program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
 152                 PIPE_USAGE_IMMUTABLE, program->input_size);
 153
 154         return program;
 155 }
 156
 157 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 158 {
 159         struct si_context *sctx = (struct si_context*)ctx;
 160         sctx->cs_shader_state.program = (struct si_compute*)state;
 161 }
 162
 163 static void si_set_global_binding(
 164         struct pipe_context *ctx, unsigned first, unsigned n,
 165         struct pipe_resource **resources,
 166         uint32_t **handles)
 167 {
 168         unsigned i;
 169         struct si_context *sctx = (struct si_context*)ctx;
 170         struct si_compute *program = sctx->cs_shader_state.program;
 171
 172         if (!resources) {
 173                 for (i = first; i < first + n; i++) {
 174                         pipe_resource_reference(&program->global_buffers[i], NULL);
 175                 }
 176                 return;
 177         }
 178
 179         for (i = first; i < first + n; i++) {
 180                 uint64_t va;
 181                 uint32_t offset;
 182                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 183                 va = r600_resource(resources[i])->gpu_address;
 184                 offset = util_le32_to_cpu(*handles[i]);
 185                 va += offset;
 186                 va = util_cpu_to_le64(va);
 187                 memcpy(handles[i], &va, sizeof(va));
 188         }
 189 }
 190
 191 /**
 192  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 193  * /p block_layout is the number of threads in each work group.
 194  * /p grid layout is the number of work groups.
 195  */
 196 static unsigned compute_num_waves_for_scratch(
 197                 const struct radeon_info *info,
 198                 const uint *block_layout,
 199                 const uint *grid_layout)
 200 {
 201         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 202         unsigned num_se = MAX2(info->max_se, 1);
 203         unsigned num_blocks = 1;
 204         unsigned threads_per_block = 1;
 205         unsigned waves_per_block;
 206         unsigned waves_per_sh;
 207         unsigned waves;
 208         unsigned scratch_waves;
 209         unsigned i;
 210
 211         for (i = 0; i < 3; i++) {
 212                 threads_per_block *= block_layout[i];
 213                 num_blocks *= grid_layout[i];
 214         }
 215
 216         waves_per_block = align(threads_per_block, 64) / 64;
 217         waves = waves_per_block * num_blocks;
 218         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 219         scratch_waves = waves_per_sh * num_sh * num_se;
 220
 221         if (waves_per_block > waves_per_sh) {
 222                 scratch_waves = waves_per_block * num_sh * num_se;
 223         }
 224
 225         return scratch_waves;
 226 }
 227
 228 static void si_launch_grid(
 229                 struct pipe_context *ctx,
 230                 const uint *block_layout, const uint *grid_layout,
 231                 uint32_t pc, const void *input)
 232 {
 233         struct si_context *sctx = (struct si_context*)ctx;
 234         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 235         struct si_compute *program = sctx->cs_shader_state.program;
 236         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 237         struct r600_resource *input_buffer = program->input_buffer;
 238         unsigned kernel_args_size;
 239         unsigned num_work_size_bytes = 36;
 240         uint32_t kernel_args_offset = 0;
 241         uint32_t *kernel_args;
 242         uint64_t kernel_args_va;
 243         uint64_t scratch_buffer_va = 0;
 244         uint64_t shader_va;
 245         unsigned i;
 246         struct si_shader *shader = &program->shader;
 247         unsigned lds_blocks;
 248         unsigned num_waves_for_scratch;
 249
 250 #if HAVE_LLVM < 0x0306
 251         shader = &program->kernels[pc];
 252 #endif
 253
 254
 255         radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 256         radeon_emit(cs, 0x80000000);
 257         radeon_emit(cs, 0x80000000);
 258
 259         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
 260                          SI_CONTEXT_INV_GLOBAL_L2 |
 261                          SI_CONTEXT_INV_ICACHE |
 262                          SI_CONTEXT_INV_SMEM_L1 |
 263                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 264                          SI_CONTEXT_FLAG_COMPUTE;
 265         si_emit_cache_flush(sctx, NULL);
 266
 267         pm4->compute_pkt = true;
 268
 269 #if HAVE_LLVM >= 0x0306
 270         /* Read the config information */
 271         si_shader_binary_read_config(&shader->binary, &shader->config, pc);
 272 #endif
 273
 274         /* Upload the kernel arguments */
 275
 276         /* The extra num_work_size_bytes are for work group / work item size information */
 277         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 278
 279         kernel_args = sctx->b.ws->buffer_map(input_buffer->buf,
 280                         sctx->b.gfx.cs, PIPE_TRANSFER_WRITE);
 281         for (i = 0; i < 3; i++) {
 282                 kernel_args[i] = grid_layout[i];
 283                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 284                 kernel_args[i + 6] = block_layout[i];
 285         }
 286
 287         num_waves_for_scratch = compute_num_waves_for_scratch(
 288                 &sctx->screen->b.info, block_layout, grid_layout);
 289
 290         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 291
 292         if (shader->config.scratch_bytes_per_wave > 0) {
 293
 294                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 295                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 296                             shader->config.scratch_bytes_per_wave,
 297                             shader->config.scratch_bytes_per_wave *
 298                             num_waves_for_scratch);
 299
 300                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 301                                           shader->scratch_bo,
 302                                           RADEON_USAGE_READWRITE,
 303                                           RADEON_PRIO_SCRATCH_BUFFER);
 304
 305                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 306         }
 307
 308         for (i = 0; i < (kernel_args_size / 4); i++) {
 309                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 310                         kernel_args[i]);
 311         }
 312
 313         kernel_args_va = input_buffer->gpu_address;
 314         kernel_args_va += kernel_args_offset;
 315
 316         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 317                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 318
 319         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 320         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 321         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 322         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 323                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 324                 |  S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64));
 325
 326         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 327         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 328         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 329
 330         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 331                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 332         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 333                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 334         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 335                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 336
 337         /* Global buffers */
 338         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 339                 struct r600_resource *buffer =
 340                                 (struct r600_resource*)program->global_buffers[i];
 341                 if (!buffer) {
 342                         continue;
 343                 }
 344                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 345                                           RADEON_USAGE_READWRITE,
 346                                           RADEON_PRIO_COMPUTE_GLOBAL);
 347         }
 348
 349         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 350          * and is now per pipe, so it should be handled in the
 351          * kernel if we want to use something other than the default value,
 352          * which is now 0x22f.
 353          */
 354         if (sctx->b.chip_class <= SI) {
 355                 /* XXX: This should be:
 356                  * (number of compute units) * 4 * (waves per simd) - 1 */
 357
 358                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 359                                                 0x190 /* Default value */);
 360         }
 361
 362         shader_va = shader->bo->gpu_address;
 363
 364 #if HAVE_LLVM >= 0x0306
 365         shader_va += pc;
 366 #endif
 367         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 368                                   RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 369         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
 370         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 371
 372         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->config.rsrc1);
 373
 374         lds_blocks = shader->config.lds_size;
 375         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 376          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 377          * the shader and 4 bytes allocated by the state tracker, then
 378          * we will set LDS_SIZE to 512 bytes rather than 256.
 379          */
 380         if (sctx->b.chip_class <= SI) {
 381                 lds_blocks += align(program->local_size, 256) >> 8;
 382         } else {
 383                 lds_blocks += align(program->local_size, 512) >> 9;
 384         }
 385
 386         assert(lds_blocks <= 0xFF);
 387
 388         shader->config.rsrc2 &= C_00B84C_LDS_SIZE;
 389         shader->config.rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 390
 391         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->config.rsrc2);
 392         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 393
 394         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 395                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 396                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 397                 ;
 398
 399         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 400                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 401                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 402                 ;
 403
 404         num_waves_for_scratch =
 405                 MIN2(num_waves_for_scratch,
 406                      32 * sctx->screen->b.info.num_good_compute_units);
 407         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 408                 /* The maximum value for WAVES is 32 * num CU.
 409                  * If you program this value incorrectly, the GPU will hang if
 410                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 411                  */
 412                 S_00B860_WAVES(num_waves_for_scratch)
 413                 | S_00B860_WAVESIZE(shader->config.scratch_bytes_per_wave >> 10))
 414                 ;
 415
 416         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 417         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 418         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 419         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 420         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 421         si_pm4_cmd_end(pm4, false);
 422
 423         si_pm4_emit(sctx, pm4);
 424
 425 #if 0
 426         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 427         for (i = 0; i < sctx->cs->cdw; i++) {
 428                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 429         }
 430 #endif
 431
 432         si_pm4_free_state(sctx, pm4, ~0);
 433
 434         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 435                          SI_CONTEXT_INV_VMEM_L1 |
 436                          SI_CONTEXT_INV_GLOBAL_L2 |
 437                          SI_CONTEXT_INV_ICACHE |
 438                          SI_CONTEXT_INV_SMEM_L1 |
 439                          SI_CONTEXT_FLAG_COMPUTE;
 440         si_emit_cache_flush(sctx, NULL);
 441 }
 442
 443
 444 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 445         struct si_compute *program = (struct si_compute *)state;
 446
 447         if (!state) {
 448                 return;
 449         }
 450
 451 #if HAVE_LLVM < 0x0306
 452         if (program->kernels) {
 453                 for (int i = 0; i < program->num_kernels; i++){
 454                         if (program->kernels[i].bo){
 455                                 si_shader_destroy(&program->kernels[i]);
 456                         }
 457                 }
 458                 FREE(program->kernels);
 459         }
 460
 461         if (program->llvm_ctx){
 462                 LLVMContextDispose(program->llvm_ctx);
 463         }
 464 #else
 465         si_shader_destroy(&program->shader);
 466 #endif
 467
 468         pipe_resource_reference(
 469                 (struct pipe_resource **)&program->input_buffer, NULL);
 470
 471         FREE(program);
 472 }
 473
 474 static void si_set_compute_resources(struct pipe_context * ctx_,
 475                 unsigned start, unsigned count,
 476                 struct pipe_surface ** surfaces) { }
 477
 478 void si_init_compute_functions(struct si_context *sctx)
 479 {
 480         sctx->b.b.create_compute_state = si_create_compute_state;
 481         sctx->b.b.delete_compute_state = si_delete_compute_state;
 482         sctx->b.b.bind_compute_state = si_bind_compute_state;
 483 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 484         sctx->b.b.set_compute_resources = si_set_compute_resources;
 485         sctx->b.b.set_global_binding = si_set_global_binding;
 486         sctx->b.b.launch_grid = si_launch_grid;
 487 }