src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_memory.h"
  26 #include "radeon/r600_pipe_common.h"
  27 #include "radeon/radeon_elf_util.h"
  28 #include "radeon/radeon_llvm_util.h"
  29
  30 #include "radeon/r600_cs.h"
  31 #include "si_pipe.h"
  32 #include "si_shader.h"
  33 #include "sid.h"
  34
  35 #define MAX_GLOBAL_BUFFERS 20
  36 #if HAVE_LLVM < 0x0305
  37 #define NUM_USER_SGPRS 2
  38 #else
  39 #define NUM_USER_SGPRS 4
  40 #endif
  41
  42 struct si_compute {
  43         struct si_context *ctx;
  44
  45         unsigned local_size;
  46         unsigned private_size;
  47         unsigned input_size;
  48         struct radeon_shader_binary binary;
  49         struct si_shader program;
  50         unsigned num_user_sgprs;
  51
  52         struct r600_resource *input_buffer;
  53         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  54
  55 #if HAVE_LLVM < 0x0306
  56         unsigned num_kernels;
  57         struct si_shader *kernels;
  58         LLVMContextRef llvm_ctx;
  59 #endif
  60 };
  61
  62 static void *si_create_compute_state(
  63         struct pipe_context *ctx,
  64         const struct pipe_compute_state *cso)
  65 {
  66         struct si_context *sctx = (struct si_context *)ctx;
  67         struct si_compute *program = CALLOC_STRUCT(si_compute);
  68         const struct pipe_llvm_program_header *header;
  69         const char *code;
  70
  71         header = cso->prog;
  72         code = cso->prog + sizeof(struct pipe_llvm_program_header);
  73
  74         program->ctx = sctx;
  75         program->local_size = cso->req_local_mem;
  76         program->private_size = cso->req_private_mem;
  77         program->input_size = cso->req_input_mem;
  78
  79 #if HAVE_LLVM < 0x0306
  80         {
  81                 unsigned i;
  82                 program->llvm_ctx = LLVMContextCreate();
  83                 program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
  84                                         code, header->num_bytes);
  85                 program->kernels = CALLOC(sizeof(struct si_shader),
  86                                                         program->num_kernels);
  87                 for (i = 0; i < program->num_kernels; i++) {
  88                         LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
  89                                                         code, header->num_bytes);
  90                         si_compile_llvm(sctx->screen, &program->kernels[i], mod);
  91                         LLVMDisposeModule(mod);
  92                 }
  93         }
  94 #else
  95
  96         radeon_elf_read(code, header->num_bytes, &program->binary, true);
  97         si_shader_binary_read(sctx->screen, &program->program, &program->binary);
  98
  99 #endif
 100         program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
 101                 PIPE_USAGE_IMMUTABLE, program->input_size);
 102
 103         return program;
 104 }
 105
 106 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 107 {
 108         struct si_context *sctx = (struct si_context*)ctx;
 109         sctx->cs_shader_state.program = (struct si_compute*)state;
 110 }
 111
 112 static void si_set_global_binding(
 113         struct pipe_context *ctx, unsigned first, unsigned n,
 114         struct pipe_resource **resources,
 115         uint32_t **handles)
 116 {
 117         unsigned i;
 118         struct si_context *sctx = (struct si_context*)ctx;
 119         struct si_compute *program = sctx->cs_shader_state.program;
 120
 121         if (!resources) {
 122                 for (i = first; i < first + n; i++) {
 123                         pipe_resource_reference(&program->global_buffers[i], NULL);
 124                 }
 125                 return;
 126         }
 127
 128         for (i = first; i < first + n; i++) {
 129                 uint64_t va;
 130                 uint32_t offset;
 131                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 132                 va = r600_resource(resources[i])->gpu_address;
 133                 offset = util_le32_to_cpu(*handles[i]);
 134                 va += offset;
 135                 va = util_cpu_to_le64(va);
 136                 memcpy(handles[i], &va, sizeof(va));
 137         }
 138 }
 139
 140 /**
 141  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 142  * /p block_layout is the number of threads in each work group.
 143  * /p grid layout is the number of work groups.
 144  */
 145 static unsigned compute_num_waves_for_scratch(
 146                 const struct radeon_info *info,
 147                 const uint *block_layout,
 148                 const uint *grid_layout)
 149 {
 150         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 151         unsigned num_se = MAX2(info->max_se, 1);
 152         unsigned num_blocks = 1;
 153         unsigned threads_per_block = 1;
 154         unsigned waves_per_block;
 155         unsigned waves_per_sh;
 156         unsigned waves;
 157         unsigned scratch_waves;
 158         unsigned i;
 159
 160         for (i = 0; i < 3; i++) {
 161                 threads_per_block *= block_layout[i];
 162                 num_blocks *= grid_layout[i];
 163         }
 164
 165         waves_per_block = align(threads_per_block, 64) / 64;
 166         waves = waves_per_block * num_blocks;
 167         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 168         scratch_waves = waves_per_sh * num_sh * num_se;
 169
 170         if (waves_per_block > waves_per_sh) {
 171                 scratch_waves = waves_per_block * num_sh * num_se;
 172         }
 173
 174         return scratch_waves;
 175 }
 176
 177 static void si_launch_grid(
 178                 struct pipe_context *ctx,
 179                 const uint *block_layout, const uint *grid_layout,
 180                 uint32_t pc, const void *input)
 181 {
 182         struct si_context *sctx = (struct si_context*)ctx;
 183         struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
 184         struct si_compute *program = sctx->cs_shader_state.program;
 185         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 186         struct r600_resource *input_buffer = program->input_buffer;
 187         unsigned kernel_args_size;
 188         unsigned num_work_size_bytes = 36;
 189         uint32_t kernel_args_offset = 0;
 190         uint32_t *kernel_args;
 191         uint64_t kernel_args_va;
 192         uint64_t scratch_buffer_va = 0;
 193         uint64_t shader_va;
 194         unsigned arg_user_sgpr_count = NUM_USER_SGPRS;
 195         unsigned i;
 196         struct si_shader *shader = &program->program;
 197         unsigned lds_blocks;
 198         unsigned num_waves_for_scratch;
 199
 200 #if HAVE_LLVM < 0x0306
 201         shader = &program->kernels[pc];
 202 #endif
 203
 204
 205         radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 206         radeon_emit(cs, 0x80000000);
 207         radeon_emit(cs, 0x80000000);
 208
 209         sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
 210                          SI_CONTEXT_INV_TC_L2 |
 211                          SI_CONTEXT_INV_ICACHE |
 212                          SI_CONTEXT_INV_KCACHE |
 213                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 214                          SI_CONTEXT_FLAG_COMPUTE;
 215         si_emit_cache_flush(&sctx->b, NULL);
 216
 217         pm4->compute_pkt = true;
 218
 219 #if HAVE_LLVM >= 0x0306
 220         /* Read the config information */
 221         si_shader_binary_read_config(&program->binary, &program->program, pc);
 222 #endif
 223
 224         /* Upload the kernel arguments */
 225
 226         /* The extra num_work_size_bytes are for work group / work item size information */
 227         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 228
 229         kernel_args = sctx->b.ws->buffer_map(input_buffer->cs_buf,
 230                         sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
 231         for (i = 0; i < 3; i++) {
 232                 kernel_args[i] = grid_layout[i];
 233                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 234                 kernel_args[i + 6] = block_layout[i];
 235         }
 236
 237         num_waves_for_scratch = compute_num_waves_for_scratch(
 238                 &sctx->screen->b.info, block_layout, grid_layout);
 239
 240         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 241
 242         if (shader->scratch_bytes_per_wave > 0) {
 243                 unsigned scratch_bytes = shader->scratch_bytes_per_wave *
 244                                                 num_waves_for_scratch;
 245
 246                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 247                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 248                             shader->scratch_bytes_per_wave, scratch_bytes);
 249                 if (!shader->scratch_bo) {
 250                         shader->scratch_bo = (struct r600_resource*)
 251                                 si_resource_create_custom(sctx->b.b.screen,
 252                                 PIPE_USAGE_DEFAULT, scratch_bytes);
 253                 }
 254                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 255                 si_pm4_add_bo(pm4, shader->scratch_bo,
 256                                 RADEON_USAGE_READWRITE,
 257                                 RADEON_PRIO_SHADER_RESOURCE_RW);
 258
 259         }
 260
 261         for (i = 0; i < (kernel_args_size / 4); i++) {
 262                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 263                         kernel_args[i]);
 264         }
 265
 266         sctx->b.ws->buffer_unmap(input_buffer->cs_buf);
 267
 268         kernel_args_va = input_buffer->gpu_address;
 269         kernel_args_va += kernel_args_offset;
 270
 271         si_pm4_add_bo(pm4, input_buffer, RADEON_USAGE_READ,
 272                 RADEON_PRIO_SHADER_DATA);
 273
 274         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 275         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 276         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 277         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 278                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 279                 |  S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64));
 280
 281         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 282         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 283         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 284
 285         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 286                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 287         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 288                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 289         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 290                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 291
 292         /* Global buffers */
 293         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 294                 struct r600_resource *buffer =
 295                                 (struct r600_resource*)program->global_buffers[i];
 296                 if (!buffer) {
 297                         continue;
 298                 }
 299                 si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
 300         }
 301
 302         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 303          * and is now per pipe, so it should be handled in the
 304          * kernel if we want to use something other than the default value,
 305          * which is now 0x22f.
 306          */
 307         if (sctx->b.chip_class <= SI) {
 308                 /* XXX: This should be:
 309                  * (number of compute units) * 4 * (waves per simd) - 1 */
 310
 311                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 312                                                 0x190 /* Default value */);
 313         }
 314
 315         shader_va = shader->bo->gpu_address;
 316
 317 #if HAVE_LLVM >= 0x0306
 318         shader_va += pc;
 319 #endif
 320         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 321         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 322         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 323
 324         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 325                 /* We always use at least 3 VGPRS, these come from
 326                  * TIDIG_COMP_CNT.
 327                  * XXX: The compiler should account for this.
 328                  */
 329                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 330                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 331                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 332                  * XXX: The compiler should account for this.
 333                  */
 334                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 335                                         shader->num_sgprs)) - 1) / 8))
 336                 ;
 337
 338         lds_blocks = shader->lds_size;
 339         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 340          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 341          * the shader and 4 bytes allocated by the state tracker, then
 342          * we will set LDS_SIZE to 512 bytes rather than 256.
 343          */
 344         if (sctx->b.chip_class <= SI) {
 345                 lds_blocks += align(program->local_size, 256) >> 8;
 346         } else {
 347                 lds_blocks += align(program->local_size, 512) >> 9;
 348         }
 349
 350         assert(lds_blocks <= 0xFF);
 351
 352         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 353                 S_00B84C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0)
 354                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 355                 | S_00B84C_TGID_X_EN(1)
 356                 | S_00B84C_TGID_Y_EN(1)
 357                 | S_00B84C_TGID_Z_EN(1)
 358                 | S_00B84C_TG_SIZE_EN(1)
 359                 | S_00B84C_TIDIG_COMP_CNT(2)
 360                 | S_00B84C_LDS_SIZE(lds_blocks)
 361                 | S_00B84C_EXCP_EN(0))
 362                 ;
 363         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 364
 365         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 366                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 367                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 368                 ;
 369
 370         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 371                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 372                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 373                 ;
 374
 375         num_waves_for_scratch =
 376                 MIN2(num_waves_for_scratch,
 377                      32 * sctx->screen->b.info.max_compute_units);
 378         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 379                 /* The maximum value for WAVES is 32 * num CU.
 380                  * If you program this value incorrectly, the GPU will hang if
 381                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 382                  */
 383                 S_00B860_WAVES(num_waves_for_scratch)
 384                 | S_00B860_WAVESIZE(shader->scratch_bytes_per_wave >> 10))
 385                 ;
 386
 387         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 388         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 389         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 390         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 391         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 392         si_pm4_cmd_end(pm4, false);
 393
 394         si_pm4_emit(sctx, pm4);
 395
 396 #if 0
 397         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 398         for (i = 0; i < sctx->cs->cdw; i++) {
 399                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 400         }
 401 #endif
 402
 403         si_pm4_free_state(sctx, pm4, ~0);
 404
 405         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 406                          SI_CONTEXT_INV_TC_L1 |
 407                          SI_CONTEXT_INV_TC_L2 |
 408                          SI_CONTEXT_INV_ICACHE |
 409                          SI_CONTEXT_INV_KCACHE |
 410                          SI_CONTEXT_FLAG_COMPUTE;
 411         si_emit_cache_flush(&sctx->b, NULL);
 412 }
 413
 414
 415 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 416         struct si_compute *program = (struct si_compute *)state;
 417
 418         if (!state) {
 419                 return;
 420         }
 421
 422 #if HAVE_LLVM < 0x0306
 423         if (program->kernels) {
 424                 for (int i = 0; i < program->num_kernels; i++){
 425                         if (program->kernels[i].bo){
 426                                 si_shader_destroy(ctx, &program->kernels[i]);
 427                         }
 428                 }
 429                 FREE(program->kernels);
 430         }
 431
 432         if (program->llvm_ctx){
 433                 LLVMContextDispose(program->llvm_ctx);
 434         }
 435 #else
 436         si_shader_destroy(ctx, &program->program);
 437 #endif
 438
 439         pipe_resource_reference(
 440                 (struct pipe_resource **)&program->input_buffer, NULL);
 441
 442         radeon_shader_binary_free_members(&program->binary, true);
 443         FREE(program);
 444 }
 445
 446 static void si_set_compute_resources(struct pipe_context * ctx_,
 447                 unsigned start, unsigned count,
 448                 struct pipe_surface ** surfaces) { }
 449
 450 void si_init_compute_functions(struct si_context *sctx)
 451 {
 452         sctx->b.b.create_compute_state = si_create_compute_state;
 453         sctx->b.b.delete_compute_state = si_delete_compute_state;
 454         sctx->b.b.bind_compute_state = si_bind_compute_state;
 455 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 456         sctx->b.b.set_compute_resources = si_set_compute_resources;
 457         sctx->b.b.set_global_binding = si_set_global_binding;
 458         sctx->b.b.launch_grid = si_launch_grid;
 459 }