src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_memory.h"
  26 #include "radeon/r600_pipe_common.h"
  27 #include "radeon/radeon_elf_util.h"
  28 #include "radeon/radeon_llvm_util.h"
  29
  30 #include "radeon/r600_cs.h"
  31 #include "si_pipe.h"
  32 #include "si_shader.h"
  33 #include "sid.h"
  34
  35 #define MAX_GLOBAL_BUFFERS 20
  36
  37 struct si_compute {
  38         struct si_context *ctx;
  39
  40         unsigned local_size;
  41         unsigned private_size;
  42         unsigned input_size;
  43         struct si_shader shader;
  44         unsigned num_user_sgprs;
  45
  46         struct r600_resource *input_buffer;
  47         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  48
  49 #if HAVE_LLVM < 0x0306
  50         unsigned num_kernels;
  51         struct si_shader *kernels;
  52         LLVMContextRef llvm_ctx;
  53 #endif
  54 };
  55
  56 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
  57 {
  58         unsigned scratch_bytes = 0;
  59         uint64_t scratch_buffer_va;
  60         unsigned i;
  61
  62         /* Compute the scratch buffer size using the maximum number of waves.
  63          * This way we don't need to recompute it for each kernel launch. */
  64         unsigned scratch_waves = 32 * sctx->screen->b.info.max_compute_units;
  65         for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
  66                 unsigned offset =
  67                                 program->shader.binary.global_symbol_offsets[i];
  68                 unsigned scratch_bytes_needed;
  69
  70                 si_shader_binary_read_config(&program->shader.binary,
  71                                              &program->shader.config, offset);
  72                 scratch_bytes_needed = program->shader.config.scratch_bytes_per_wave;
  73                 scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
  74         }
  75
  76         if (scratch_bytes == 0)
  77                 return;
  78
  79         program->shader.scratch_bo =
  80                                 si_resource_create_custom(sctx->b.b.screen,
  81                                 PIPE_USAGE_DEFAULT,
  82                                 scratch_bytes * scratch_waves);
  83
  84         scratch_buffer_va = program->shader.scratch_bo->gpu_address;
  85
  86         /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
  87          * to the maximum bytes needed, so it can compute the stride
  88          * correctly.
  89          */
  90         program->shader.config.scratch_bytes_per_wave = scratch_bytes;
  91
  92         /* Patch the shader with the scratch buffer address. */
  93         si_shader_apply_scratch_relocs(sctx,
  94                                 &program->shader, scratch_buffer_va);
  95 }
  96
  97 static void *si_create_compute_state(
  98         struct pipe_context *ctx,
  99         const struct pipe_compute_state *cso)
 100 {
 101         struct si_context *sctx = (struct si_context *)ctx;
 102         struct si_compute *program = CALLOC_STRUCT(si_compute);
 103         const struct pipe_llvm_program_header *header;
 104         const char *code;
 105
 106         header = cso->prog;
 107         code = cso->prog + sizeof(struct pipe_llvm_program_header);
 108
 109         program->ctx = sctx;
 110         program->local_size = cso->req_local_mem;
 111         program->private_size = cso->req_private_mem;
 112         program->input_size = cso->req_input_mem;
 113
 114 #if HAVE_LLVM < 0x0306
 115         {
 116                 unsigned i;
 117                 program->llvm_ctx = LLVMContextCreate();
 118                 program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
 119                                         code, header->num_bytes);
 120                 program->kernels = CALLOC(sizeof(struct si_shader),
 121                                                         program->num_kernels);
 122                 for (i = 0; i < program->num_kernels; i++) {
 123                         LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
 124                                                         code, header->num_bytes);
 125                         si_compile_llvm(sctx->screen, &program->kernels[i].binary,
 126                                         &program->kernels[i].config, sctx->tm,
 127                                         mod, &sctx->b.debug, TGSI_PROCESSOR_COMPUTE);
 128                         si_shader_dump(sctx->screen, &program->kernels[i],
 129                                        &sctx->b.debug, TGSI_PROCESSOR_COMPUTE);
 130                         si_shader_binary_upload(sctx->screen, &program->kernels[i]);
 131                         LLVMDisposeModule(mod);
 132                 }
 133         }
 134 #else
 135
 136         radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 137
 138         /* init_scratch_buffer patches the shader code with the scratch address,
 139          * so we need to call it before si_shader_binary_read() which uploads
 140          * the shader code to the GPU.
 141          */
 142         init_scratch_buffer(sctx, program);
 143         si_shader_binary_read_config(&program->shader.binary,
 144                                      &program->shader.config, 0);
 145         si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 146                        TGSI_PROCESSOR_COMPUTE);
 147         si_shader_binary_upload(sctx->screen, &program->shader);
 148
 149 #endif
 150         program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
 151                 PIPE_USAGE_IMMUTABLE, program->input_size);
 152
 153         return program;
 154 }
 155
 156 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 157 {
 158         struct si_context *sctx = (struct si_context*)ctx;
 159         sctx->cs_shader_state.program = (struct si_compute*)state;
 160 }
 161
 162 static void si_set_global_binding(
 163         struct pipe_context *ctx, unsigned first, unsigned n,
 164         struct pipe_resource **resources,
 165         uint32_t **handles)
 166 {
 167         unsigned i;
 168         struct si_context *sctx = (struct si_context*)ctx;
 169         struct si_compute *program = sctx->cs_shader_state.program;
 170
 171         if (!resources) {
 172                 for (i = first; i < first + n; i++) {
 173                         pipe_resource_reference(&program->global_buffers[i], NULL);
 174                 }
 175                 return;
 176         }
 177
 178         for (i = first; i < first + n; i++) {
 179                 uint64_t va;
 180                 uint32_t offset;
 181                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 182                 va = r600_resource(resources[i])->gpu_address;
 183                 offset = util_le32_to_cpu(*handles[i]);
 184                 va += offset;
 185                 va = util_cpu_to_le64(va);
 186                 memcpy(handles[i], &va, sizeof(va));
 187         }
 188 }
 189
 190 /**
 191  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 192  * /p block_layout is the number of threads in each work group.
 193  * /p grid layout is the number of work groups.
 194  */
 195 static unsigned compute_num_waves_for_scratch(
 196                 const struct radeon_info *info,
 197                 const uint *block_layout,
 198                 const uint *grid_layout)
 199 {
 200         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 201         unsigned num_se = MAX2(info->max_se, 1);
 202         unsigned num_blocks = 1;
 203         unsigned threads_per_block = 1;
 204         unsigned waves_per_block;
 205         unsigned waves_per_sh;
 206         unsigned waves;
 207         unsigned scratch_waves;
 208         unsigned i;
 209
 210         for (i = 0; i < 3; i++) {
 211                 threads_per_block *= block_layout[i];
 212                 num_blocks *= grid_layout[i];
 213         }
 214
 215         waves_per_block = align(threads_per_block, 64) / 64;
 216         waves = waves_per_block * num_blocks;
 217         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 218         scratch_waves = waves_per_sh * num_sh * num_se;
 219
 220         if (waves_per_block > waves_per_sh) {
 221                 scratch_waves = waves_per_block * num_sh * num_se;
 222         }
 223
 224         return scratch_waves;
 225 }
 226
 227 static void si_launch_grid(
 228                 struct pipe_context *ctx,
 229                 const uint *block_layout, const uint *grid_layout,
 230                 uint32_t pc, const void *input)
 231 {
 232         struct si_context *sctx = (struct si_context*)ctx;
 233         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 234         struct si_compute *program = sctx->cs_shader_state.program;
 235         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 236         struct r600_resource *input_buffer = program->input_buffer;
 237         unsigned kernel_args_size;
 238         unsigned num_work_size_bytes = 36;
 239         uint32_t kernel_args_offset = 0;
 240         uint32_t *kernel_args;
 241         uint64_t kernel_args_va;
 242         uint64_t scratch_buffer_va = 0;
 243         uint64_t shader_va;
 244         unsigned i;
 245         struct si_shader *shader = &program->shader;
 246         unsigned lds_blocks;
 247         unsigned num_waves_for_scratch;
 248
 249 #if HAVE_LLVM < 0x0306
 250         shader = &program->kernels[pc];
 251 #endif
 252
 253
 254         radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 255         radeon_emit(cs, 0x80000000);
 256         radeon_emit(cs, 0x80000000);
 257
 258         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
 259                          SI_CONTEXT_INV_GLOBAL_L2 |
 260                          SI_CONTEXT_INV_ICACHE |
 261                          SI_CONTEXT_INV_SMEM_L1 |
 262                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 263                          SI_CONTEXT_FLAG_COMPUTE;
 264         si_emit_cache_flush(sctx, NULL);
 265
 266         pm4->compute_pkt = true;
 267
 268 #if HAVE_LLVM >= 0x0306
 269         /* Read the config information */
 270         si_shader_binary_read_config(&shader->binary, &shader->config, pc);
 271 #endif
 272
 273         /* Upload the kernel arguments */
 274
 275         /* The extra num_work_size_bytes are for work group / work item size information */
 276         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 277
 278         kernel_args = sctx->b.ws->buffer_map(input_buffer->buf,
 279                         sctx->b.gfx.cs, PIPE_TRANSFER_WRITE);
 280         for (i = 0; i < 3; i++) {
 281                 kernel_args[i] = grid_layout[i];
 282                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 283                 kernel_args[i + 6] = block_layout[i];
 284         }
 285
 286         num_waves_for_scratch = compute_num_waves_for_scratch(
 287                 &sctx->screen->b.info, block_layout, grid_layout);
 288
 289         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 290
 291         if (shader->config.scratch_bytes_per_wave > 0) {
 292
 293                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 294                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 295                             shader->config.scratch_bytes_per_wave,
 296                             shader->config.scratch_bytes_per_wave *
 297                             num_waves_for_scratch);
 298
 299                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 300                                           shader->scratch_bo,
 301                                           RADEON_USAGE_READWRITE,
 302                                           RADEON_PRIO_SCRATCH_BUFFER);
 303
 304                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 305         }
 306
 307         for (i = 0; i < (kernel_args_size / 4); i++) {
 308                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 309                         kernel_args[i]);
 310         }
 311
 312         kernel_args_va = input_buffer->gpu_address;
 313         kernel_args_va += kernel_args_offset;
 314
 315         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 316                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 317
 318         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 319         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 320         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 321         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 322                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 323                 |  S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64));
 324
 325         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 326         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 327         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 328
 329         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 330                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 331         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 332                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 333         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 334                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 335
 336         /* Global buffers */
 337         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 338                 struct r600_resource *buffer =
 339                                 (struct r600_resource*)program->global_buffers[i];
 340                 if (!buffer) {
 341                         continue;
 342                 }
 343                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 344                                           RADEON_USAGE_READWRITE,
 345                                           RADEON_PRIO_COMPUTE_GLOBAL);
 346         }
 347
 348         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 349          * and is now per pipe, so it should be handled in the
 350          * kernel if we want to use something other than the default value,
 351          * which is now 0x22f.
 352          */
 353         if (sctx->b.chip_class <= SI) {
 354                 /* XXX: This should be:
 355                  * (number of compute units) * 4 * (waves per simd) - 1 */
 356
 357                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 358                                                 0x190 /* Default value */);
 359         }
 360
 361         shader_va = shader->bo->gpu_address;
 362
 363 #if HAVE_LLVM >= 0x0306
 364         shader_va += pc;
 365 #endif
 366         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 367                                   RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 368         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
 369         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 370
 371         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->config.rsrc1);
 372
 373         lds_blocks = shader->config.lds_size;
 374         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 375          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 376          * the shader and 4 bytes allocated by the state tracker, then
 377          * we will set LDS_SIZE to 512 bytes rather than 256.
 378          */
 379         if (sctx->b.chip_class <= SI) {
 380                 lds_blocks += align(program->local_size, 256) >> 8;
 381         } else {
 382                 lds_blocks += align(program->local_size, 512) >> 9;
 383         }
 384
 385         assert(lds_blocks <= 0xFF);
 386
 387         shader->config.rsrc2 &= C_00B84C_LDS_SIZE;
 388         shader->config.rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 389
 390         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->config.rsrc2);
 391         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 392
 393         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 394                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 395                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 396                 ;
 397
 398         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 399                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 400                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 401                 ;
 402
 403         num_waves_for_scratch =
 404                 MIN2(num_waves_for_scratch,
 405                      32 * sctx->screen->b.info.max_compute_units);
 406         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 407                 /* The maximum value for WAVES is 32 * num CU.
 408                  * If you program this value incorrectly, the GPU will hang if
 409                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 410                  */
 411                 S_00B860_WAVES(num_waves_for_scratch)
 412                 | S_00B860_WAVESIZE(shader->config.scratch_bytes_per_wave >> 10))
 413                 ;
 414
 415         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 416         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 417         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 418         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 419         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 420         si_pm4_cmd_end(pm4, false);
 421
 422         si_pm4_emit(sctx, pm4);
 423
 424 #if 0
 425         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 426         for (i = 0; i < sctx->cs->cdw; i++) {
 427                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 428         }
 429 #endif
 430
 431         si_pm4_free_state(sctx, pm4, ~0);
 432
 433         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 434                          SI_CONTEXT_INV_VMEM_L1 |
 435                          SI_CONTEXT_INV_GLOBAL_L2 |
 436                          SI_CONTEXT_INV_ICACHE |
 437                          SI_CONTEXT_INV_SMEM_L1 |
 438                          SI_CONTEXT_FLAG_COMPUTE;
 439         si_emit_cache_flush(sctx, NULL);
 440 }
 441
 442
 443 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 444         struct si_compute *program = (struct si_compute *)state;
 445
 446         if (!state) {
 447                 return;
 448         }
 449
 450 #if HAVE_LLVM < 0x0306
 451         if (program->kernels) {
 452                 for (int i = 0; i < program->num_kernels; i++){
 453                         if (program->kernels[i].bo){
 454                                 si_shader_destroy(&program->kernels[i]);
 455                         }
 456                 }
 457                 FREE(program->kernels);
 458         }
 459
 460         if (program->llvm_ctx){
 461                 LLVMContextDispose(program->llvm_ctx);
 462         }
 463 #else
 464         FREE(program->shader.binary.config);
 465         FREE(program->shader.binary.rodata);
 466         FREE(program->shader.binary.global_symbol_offsets);
 467         si_shader_destroy(&program->shader);
 468 #endif
 469
 470         pipe_resource_reference(
 471                 (struct pipe_resource **)&program->input_buffer, NULL);
 472
 473         FREE(program);
 474 }
 475
 476 static void si_set_compute_resources(struct pipe_context * ctx_,
 477                 unsigned start, unsigned count,
 478                 struct pipe_surface ** surfaces) { }
 479
 480 void si_init_compute_functions(struct si_context *sctx)
 481 {
 482         sctx->b.b.create_compute_state = si_create_compute_state;
 483         sctx->b.b.delete_compute_state = si_delete_compute_state;
 484         sctx->b.b.bind_compute_state = si_bind_compute_state;
 485 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 486         sctx->b.b.set_compute_resources = si_set_compute_resources;
 487         sctx->b.b.set_global_binding = si_set_global_binding;
 488         sctx->b.b.launch_grid = si_launch_grid;
 489 }