src/gallium/drivers/radeonsi/si_compute.c

   1 #include "util/u_memory.h"
   2
   3 #include "../radeon/r600_cs.h"
   4 #include "si_pipe.h"
   5 #include "si_shader.h"
   6
   7 #include "radeon_llvm_util.h"
   8
   9 #define MAX_GLOBAL_BUFFERS 20
  10
  11 struct si_pipe_compute {
  12         struct si_context *ctx;
  13
  14         unsigned local_size;
  15         unsigned private_size;
  16         unsigned input_size;
  17         unsigned num_kernels;
  18         struct si_pipe_shader *kernels;
  19         unsigned num_user_sgprs;
  20
  21         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  22
  23         LLVMContextRef llvm_ctx;
  24 };
  25
  26 static void *radeonsi_create_compute_state(
  27         struct pipe_context *ctx,
  28         const struct pipe_compute_state *cso)
  29 {
  30         struct si_context *rctx = (struct si_context *)ctx;
  31         struct si_pipe_compute *program =
  32                                         CALLOC_STRUCT(si_pipe_compute);
  33         const struct pipe_llvm_program_header *header;
  34         const unsigned char *code;
  35         unsigned i;
  36
  37         program->llvm_ctx = LLVMContextCreate();
  38
  39         header = cso->prog;
  40         code = cso->prog + sizeof(struct pipe_llvm_program_header);
  41
  42         program->ctx = rctx;
  43         program->local_size = cso->req_local_mem;
  44         program->private_size = cso->req_private_mem;
  45         program->input_size = cso->req_input_mem;
  46
  47         program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx, code,
  48                                                         header->num_bytes);
  49         program->kernels = CALLOC(sizeof(struct si_pipe_shader),
  50                                                         program->num_kernels);
  51         for (i = 0; i < program->num_kernels; i++) {
  52                 LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
  53                                                         code, header->num_bytes);
  54                 si_compile_llvm(rctx, &program->kernels[i], mod);
  55                 LLVMDisposeModule(mod);
  56         }
  57
  58         return program;
  59 }
  60
  61 static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state)
  62 {
  63         struct si_context *rctx = (struct si_context*)ctx;
  64         rctx->cs_shader_state.program = (struct si_pipe_compute*)state;
  65 }
  66
  67 static void radeonsi_set_global_binding(
  68         struct pipe_context *ctx, unsigned first, unsigned n,
  69         struct pipe_resource **resources,
  70         uint32_t **handles)
  71 {
  72         unsigned i;
  73         struct si_context *rctx = (struct si_context*)ctx;
  74         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  75
  76         if (!resources) {
  77                 for (i = first; i < first + n; i++) {
  78                         program->global_buffers[i] = NULL;
  79                 }
  80                 return;
  81         }
  82
  83         for (i = first; i < first + n; i++) {
  84                 uint64_t va;
  85                 program->global_buffers[i] = resources[i];
  86                 va = r600_resource_va(ctx->screen, resources[i]);
  87                 memcpy(handles[i], &va, sizeof(va));
  88         }
  89 }
  90
  91 static void radeonsi_launch_grid(
  92                 struct pipe_context *ctx,
  93                 const uint *block_layout, const uint *grid_layout,
  94                 uint32_t pc, const void *input)
  95 {
  96         struct si_context *rctx = (struct si_context*)ctx;
  97         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  98         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
  99         struct r600_resource *kernel_args_buffer = NULL;
 100         unsigned kernel_args_size;
 101         unsigned num_work_size_bytes = 36;
 102         uint32_t kernel_args_offset = 0;
 103         uint32_t *kernel_args;
 104         uint64_t kernel_args_va;
 105         uint64_t shader_va;
 106         unsigned arg_user_sgpr_count = 2;
 107         unsigned i;
 108         struct si_pipe_shader *shader = &program->kernels[pc];
 109         unsigned lds_blocks;
 110
 111         pm4->compute_pkt = true;
 112         si_cmd_context_control(pm4);
 113
 114         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 115         si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
 116                             EVENT_INDEX(0x7) |
 117                             EVENT_WRITE_INV_L2);
 118         si_pm4_cmd_end(pm4, false);
 119
 120         si_pm4_inval_texture_cache(pm4);
 121         si_pm4_inval_shader_cache(pm4);
 122         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 123
 124         /* Upload the kernel arguments */
 125
 126         /* The extra num_work_size_bytes are for work group / work item size information */
 127         kernel_args_size = program->input_size + num_work_size_bytes;
 128         kernel_args = MALLOC(kernel_args_size);
 129         for (i = 0; i < 3; i++) {
 130                 kernel_args[i] = grid_layout[i];
 131                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 132                 kernel_args[i + 6] = block_layout[i];
 133         }
 134
 135         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 136
 137         si_upload_const_buffer(rctx, &kernel_args_buffer, (uint8_t*)kernel_args,
 138                                         kernel_args_size, &kernel_args_offset);
 139         kernel_args_va = r600_resource_va(ctx->screen,
 140                                 (struct pipe_resource*)kernel_args_buffer);
 141         kernel_args_va += kernel_args_offset;
 142
 143         si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ);
 144
 145         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 146         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 147
 148         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 149         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 150         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 151
 152         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 153                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 154         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 155                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 156         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 157                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 158
 159         /* Global buffers */
 160         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 161                 struct r600_resource *buffer =
 162                                 (struct r600_resource*)program->global_buffers[i];
 163                 if (!buffer) {
 164                         continue;
 165                 }
 166                 si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
 167         }
 168
 169         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 170          * and is now per pipe, so it should be handled in the
 171          * kernel if we want to use something other than the default value,
 172          * which is now 0x22f.
 173          */
 174         if (rctx->b.chip_class <= SI) {
 175                 /* XXX: This should be:
 176                  * (number of compute units) * 4 * (waves per simd) - 1 */
 177
 178                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 179                                                 0x190 /* Default value */);
 180         }
 181
 182         shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
 183         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
 184         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 185         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 186
 187         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 188                 /* We always use at least 3 VGPRS, these come from
 189                  * TIDIG_COMP_CNT.
 190                  * XXX: The compiler should account for this.
 191                  */
 192                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 193                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 194                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 195                  * XXX: The compiler should account for this.
 196                  */
 197                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 198                                         shader->num_sgprs)) - 1) / 8))
 199                 ;
 200
 201         lds_blocks = shader->lds_size;
 202         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 203          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 204          * the shader and 4 bytes allocated by the state tracker, then
 205          * we will set LDS_SIZE to 512 bytes rather than 256.
 206          */
 207         if (rctx->b.chip_class <= SI) {
 208                 lds_blocks += align(program->local_size, 256) >> 8;
 209         } else {
 210                 lds_blocks += align(program->local_size, 512) >> 9;
 211         }
 212
 213         assert(lds_blocks <= 0xFF);
 214
 215         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 216                 S_00B84C_SCRATCH_EN(0)
 217                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 218                 | S_00B84C_TGID_X_EN(1)
 219                 | S_00B84C_TGID_Y_EN(1)
 220                 | S_00B84C_TGID_Z_EN(1)
 221                 | S_00B84C_TG_SIZE_EN(1)
 222                 | S_00B84C_TIDIG_COMP_CNT(2)
 223                 | S_00B84C_LDS_SIZE(lds_blocks)
 224                 | S_00B84C_EXCP_EN(0))
 225                 ;
 226         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 227
 228         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 229                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 230                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 231                 ;
 232
 233         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 234                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 235                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 236                 ;
 237
 238         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 239         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 240         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 241         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 242         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 243         si_pm4_cmd_end(pm4, false);
 244
 245         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 246         si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
 247         si_pm4_cmd_end(pm4, false);
 248
 249         si_pm4_inval_texture_cache(pm4);
 250         si_pm4_inval_shader_cache(pm4);
 251         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 252
 253         si_pm4_emit(rctx, pm4);
 254
 255 #if 0
 256         fprintf(stderr, "cdw: %i\n", rctx->cs->cdw);
 257         for (i = 0; i < rctx->cs->cdw; i++) {
 258                 fprintf(stderr, "%4i : 0x%08X\n", i, rctx->cs->buf[i]);
 259         }
 260 #endif
 261
 262         FREE(pm4);
 263         FREE(kernel_args);
 264 }
 265
 266
 267 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 268         struct si_pipe_compute *program = (struct si_pipe_compute *)state;
 269
 270         if (!state) {
 271                 return;
 272         }
 273
 274         if (program->kernels) {
 275                 FREE(program->kernels);
 276         }
 277
 278         if (program->llvm_ctx){
 279                 LLVMContextDispose(program->llvm_ctx);
 280         }
 281
 282         //And then free the program itself.
 283         FREE(program);
 284 }
 285
 286 static void si_set_compute_resources(struct pipe_context * ctx_,
 287                 unsigned start, unsigned count,
 288                 struct pipe_surface ** surfaces) { }
 289
 290 void si_init_compute_functions(struct si_context *rctx)
 291 {
 292         rctx->b.b.create_compute_state = radeonsi_create_compute_state;
 293         rctx->b.b.delete_compute_state = si_delete_compute_state;
 294         rctx->b.b.bind_compute_state = radeonsi_bind_compute_state;
 295 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 296         rctx->b.b.set_compute_resources = si_set_compute_resources;
 297         rctx->b.b.set_global_binding = radeonsi_set_global_binding;
 298         rctx->b.b.launch_grid = radeonsi_launch_grid;
 299 }