src/gallium/drivers/radeonsi/si_compute_blit.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "si_pipe.h"
  27 #include "util/u_format.h"
  28 #include "util/format_srgb.h"
  29
  30 /* Note: Compute shaders always use SI_COMPUTE_DST_CACHE_POLICY for dst
  31  * and L2_STREAM for src.
  32  */
  33 static enum si_cache_policy get_cache_policy(struct si_context *sctx,
  34                                              enum si_coherency coher,
  35                                              uint64_t size)
  36 {
  37         if ((sctx->chip_class >= GFX9 && (coher == SI_COHERENCY_CB_META ||
  38                                           coher == SI_COHERENCY_CP)) ||
  39             (sctx->chip_class >= CIK && coher == SI_COHERENCY_SHADER))
  40                 return size <= 256 * 1024 ? L2_LRU : L2_STREAM;
  41
  42         return L2_BYPASS;
  43 }
  44
  45 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
  46                             enum si_cache_policy cache_policy)
  47 {
  48         switch (coher) {
  49         default:
  50         case SI_COHERENCY_NONE:
  51         case SI_COHERENCY_CP:
  52                 return 0;
  53         case SI_COHERENCY_SHADER:
  54                 return SI_CONTEXT_INV_SMEM_L1 |
  55                        SI_CONTEXT_INV_VMEM_L1 |
  56                        (cache_policy == L2_BYPASS ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
  57         case SI_COHERENCY_CB_META:
  58                 return SI_CONTEXT_FLUSH_AND_INV_CB;
  59         }
  60 }
  61
  62 static void si_compute_internal_begin(struct si_context *sctx)
  63 {
  64         sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
  65         sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
  66         sctx->render_cond_force_off = true;
  67 }
  68
  69 static void si_compute_internal_end(struct si_context *sctx)
  70 {
  71         sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
  72         sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
  73         sctx->render_cond_force_off = false;
  74 }
  75
  76 static void si_compute_do_clear_or_copy(struct si_context *sctx,
  77                                         struct pipe_resource *dst,
  78                                         unsigned dst_offset,
  79                                         struct pipe_resource *src,
  80                                         unsigned src_offset,
  81                                         unsigned size,
  82                                         const uint32_t *clear_value,
  83                                         unsigned clear_value_size,
  84                                         enum si_coherency coher)
  85 {
  86         struct pipe_context *ctx = &sctx->b;
  87
  88         assert(src_offset % 4 == 0);
  89         assert(dst_offset % 4 == 0);
  90         assert(size % 4 == 0);
  91
  92         assert(dst->target != PIPE_BUFFER || dst_offset + size <= dst->width0);
  93         assert(!src || src_offset + size <= src->width0);
  94
  95         si_compute_internal_begin(sctx);
  96         sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  97                        SI_CONTEXT_CS_PARTIAL_FLUSH |
  98                        si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
  99
 100         /* Save states. */
 101         void *saved_cs = sctx->cs_shader_state.program;
 102         struct pipe_shader_buffer saved_sb[2] = {};
 103         si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb);
 104
 105         /* The memory accesses are coalesced, meaning that the 1st instruction writes
 106          * the 1st contiguous block of data for the whole wave, the 2nd instruction
 107          * writes the 2nd contiguous block of data, etc.
 108          */
 109         unsigned dwords_per_thread = src ? SI_COMPUTE_COPY_DW_PER_THREAD :
 110                                            SI_COMPUTE_CLEAR_DW_PER_THREAD;
 111         unsigned instructions_per_thread = MAX2(1, dwords_per_thread / 4);
 112         unsigned dwords_per_instruction = dwords_per_thread / instructions_per_thread;
 113         unsigned dwords_per_wave = dwords_per_thread * 64;
 114
 115         unsigned num_dwords = size / 4;
 116         unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction);
 117
 118         struct pipe_grid_info info = {};
 119         info.block[0] = MIN2(64, num_instructions);
 120         info.block[1] = 1;
 121         info.block[2] = 1;
 122         info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave);
 123         info.grid[1] = 1;
 124         info.grid[2] = 1;
 125
 126         struct pipe_shader_buffer sb[2] = {};
 127         sb[0].buffer = dst;
 128         sb[0].buffer_offset = dst_offset;
 129         sb[0].buffer_size = size;
 130
 131         bool shader_dst_stream_policy = SI_COMPUTE_DST_CACHE_POLICY != L2_LRU;
 132
 133         if (src) {
 134                 sb[1].buffer = src;
 135                 sb[1].buffer_offset = src_offset;
 136                 sb[1].buffer_size = size;
 137
 138                 ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 2, sb, 0x1);
 139
 140                 if (!sctx->cs_copy_buffer) {
 141                         sctx->cs_copy_buffer = si_create_dma_compute_shader(&sctx->b,
 142                                                              SI_COMPUTE_COPY_DW_PER_THREAD,
 143                                                              shader_dst_stream_policy, true);
 144                 }
 145                 ctx->bind_compute_state(ctx, sctx->cs_copy_buffer);
 146         } else {
 147                 assert(clear_value_size >= 4 &&
 148                        clear_value_size <= 16 &&
 149                        util_is_power_of_two_or_zero(clear_value_size));
 150
 151                 for (unsigned i = 0; i < 4; i++)
 152                         sctx->cs_user_data[i] = clear_value[i % (clear_value_size / 4)];
 153
 154                 ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, sb, 0x1);
 155
 156                 if (!sctx->cs_clear_buffer) {
 157                         sctx->cs_clear_buffer = si_create_dma_compute_shader(&sctx->b,
 158                                                              SI_COMPUTE_CLEAR_DW_PER_THREAD,
 159                                                              shader_dst_stream_policy, false);
 160                 }
 161                 ctx->bind_compute_state(ctx, sctx->cs_clear_buffer);
 162         }
 163
 164         ctx->launch_grid(ctx, &info);
 165
 166         enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, size);
 167         sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 168                        (cache_policy == L2_BYPASS ? SI_CONTEXT_WRITEBACK_GLOBAL_L2 : 0);
 169
 170         if (cache_policy != L2_BYPASS)
 171                 si_resource(dst)->TC_L2_dirty = true;
 172
 173         /* Restore states. */
 174         ctx->bind_compute_state(ctx, saved_cs);
 175         ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb, ~0);
 176         si_compute_internal_end(sctx);
 177 }
 178
 179 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 180                      uint64_t offset, uint64_t size, uint32_t *clear_value,
 181                      uint32_t clear_value_size, enum si_coherency coher)
 182 {
 183         if (!size)
 184                 return;
 185
 186         unsigned clear_alignment = MIN2(clear_value_size, 4);
 187
 188         assert(clear_value_size != 3 && clear_value_size != 6); /* 12 is allowed. */
 189         assert(offset % clear_alignment == 0);
 190         assert(size % clear_alignment == 0);
 191         assert(size < (UINT_MAX & ~0xf)); /* TODO: test 64-bit sizes in all codepaths */
 192
 193         /* Reduce a large clear value size if possible. */
 194         if (clear_value_size > 4) {
 195                 bool clear_dword_duplicated = true;
 196
 197                 /* See if we can lower large fills to dword fills. */
 198                 for (unsigned i = 1; i < clear_value_size / 4; i++) {
 199                         if (clear_value[0] != clear_value[i]) {
 200                                 clear_dword_duplicated = false;
 201                                 break;
 202                         }
 203                 }
 204                 if (clear_dword_duplicated)
 205                         clear_value_size = 4;
 206         }
 207
 208         /* Expand a small clear value size. */
 209         uint32_t tmp_clear_value;
 210         if (clear_value_size <= 2) {
 211                 if (clear_value_size == 1) {
 212                         tmp_clear_value = *(uint8_t*)clear_value;
 213                         tmp_clear_value |= (tmp_clear_value << 8) |
 214                                            (tmp_clear_value << 16) |
 215                                            (tmp_clear_value << 24);
 216                 } else {
 217                         tmp_clear_value = *(uint16_t*)clear_value;
 218                         tmp_clear_value |= tmp_clear_value << 16;
 219                 }
 220                 clear_value = &tmp_clear_value;
 221                 clear_value_size = 4;
 222         }
 223
 224         /* Use transform feedback for 12-byte clears. */
 225         /* TODO: Use compute. */
 226         if (clear_value_size == 12) {
 227                 union pipe_color_union streamout_clear_value;
 228
 229                 memcpy(&streamout_clear_value, clear_value, clear_value_size);
 230                 si_blitter_begin(sctx, SI_DISABLE_RENDER_COND);
 231                 util_blitter_clear_buffer(sctx->blitter, dst, offset,
 232                                           size, clear_value_size / 4,
 233                                           &streamout_clear_value);
 234                 si_blitter_end(sctx);
 235                 return;
 236         }
 237
 238         uint64_t aligned_size = size & ~3ull;
 239         if (aligned_size >= 4) {
 240                 /* Before GFX9, CP DMA was very slow when clearing GTT, so never
 241                  * use CP DMA clears on those chips, because we can't be certain
 242                  * about buffer placements.
 243                  */
 244                 if (clear_value_size > 4 ||
 245                     (clear_value_size == 4 &&
 246                      offset % 4 == 0 &&
 247                      (size > 32*1024 || sctx->chip_class <= VI))) {
 248                         si_compute_do_clear_or_copy(sctx, dst, offset, NULL, 0,
 249                                                     aligned_size, clear_value,
 250                                                     clear_value_size, coher);
 251                 } else {
 252                         assert(clear_value_size == 4);
 253                         si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, dst, offset,
 254                                                aligned_size, *clear_value, 0, coher,
 255                                                get_cache_policy(sctx, coher, size));
 256                 }
 257
 258                 offset += aligned_size;
 259                 size -= aligned_size;
 260         }
 261
 262         /* Handle non-dword alignment. */
 263         if (size) {
 264                 assert(dst);
 265                 assert(dst->target == PIPE_BUFFER);
 266                 assert(size < 4);
 267
 268                 pipe_buffer_write(&sctx->b, dst, offset, size, clear_value);
 269         }
 270 }
 271
 272 static void si_pipe_clear_buffer(struct pipe_context *ctx,
 273                                  struct pipe_resource *dst,
 274                                  unsigned offset, unsigned size,
 275                                  const void *clear_value,
 276                                  int clear_value_size)
 277 {
 278         si_clear_buffer((struct si_context*)ctx, dst, offset, size, (uint32_t*)clear_value,
 279                         clear_value_size, SI_COHERENCY_SHADER);
 280 }
 281
 282 void si_copy_buffer(struct si_context *sctx,
 283                     struct pipe_resource *dst, struct pipe_resource *src,
 284                     uint64_t dst_offset, uint64_t src_offset, unsigned size)
 285 {
 286         if (!size)
 287                 return;
 288
 289         enum si_coherency coher = SI_COHERENCY_SHADER;
 290         enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, size);
 291
 292         /* Only use compute for VRAM copies on dGPUs. */
 293         if (sctx->screen->info.has_dedicated_vram &&
 294             si_resource(dst)->domains & RADEON_DOMAIN_VRAM &&
 295             si_resource(src)->domains & RADEON_DOMAIN_VRAM &&
 296             size > 32 * 1024 &&
 297             dst_offset % 4 == 0 && src_offset % 4 == 0 && size % 4 == 0) {
 298                 si_compute_do_clear_or_copy(sctx, dst, dst_offset, src, src_offset,
 299                                             size, NULL, 0, coher);
 300         } else {
 301                 si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size,
 302                                       0, coher, cache_policy);
 303         }
 304 }
 305
 306 void si_compute_copy_image(struct si_context *sctx,
 307                            struct pipe_resource *dst,
 308                            unsigned dst_level,
 309                            struct pipe_resource *src,
 310                            unsigned src_level,
 311                            unsigned dstx, unsigned dsty, unsigned dstz,
 312                            const struct pipe_box *src_box)
 313 {
 314         struct pipe_context *ctx = &sctx->b;
 315         unsigned width = src_box->width;
 316         unsigned height = src_box->height;
 317         unsigned depth = src_box->depth;
 318
 319         unsigned data[] = {src_box->x, src_box->y, src_box->z, 0, dstx, dsty, dstz, 0};
 320
 321         if (width == 0 || height == 0)
 322                 return;
 323
 324         si_compute_internal_begin(sctx);
 325         sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 326                        si_get_flush_flags(sctx, SI_COHERENCY_SHADER, L2_STREAM);
 327
 328         /* src and dst have the same number of samples. */
 329         si_make_CB_shader_coherent(sctx, src->nr_samples, true,
 330                                    /* Only src can have DCC.*/
 331                                    ((struct si_texture*)src)->surface.u.gfx9.dcc.pipe_aligned);
 332
 333         struct pipe_constant_buffer saved_cb = {};
 334         si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &saved_cb);
 335
 336         struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE];
 337         struct pipe_image_view saved_image[2] = {0};
 338         util_copy_image_view(&saved_image[0], &images->views[0]);
 339         util_copy_image_view(&saved_image[1], &images->views[1]);
 340
 341         void *saved_cs = sctx->cs_shader_state.program;
 342
 343         struct pipe_constant_buffer cb = {};
 344         cb.buffer_size = sizeof(data);
 345         cb.user_buffer = data;
 346         ctx->set_constant_buffer(ctx, PIPE_SHADER_COMPUTE, 0, &cb);
 347
 348         struct pipe_image_view image[2] = {0};
 349         image[0].resource = src;
 350         image[0].shader_access = image[0].access = PIPE_IMAGE_ACCESS_READ;
 351         image[0].format = util_format_linear(src->format);
 352         image[0].u.tex.level = src_level;
 353         image[0].u.tex.first_layer = 0;
 354         image[0].u.tex.last_layer =
 355                 src->target == PIPE_TEXTURE_3D ? u_minify(src->depth0, src_level) - 1
 356                                                 : (unsigned)(src->array_size - 1);
 357         image[1].resource = dst;
 358         image[1].shader_access = image[1].access = PIPE_IMAGE_ACCESS_WRITE;
 359         image[1].format = util_format_linear(dst->format);
 360         image[1].u.tex.level = dst_level;
 361         image[1].u.tex.first_layer = 0;
 362         image[1].u.tex.last_layer =
 363                 dst->target == PIPE_TEXTURE_3D ? u_minify(dst->depth0, dst_level) - 1
 364                                                 : (unsigned)(dst->array_size - 1);
 365
 366         if (src->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
 367                 image[0].format = image[1].format = PIPE_FORMAT_R32_UINT;
 368
 369         /* SNORM8 blitting has precision issues on some chips. Use the SINT
 370          * equivalent instead, which doesn't force DCC decompression.
 371          * Note that some chips avoid this issue by using SDMA.
 372          */
 373         if (util_format_is_snorm8(dst->format)) {
 374                 image[0].format = image[1].format =
 375                         util_format_snorm8_to_sint8(dst->format);
 376         }
 377
 378         ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 2, image);
 379
 380         struct pipe_grid_info info = {0};
 381
 382         if (dst->target == PIPE_TEXTURE_1D_ARRAY && src->target == PIPE_TEXTURE_1D_ARRAY) {
 383                 if (!sctx->cs_copy_image_1d_array)
 384                         sctx->cs_copy_image_1d_array =
 385                                 si_create_copy_image_compute_shader_1d_array(ctx);
 386                 ctx->bind_compute_state(ctx, sctx->cs_copy_image_1d_array);
 387                 info.block[0] = 64;
 388                 info.last_block[0] = width % 64;
 389                 info.block[1] = 1;
 390                 info.block[2] = 1;
 391                 info.grid[0] = DIV_ROUND_UP(width, 64);
 392                 info.grid[1] = depth;
 393                 info.grid[2] = 1;
 394         } else {
 395                 if (!sctx->cs_copy_image)
 396                         sctx->cs_copy_image = si_create_copy_image_compute_shader(ctx);
 397                 ctx->bind_compute_state(ctx, sctx->cs_copy_image);
 398                 info.block[0] = 8;
 399                 info.last_block[0] = width % 8;
 400                 info.block[1] = 8;
 401                 info.last_block[1] = height % 8;
 402                 info.block[2] = 1;
 403                 info.grid[0] = DIV_ROUND_UP(width, 8);
 404                 info.grid[1] = DIV_ROUND_UP(height, 8);
 405                 info.grid[2] = depth;
 406         }
 407
 408         ctx->launch_grid(ctx, &info);
 409
 410         sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 411                        (sctx->chip_class <= VI ? SI_CONTEXT_WRITEBACK_GLOBAL_L2 : 0) |
 412                        si_get_flush_flags(sctx, SI_COHERENCY_SHADER, L2_STREAM);
 413         ctx->bind_compute_state(ctx, saved_cs);
 414         ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 2, saved_image);
 415         ctx->set_constant_buffer(ctx, PIPE_SHADER_COMPUTE, 0, &saved_cb);
 416         si_compute_internal_end(sctx);
 417 }
 418
 419 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
 420 {
 421         struct pipe_context *ctx = &sctx->b;
 422
 423         sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 424                        SI_CONTEXT_CS_PARTIAL_FLUSH |
 425                        si_get_flush_flags(sctx, SI_COHERENCY_CB_META, L2_LRU) |
 426                        si_get_flush_flags(sctx, SI_COHERENCY_SHADER, L2_LRU);
 427         si_emit_cache_flush(sctx);
 428
 429         /* Save states. */
 430         void *saved_cs = sctx->cs_shader_state.program;
 431         struct pipe_image_view saved_img[3] = {};
 432
 433         for (unsigned i = 0; i < 3; i++) {
 434                 util_copy_image_view(&saved_img[i],
 435                                      &sctx->images[PIPE_SHADER_COMPUTE].views[i]);
 436         }
 437
 438         /* Set images. */
 439         bool use_uint16 = tex->surface.u.gfx9.dcc_retile_use_uint16;
 440         unsigned num_elements = tex->surface.u.gfx9.dcc_retile_num_elements;
 441         struct pipe_image_view img[3];
 442
 443         assert(tex->dcc_retile_map_offset && tex->dcc_retile_map_offset <= UINT_MAX);
 444         assert(tex->dcc_offset && tex->dcc_offset <= UINT_MAX);
 445         assert(tex->display_dcc_offset && tex->display_dcc_offset <= UINT_MAX);
 446
 447         for (unsigned i = 0; i < 3; i++) {
 448                 img[i].resource = &tex->buffer.b.b;
 449                 img[i].access = i == 2 ? PIPE_IMAGE_ACCESS_WRITE : PIPE_IMAGE_ACCESS_READ;
 450                 img[i].shader_access = SI_IMAGE_ACCESS_AS_BUFFER;
 451         }
 452
 453         img[0].format = use_uint16 ? PIPE_FORMAT_R16G16B16A16_UINT :
 454                                      PIPE_FORMAT_R32G32B32A32_UINT;
 455         img[0].u.buf.offset = tex->dcc_retile_map_offset;
 456         img[0].u.buf.size = num_elements * (use_uint16 ? 2 : 4);
 457
 458         img[1].format = PIPE_FORMAT_R8_UINT;
 459         img[1].u.buf.offset = tex->dcc_offset;
 460         img[1].u.buf.size = tex->surface.dcc_size;
 461
 462         img[2].format = PIPE_FORMAT_R8_UINT;
 463         img[2].u.buf.offset = tex->display_dcc_offset;
 464         img[2].u.buf.size = tex->surface.u.gfx9.display_dcc_size;
 465
 466         ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 3, img);
 467
 468         /* Bind the compute shader. */
 469         if (!sctx->cs_dcc_retile)
 470                 sctx->cs_dcc_retile = si_create_dcc_retile_cs(ctx);
 471         ctx->bind_compute_state(ctx, sctx->cs_dcc_retile);
 472
 473         /* Dispatch compute. */
 474         /* img[0] has 4 channels per element containing 2 pairs of DCC offsets. */
 475         unsigned num_threads = num_elements / 4;
 476
 477         struct pipe_grid_info info = {};
 478         info.block[0] = 64;
 479         info.block[1] = 1;
 480         info.block[2] = 1;
 481         info.grid[0] = DIV_ROUND_UP(num_threads, 64); /* includes the partial block */
 482         info.grid[1] = 1;
 483         info.grid[2] = 1;
 484         info.last_block[0] = num_threads % 64;
 485
 486         ctx->launch_grid(ctx, &info);
 487
 488         /* Don't flush caches or wait. The driver will wait at the end of this IB,
 489          * and L2 will be flushed by the kernel fence.
 490          */
 491
 492         /* Restore states. */
 493         ctx->bind_compute_state(ctx, saved_cs);
 494         ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 3, saved_img);
 495 }
 496
 497 void si_init_compute_blit_functions(struct si_context *sctx)
 498 {
 499         sctx->b.clear_buffer = si_pipe_clear_buffer;
 500 }
 501
 502 /* Clear a region of a color surface to a constant value. */
 503 void si_compute_clear_render_target(struct pipe_context *ctx,
 504                                     struct pipe_surface *dstsurf,
 505                                     const union pipe_color_union *color,
 506                                     unsigned dstx, unsigned dsty,
 507                                     unsigned width, unsigned height,
 508                                     bool render_condition_enabled)
 509 {
 510         struct si_context *sctx = (struct si_context *)ctx;
 511         unsigned num_layers = dstsurf->u.tex.last_layer - dstsurf->u.tex.first_layer + 1;
 512         unsigned data[4 + sizeof(color->ui)] = {dstx, dsty, dstsurf->u.tex.first_layer, 0};
 513
 514         if (width == 0 || height == 0)
 515                 return;
 516
 517         if (util_format_is_srgb(dstsurf->format)) {
 518                 union pipe_color_union color_srgb;
 519                 for (int i = 0; i < 3; i++)
 520                         color_srgb.f[i] = util_format_linear_to_srgb_float(color->f[i]);
 521                 color_srgb.f[3] = color->f[3];
 522                 memcpy(data + 4, color_srgb.ui, sizeof(color->ui));
 523         } else {
 524                 memcpy(data + 4, color->ui, sizeof(color->ui));
 525         }
 526
 527         si_compute_internal_begin(sctx);
 528         sctx->render_cond_force_off = !render_condition_enabled;
 529
 530         sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 531                        si_get_flush_flags(sctx, SI_COHERENCY_SHADER, L2_STREAM);
 532         si_make_CB_shader_coherent(sctx, dstsurf->texture->nr_samples, true,
 533                                    true /* DCC is not possible with image stores */);
 534
 535         struct pipe_constant_buffer saved_cb = {};
 536         si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &saved_cb);
 537
 538         struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE];
 539         struct pipe_image_view saved_image = {0};
 540         util_copy_image_view(&saved_image, &images->views[0]);
 541
 542         void *saved_cs = sctx->cs_shader_state.program;
 543
 544         struct pipe_constant_buffer cb = {};
 545         cb.buffer_size = sizeof(data);
 546         cb.user_buffer = data;
 547         ctx->set_constant_buffer(ctx, PIPE_SHADER_COMPUTE, 0, &cb);
 548
 549         struct pipe_image_view image = {0};
 550         image.resource = dstsurf->texture;
 551         image.shader_access = image.access = PIPE_IMAGE_ACCESS_WRITE;
 552         image.format = util_format_linear(dstsurf->format);
 553         image.u.tex.level = dstsurf->u.tex.level;
 554         image.u.tex.first_layer = 0; /* 3D images ignore first_layer (BASE_ARRAY) */
 555         image.u.tex.last_layer = dstsurf->u.tex.last_layer;
 556
 557         ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 1, &image);
 558
 559         struct pipe_grid_info info = {0};
 560
 561         if (dstsurf->texture->target != PIPE_TEXTURE_1D_ARRAY) {
 562                 if (!sctx->cs_clear_render_target)
 563                         sctx->cs_clear_render_target = si_clear_render_target_shader(ctx);
 564                 ctx->bind_compute_state(ctx, sctx->cs_clear_render_target);
 565                 info.block[0] = 8;
 566                 info.last_block[0] = width % 8;
 567                 info.block[1] = 8;
 568                 info.last_block[1] = height % 8;
 569                 info.block[2] = 1;
 570                 info.grid[0] = DIV_ROUND_UP(width, 8);
 571                 info.grid[1] = DIV_ROUND_UP(height, 8);
 572                 info.grid[2] = num_layers;
 573         } else {
 574                 if (!sctx->cs_clear_render_target_1d_array)
 575                         sctx->cs_clear_render_target_1d_array =
 576                                 si_clear_render_target_shader_1d_array(ctx);
 577                 ctx->bind_compute_state(ctx, sctx->cs_clear_render_target_1d_array);
 578                 info.block[0] = 64;
 579                 info.last_block[0] = width % 64;
 580                 info.block[1] = 1;
 581                 info.block[2] = 1;
 582                 info.grid[0] = DIV_ROUND_UP(width, 64);
 583                 info.grid[1] = num_layers;
 584                 info.grid[2] = 1;
 585         }
 586
 587         ctx->launch_grid(ctx, &info);
 588
 589         sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 590                        (sctx->chip_class <= VI ? SI_CONTEXT_WRITEBACK_GLOBAL_L2 : 0) |
 591                        si_get_flush_flags(sctx, SI_COHERENCY_SHADER, L2_STREAM);
 592         ctx->bind_compute_state(ctx, saved_cs);
 593         ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_image);
 594         ctx->set_constant_buffer(ctx, PIPE_SHADER_COMPUTE, 0, &saved_cb);
 595         si_compute_internal_end(sctx);
 596 }