2 * Copyright 2019 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_shader_internal.h"
29 #include "si_build_pm4.h"
30 #include "ac_llvm_cull.h"
32 #include "util/u_prim.h"
33 #include "util/u_suballoc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 * https://frostbite-wp-prd.s3.amazonaws.com/wp-content/uploads/2016/03/29204330/GDC_2016_Compute.pdf
41 /* This file implements primitive culling using asynchronous compute.
42 * It's written to be GL conformant.
44 * It takes a monolithic VS in LLVM IR returning gl_Position and invokes it
45 * in a compute shader. The shader processes 1 primitive/thread by invoking
46 * the VS for each vertex to get the positions, decomposes strips and fans
47 * into triangles (if needed), eliminates primitive restart (if needed),
48 * does (W<0) culling, face culling, view XY culling, zero-area and
49 * small-primitive culling, and generates a new index buffer that doesn't
50 * contain culled primitives.
52 * The index buffer is generated using the Ordered Count feature of GDS,
53 * which is an atomic counter that is incremented in the wavefront launch
54 * order, so that the original primitive order is preserved.
56 * Another GDS ordered counter is used to eliminate primitive restart indices.
57 * If a restart index lands on an even thread ID, the compute shader has to flip
58 * the primitive orientation of the whole following triangle strip. The primitive
59 * orientation has to be correct after strip and fan decomposition for two-sided
60 * shading to behave correctly. The decomposition also needs to be aware of
61 * which vertex is the provoking vertex for flat shading to behave correctly.
63 * IB = a GPU command buffer
65 * Both the compute and gfx IBs run in parallel sort of like CE and DE.
66 * The gfx IB has a CP barrier (REWIND packet) before a draw packet. REWIND
67 * doesn't continue if its word isn't 0x80000000. Once compute shaders are
68 * finished culling, the last wave will write the final primitive count from
69 * GDS directly into the count word of the draw packet in the gfx IB, and
70 * a CS_DONE event will signal the REWIND packet to continue. It's really
71 * a direct draw with command buffer patching from the compute queue.
73 * The compute IB doesn't have to start when its corresponding gfx IB starts,
74 * but can start sooner. The compute IB is signaled to start after the last
75 * execution barrier in the *previous* gfx IB. This is handled as follows.
76 * The kernel GPU scheduler starts the compute IB after the previous gfx IB has
77 * started. The compute IB then waits (WAIT_REG_MEM) for a mid-IB fence that
78 * represents the barrier in the previous gfx IB.
81 * - Triangle strips and fans are decomposed into an indexed triangle list.
82 * The decomposition differs based on the provoking vertex state.
83 * - Instanced draws are converted into non-instanced draws for 16-bit indices.
84 * (InstanceID is stored in the high bits of VertexID and unpacked by VS)
85 * - Primitive restart is fully supported with triangle strips, including
86 * correct primitive orientation across multiple waves. (restart indices
87 * reset primitive orientation)
88 * - W<0 culling (W<0 is behind the viewer, sort of like near Z culling).
89 * - Back face culling, incl. culling zero-area / degenerate primitives.
91 * - View Z culling (disabled due to limited impact with perspective projection).
92 * - Small primitive culling for all MSAA modes and all quant modes.
94 * The following are not implemented:
95 * - ClipVertex/ClipDistance/CullDistance-based culling.
99 * Limitations (and unimplemented features that may be possible to implement):
100 * - Only triangles, triangle strips, and triangle fans are supported.
101 * - Primitive restart is only supported with triangle strips.
102 * - Instancing and primitive restart can't be used together.
103 * - Instancing is only supported with 16-bit indices and instance count <= 2^16.
104 * - The instance divisor buffer is unavailable, so all divisors must be
106 * - Multidraws where the vertex shader reads gl_DrawID are unsupported.
107 * - No support for tessellation and geometry shaders.
108 * (patch elimination where tess factors are 0 would be possible to implement)
109 * - The vertex shader must not contain memory stores.
110 * - All VS resources must not have a write usage in the command buffer.
111 * - Bindless textures and images must not occur in the vertex shader.
113 * User data SGPR layout:
114 * INDEX_BUFFERS: pointer to constants
115 * 0..3: input index buffer - typed buffer view
116 * 4..7: output index buffer - typed buffer view
117 * 8..11: viewport state - scale.xy, translate.xy
118 * VERTEX_COUNTER: counter address or first primitive ID
119 * - If unordered memory counter: address of "count" in the draw packet
120 * and is incremented atomically by the shader.
121 * - If unordered GDS counter: address of "count" in GDS starting from 0,
122 * must be initialized to 0 before the dispatch.
123 * - If ordered GDS counter: the primitive ID that should reset the vertex
124 * counter to 0 in GDS
125 * LAST_WAVE_PRIM_ID: the primitive ID that should write the final vertex
126 * count to memory if using GDS ordered append
127 * VERTEX_COUNT_ADDR: where the last wave should write the vertex count if
128 * using GDS ordered append
129 * VS.VERTEX_BUFFERS: same value as VS
130 * VS.CONST_AND_SHADER_BUFFERS: same value as VS
131 * VS.SAMPLERS_AND_IMAGES: same value as VS
132 * VS.BASE_VERTEX: same value as VS
133 * VS.START_INSTANCE: same value as VS
134 * NUM_PRIMS_UDIV_MULTIPLIER: For fast 31-bit division by the number of primitives
135 * per instance for instancing.
136 * NUM_PRIMS_UDIV_TERMS:
137 * - Bits [0:4]: "post_shift" for fast 31-bit division for instancing.
138 * - Bits [5:31]: The number of primitives per instance for computing the remainder.
139 * PRIMITIVE_RESTART_INDEX
140 * SMALL_PRIM_CULLING_PRECISION: Scale the primitive bounding box by this number.
143 * The code contains 3 codepaths:
144 * - Unordered memory counter (for debugging, random primitive order, no primitive restart)
145 * - Unordered GDS counter (for debugging, random primitive order, no primitive restart)
146 * - Ordered GDS counter (it preserves the primitive order)
148 * How to test primitive restart (the most complicated part because it needs
149 * to get the primitive orientation right):
150 * Set THREADGROUP_SIZE to 2 to exercise both intra-wave and inter-wave
151 * primitive orientation flips with small draw calls, which is what most tests use.
152 * You can also enable draw call splitting into draw calls with just 2 primitives.
155 /* At least 256 is needed for the fastest wave launch rate from compute queues
156 * due to hw constraints. Nothing in the code needs more than 1 wave/threadgroup. */
157 #define THREADGROUP_SIZE 256 /* high numbers limit available VGPRs */
158 #define THREADGROUPS_PER_CU 1 /* TGs to launch on 1 CU before going onto the next, max 8 */
159 #define MAX_WAVES_PER_SH 0 /* no limit */
160 #define INDEX_STORES_USE_SLC 1 /* don't cache indices if L2 is full */
161 /* Don't cull Z. We already do (W < 0) culling for primitives behind the viewer. */
163 /* 0 = unordered memory counter, 1 = unordered GDS counter, 2 = ordered GDS counter */
164 #define VERTEX_COUNTER_GDS_MODE 2
165 #define GDS_SIZE_UNORDERED (4 * 1024) /* only for the unordered GDS counter */
167 /* Grouping compute dispatches for small draw calls: How many primitives from multiple
168 * draw calls to process by compute before signaling the gfx IB. This reduces the number
169 * of EOP events + REWIND packets, because they decrease performance. */
170 #define PRIMS_PER_BATCH (512 * 1024)
171 /* Draw call splitting at the packet level. This allows signaling the gfx IB
172 * for big draw calls sooner, but doesn't allow context flushes between packets.
173 * Primitive restart is supported. Only implemented for ordered append. */
174 #define SPLIT_PRIMS_PACKET_LEVEL_VALUE PRIMS_PER_BATCH
175 /* If there is not enough ring buffer space for the current IB, split draw calls into
176 * this number of primitives, so that we can flush the context and get free ring space. */
177 #define SPLIT_PRIMS_DRAW_LEVEL PRIMS_PER_BATCH
179 /* Derived values. */
180 #define WAVES_PER_TG DIV_ROUND_UP(THREADGROUP_SIZE, 64)
181 #define SPLIT_PRIMS_PACKET_LEVEL (VERTEX_COUNTER_GDS_MODE == 2 ? \
182 SPLIT_PRIMS_PACKET_LEVEL_VALUE : \
183 UINT_MAX & ~(THREADGROUP_SIZE - 1))
185 #define REWIND_SIGNAL_BIT 0x80000000
186 /* For emulating the rewind packet on CI. */
187 #define FORCE_REWIND_EMULATION 0
189 void si_initialize_prim_discard_tunables(struct si_screen
*sscreen
,
191 unsigned *prim_discard_vertex_count_threshold
,
192 unsigned *index_ring_size_per_ib
)
194 *prim_discard_vertex_count_threshold
= UINT_MAX
; /* disable */
196 if (sscreen
->info
.chip_class
== GFX6
|| /* SI support is not implemented */
197 !sscreen
->info
.has_gds_ordered_append
||
198 sscreen
->debug_flags
& DBG(NO_PD
) ||
202 /* TODO: enable this after the GDS kernel memory management is fixed */
203 bool enable_on_pro_graphics_by_default
= false;
205 if (sscreen
->debug_flags
& DBG(ALWAYS_PD
) ||
206 sscreen
->debug_flags
& DBG(PD
) ||
207 (enable_on_pro_graphics_by_default
&&
208 sscreen
->info
.is_pro_graphics
&&
209 (sscreen
->info
.family
== CHIP_BONAIRE
||
210 sscreen
->info
.family
== CHIP_HAWAII
||
211 sscreen
->info
.family
== CHIP_TONGA
||
212 sscreen
->info
.family
== CHIP_FIJI
||
213 sscreen
->info
.family
== CHIP_POLARIS10
||
214 sscreen
->info
.family
== CHIP_POLARIS11
||
215 sscreen
->info
.family
== CHIP_VEGA10
||
216 sscreen
->info
.family
== CHIP_VEGA20
))) {
217 *prim_discard_vertex_count_threshold
= 6000 * 3; /* 6K triangles */
219 if (sscreen
->debug_flags
& DBG(ALWAYS_PD
))
220 *prim_discard_vertex_count_threshold
= 0; /* always enable */
222 const uint32_t MB
= 1024 * 1024;
223 const uint64_t GB
= 1024 * 1024 * 1024;
225 /* The total size is double this per context.
226 * Greater numbers allow bigger gfx IBs.
228 if (sscreen
->info
.vram_size
<= 2 * GB
)
229 *index_ring_size_per_ib
= 64 * MB
;
230 else if (sscreen
->info
.vram_size
<= 4 * GB
)
231 *index_ring_size_per_ib
= 128 * MB
;
233 *index_ring_size_per_ib
= 256 * MB
;
237 /* Opcode can be "add" or "swap". */
239 si_build_ds_ordered_op(struct si_shader_context
*ctx
, const char *opcode
,
240 LLVMValueRef m0
, LLVMValueRef value
, unsigned ordered_count_index
,
241 bool release
, bool done
)
243 LLVMValueRef args
[] = {
244 LLVMBuildIntToPtr(ctx
->ac
.builder
, m0
,
245 LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
), ""),
247 LLVMConstInt(ctx
->ac
.i32
, LLVMAtomicOrderingMonotonic
, 0), /* ordering */
248 ctx
->ac
.i32_0
, /* scope */
249 ctx
->ac
.i1false
, /* volatile */
250 LLVMConstInt(ctx
->ac
.i32
, ordered_count_index
, 0),
251 LLVMConstInt(ctx
->ac
.i1
, release
, 0),
252 LLVMConstInt(ctx
->ac
.i1
, done
, 0),
256 snprintf(intrinsic
, sizeof(intrinsic
), "llvm.amdgcn.ds.ordered.%s", opcode
);
257 return ac_build_intrinsic(&ctx
->ac
, intrinsic
, ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
260 static LLVMValueRef
si_expand_32bit_pointer(struct si_shader_context
*ctx
, LLVMValueRef ptr
)
262 uint64_t hi
= (uint64_t)ctx
->screen
->info
.address32_hi
<< 32;
263 ptr
= LLVMBuildZExt(ctx
->ac
.builder
, ptr
, ctx
->ac
.i64
, "");
264 ptr
= LLVMBuildOr(ctx
->ac
.builder
, ptr
, LLVMConstInt(ctx
->ac
.i64
, hi
, 0), "");
265 return LLVMBuildIntToPtr(ctx
->ac
.builder
, ptr
,
266 LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GLOBAL
), "");
269 struct si_thread0_section
{
270 struct si_shader_context
*ctx
;
271 LLVMValueRef vgpr_result
; /* a VGPR for the value on thread 0. */
272 LLVMValueRef saved_exec
;
275 /* Enter a section that only executes on thread 0. */
276 static void si_enter_thread0_section(struct si_shader_context
*ctx
,
277 struct si_thread0_section
*section
,
278 LLVMValueRef thread_id
)
281 section
->vgpr_result
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "result0");
283 /* This IF has 4 instructions:
284 * v_and_b32_e32 v, 63, v ; get the thread ID
285 * v_cmp_eq_u32_e32 vcc, 0, v ; thread ID == 0
286 * s_and_saveexec_b64 s, vcc
287 * s_cbranch_execz BB0_4
289 * It could just be s_and_saveexec_b64 s, 1.
291 ac_build_ifcc(&ctx
->ac
,
292 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, thread_id
,
293 ctx
->ac
.i32_0
, ""), 12601);
296 /* Exit a section that only executes on thread 0 and broadcast the result
298 static void si_exit_thread0_section(struct si_thread0_section
*section
,
299 LLVMValueRef
*result
)
301 struct si_shader_context
*ctx
= section
->ctx
;
303 LLVMBuildStore(ctx
->ac
.builder
, *result
, section
->vgpr_result
);
305 ac_build_endif(&ctx
->ac
, 12601);
307 /* Broadcast the result from thread 0 to all threads. */
308 *result
= ac_build_readlane(&ctx
->ac
,
309 LLVMBuildLoad(ctx
->ac
.builder
, section
->vgpr_result
, ""), NULL
);
312 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
)
314 struct si_shader_key
*key
= &ctx
->shader
->key
;
315 LLVMBuilderRef builder
= ctx
->ac
.builder
;
316 LLVMValueRef vs
= ctx
->main_fn
;
318 /* Always inline the VS function. */
319 ac_add_function_attr(ctx
->ac
.context
, vs
, -1, AC_FUNC_ATTR_ALWAYSINLINE
);
320 LLVMSetLinkage(vs
, LLVMPrivateLinkage
);
322 enum ac_arg_type const_desc_type
;
323 if (ctx
->shader
->selector
->info
.const_buffers_declared
== 1 &&
324 ctx
->shader
->selector
->info
.shader_buffers_declared
== 0)
325 const_desc_type
= AC_ARG_CONST_FLOAT_PTR
;
327 const_desc_type
= AC_ARG_CONST_DESC_PTR
;
329 memset(&ctx
->args
, 0, sizeof(ctx
->args
));
331 struct ac_arg param_index_buffers_and_constants
, param_vertex_counter
;
332 struct ac_arg param_vb_desc
, param_const_desc
;
333 struct ac_arg param_base_vertex
, param_start_instance
;
334 struct ac_arg param_block_id
, param_local_id
, param_ordered_wave_id
;
335 struct ac_arg param_restart_index
, param_smallprim_precision
;
336 struct ac_arg param_num_prims_udiv_multiplier
, param_num_prims_udiv_terms
;
337 struct ac_arg param_sampler_desc
, param_last_wave_prim_id
, param_vertex_count_addr
;
339 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_CONST_DESC_PTR
,
340 ¶m_index_buffers_and_constants
);
341 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_vertex_counter
);
342 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_last_wave_prim_id
);
343 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_vertex_count_addr
);
344 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_CONST_DESC_PTR
,
346 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, const_desc_type
,
348 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_CONST_IMAGE_PTR
,
349 ¶m_sampler_desc
);
350 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_base_vertex
);
351 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_start_instance
);
352 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_num_prims_udiv_multiplier
);
353 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_num_prims_udiv_terms
);
354 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_restart_index
);
355 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_FLOAT
, ¶m_smallprim_precision
);
357 /* Block ID and thread ID inputs. */
358 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_block_id
);
359 if (VERTEX_COUNTER_GDS_MODE
== 2)
360 ac_add_arg(&ctx
->args
, AC_ARG_SGPR
, 1, AC_ARG_INT
, ¶m_ordered_wave_id
);
361 ac_add_arg(&ctx
->args
, AC_ARG_VGPR
, 1, AC_ARG_INT
, ¶m_local_id
);
363 /* Create the compute shader function. */
364 unsigned old_type
= ctx
->type
;
365 ctx
->type
= PIPE_SHADER_COMPUTE
;
366 si_llvm_create_func(ctx
, "prim_discard_cs", NULL
, 0, THREADGROUP_SIZE
);
367 ctx
->type
= old_type
;
369 if (VERTEX_COUNTER_GDS_MODE
== 1) {
370 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
, "amdgpu-gds-size",
374 /* Assemble parameters for VS. */
375 LLVMValueRef vs_params
[16];
376 unsigned num_vs_params
= 0;
377 unsigned param_vertex_id
, param_instance_id
;
379 vs_params
[num_vs_params
++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs
, 0))); /* RW_BUFFERS */
380 vs_params
[num_vs_params
++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs
, 1))); /* BINDLESS */
381 vs_params
[num_vs_params
++] = ac_get_arg(&ctx
->ac
, param_const_desc
);
382 vs_params
[num_vs_params
++] = ac_get_arg(&ctx
->ac
, param_sampler_desc
);
383 vs_params
[num_vs_params
++] = LLVMConstInt(ctx
->ac
.i32
,
384 S_VS_STATE_INDEXED(key
->opt
.cs_indexed
), 0);
385 vs_params
[num_vs_params
++] = ac_get_arg(&ctx
->ac
, param_base_vertex
);
386 vs_params
[num_vs_params
++] = ac_get_arg(&ctx
->ac
, param_start_instance
);
387 vs_params
[num_vs_params
++] = ctx
->ac
.i32_0
; /* DrawID */
388 vs_params
[num_vs_params
++] = ac_get_arg(&ctx
->ac
, param_vb_desc
);
390 vs_params
[(param_vertex_id
= num_vs_params
++)] = NULL
; /* VertexID */
391 vs_params
[(param_instance_id
= num_vs_params
++)] = NULL
; /* InstanceID */
392 vs_params
[num_vs_params
++] = ctx
->ac
.i32_0
; /* unused (PrimID) */
393 vs_params
[num_vs_params
++] = ctx
->ac
.i32_0
; /* unused */
395 assert(num_vs_params
<= ARRAY_SIZE(vs_params
));
396 assert(num_vs_params
== LLVMCountParamTypes(LLVMGetElementType(LLVMTypeOf(vs
))));
398 /* Load descriptors. (load 8 dwords at once) */
399 LLVMValueRef input_indexbuf
, output_indexbuf
, tmp
, desc
[8];
401 LLVMValueRef index_buffers_and_constants
= ac_get_arg(&ctx
->ac
, param_index_buffers_and_constants
);
402 tmp
= LLVMBuildPointerCast(builder
, index_buffers_and_constants
,
403 ac_array_in_const32_addr_space(ctx
->ac
.v8i32
), "");
404 tmp
= ac_build_load_to_sgpr(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
406 for (unsigned i
= 0; i
< 8; i
++)
407 desc
[i
] = ac_llvm_extract_elem(&ctx
->ac
, tmp
, i
);
409 input_indexbuf
= ac_build_gather_values(&ctx
->ac
, desc
, 4);
410 output_indexbuf
= ac_build_gather_values(&ctx
->ac
, desc
+ 4, 4);
412 /* Compute PrimID and InstanceID. */
413 LLVMValueRef global_thread_id
=
414 ac_build_imad(&ctx
->ac
, ac_get_arg(&ctx
->ac
, param_block_id
),
415 LLVMConstInt(ctx
->ac
.i32
, THREADGROUP_SIZE
, 0),
416 ac_get_arg(&ctx
->ac
, param_local_id
));
417 LLVMValueRef prim_id
= global_thread_id
; /* PrimID within an instance */
418 LLVMValueRef instance_id
= ctx
->ac
.i32_0
;
420 if (key
->opt
.cs_instancing
) {
421 LLVMValueRef num_prims_udiv_terms
=
422 ac_get_arg(&ctx
->ac
, param_num_prims_udiv_terms
);
423 LLVMValueRef num_prims_udiv_multiplier
=
424 ac_get_arg(&ctx
->ac
, param_num_prims_udiv_multiplier
);
425 /* Unpack num_prims_udiv_terms. */
426 LLVMValueRef post_shift
= LLVMBuildAnd(builder
, num_prims_udiv_terms
,
427 LLVMConstInt(ctx
->ac
.i32
, 0x1f, 0), "");
428 LLVMValueRef prims_per_instance
= LLVMBuildLShr(builder
, num_prims_udiv_terms
,
429 LLVMConstInt(ctx
->ac
.i32
, 5, 0), "");
430 /* Divide the total prim_id by the number of prims per instance. */
431 instance_id
= ac_build_fast_udiv_u31_d_not_one(&ctx
->ac
, prim_id
,
432 num_prims_udiv_multiplier
,
434 /* Compute the remainder. */
435 prim_id
= LLVMBuildSub(builder
, prim_id
,
436 LLVMBuildMul(builder
, instance_id
,
437 prims_per_instance
, ""), "");
440 /* Generate indices (like a non-indexed draw call). */
441 LLVMValueRef index
[4] = {NULL
, NULL
, NULL
, LLVMGetUndef(ctx
->ac
.i32
)};
442 unsigned vertices_per_prim
= 3;
444 switch (key
->opt
.cs_prim_type
) {
445 case PIPE_PRIM_TRIANGLES
:
446 for (unsigned i
= 0; i
< 3; i
++) {
447 index
[i
] = ac_build_imad(&ctx
->ac
, prim_id
,
448 LLVMConstInt(ctx
->ac
.i32
, 3, 0),
449 LLVMConstInt(ctx
->ac
.i32
, i
, 0));
452 case PIPE_PRIM_TRIANGLE_STRIP
:
453 for (unsigned i
= 0; i
< 3; i
++) {
454 index
[i
] = LLVMBuildAdd(builder
, prim_id
,
455 LLVMConstInt(ctx
->ac
.i32
, i
, 0), "");
458 case PIPE_PRIM_TRIANGLE_FAN
:
459 /* Vertex 1 is first and vertex 2 is last. This will go to the hw clipper
460 * and rasterizer as a normal triangle, so we need to put the provoking
461 * vertex into the correct index variable and preserve orientation at the same time.
462 * gl_VertexID is preserved, because it's equal to the index.
464 if (key
->opt
.cs_provoking_vertex_first
) {
465 index
[0] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->ac
.i32
, 1, 0), "");
466 index
[1] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->ac
.i32
, 2, 0), "");
467 index
[2] = ctx
->ac
.i32_0
;
469 index
[0] = ctx
->ac
.i32_0
;
470 index
[1] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->ac
.i32
, 1, 0), "");
471 index
[2] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->ac
.i32
, 2, 0), "");
475 unreachable("unexpected primitive type");
479 if (key
->opt
.cs_indexed
) {
480 for (unsigned i
= 0; i
< 3; i
++) {
481 index
[i
] = ac_build_buffer_load_format(&ctx
->ac
, input_indexbuf
,
482 index
[i
], ctx
->ac
.i32_0
, 1,
484 index
[i
] = ac_to_integer(&ctx
->ac
, index
[i
]);
488 LLVMValueRef ordered_wave_id
= ac_get_arg(&ctx
->ac
, param_ordered_wave_id
);
490 /* Extract the ordered wave ID. */
491 if (VERTEX_COUNTER_GDS_MODE
== 2) {
492 ordered_wave_id
= LLVMBuildLShr(builder
, ordered_wave_id
,
493 LLVMConstInt(ctx
->ac
.i32
, 6, 0), "");
494 ordered_wave_id
= LLVMBuildAnd(builder
, ordered_wave_id
,
495 LLVMConstInt(ctx
->ac
.i32
, 0xfff, 0), "");
497 LLVMValueRef thread_id
=
498 LLVMBuildAnd(builder
, ac_get_arg(&ctx
->ac
, param_local_id
),
499 LLVMConstInt(ctx
->ac
.i32
, 63, 0), "");
501 /* Every other triangle in a strip has a reversed vertex order, so we
502 * need to swap vertices of odd primitives to get the correct primitive
503 * orientation when converting triangle strips to triangles. Primitive
504 * restart complicates it, because a strip can start anywhere.
506 LLVMValueRef prim_restart_accepted
= ctx
->ac
.i1true
;
507 LLVMValueRef vertex_counter
= ac_get_arg(&ctx
->ac
, param_vertex_counter
);
509 if (key
->opt
.cs_prim_type
== PIPE_PRIM_TRIANGLE_STRIP
) {
510 /* Without primitive restart, odd primitives have reversed orientation.
511 * Only primitive restart can flip it with respect to the first vertex
514 LLVMValueRef first_is_odd
= ctx
->ac
.i1false
;
516 /* Handle primitive restart. */
517 if (key
->opt
.cs_primitive_restart
) {
518 /* Get the GDS primitive restart continue flag and clear
519 * the flag in vertex_counter. This flag is used when the draw
520 * call was split and we need to load the primitive orientation
521 * flag from GDS for the first wave too.
523 LLVMValueRef gds_prim_restart_continue
=
524 LLVMBuildLShr(builder
, vertex_counter
,
525 LLVMConstInt(ctx
->ac
.i32
, 31, 0), "");
526 gds_prim_restart_continue
=
527 LLVMBuildTrunc(builder
, gds_prim_restart_continue
, ctx
->ac
.i1
, "");
528 vertex_counter
= LLVMBuildAnd(builder
, vertex_counter
,
529 LLVMConstInt(ctx
->ac
.i32
, 0x7fffffff, 0), "");
531 LLVMValueRef index0_is_reset
;
533 for (unsigned i
= 0; i
< 3; i
++) {
534 LLVMValueRef not_reset
= LLVMBuildICmp(builder
, LLVMIntNE
, index
[i
],
535 ac_get_arg(&ctx
->ac
, param_restart_index
),
538 index0_is_reset
= LLVMBuildNot(builder
, not_reset
, "");
539 prim_restart_accepted
= LLVMBuildAnd(builder
, prim_restart_accepted
,
543 /* If the previous waves flip the primitive orientation
544 * of the current triangle strip, it will be stored in GDS.
546 * Sometimes the correct orientation is not needed, in which case
547 * we don't need to execute this.
549 if (key
->opt
.cs_need_correct_orientation
&& VERTEX_COUNTER_GDS_MODE
== 2) {
550 /* If there are reset indices in this wave, get the thread index
551 * where the most recent strip starts relative to each thread.
553 LLVMValueRef preceding_threads_mask
=
554 LLVMBuildSub(builder
,
555 LLVMBuildShl(builder
, ctx
->ac
.i64_1
,
556 LLVMBuildZExt(builder
, thread_id
, ctx
->ac
.i64
, ""), ""),
559 LLVMValueRef reset_threadmask
= ac_get_i1_sgpr_mask(&ctx
->ac
, index0_is_reset
);
560 LLVMValueRef preceding_reset_threadmask
=
561 LLVMBuildAnd(builder
, reset_threadmask
, preceding_threads_mask
, "");
562 LLVMValueRef strip_start
=
563 ac_build_umsb(&ctx
->ac
, preceding_reset_threadmask
, NULL
);
564 strip_start
= LLVMBuildAdd(builder
, strip_start
, ctx
->ac
.i32_1
, "");
566 /* This flips the orientatino based on reset indices within this wave only. */
567 first_is_odd
= LLVMBuildTrunc(builder
, strip_start
, ctx
->ac
.i1
, "");
569 LLVMValueRef last_strip_start
, prev_wave_state
, ret
, tmp
;
570 LLVMValueRef is_first_wave
, current_wave_resets_index
;
572 /* Get the thread index where the last strip starts in this wave.
574 * If the last strip doesn't start in this wave, the thread index
577 * If the last strip starts in the next wave, the thread index will
580 last_strip_start
= ac_build_umsb(&ctx
->ac
, reset_threadmask
, NULL
);
581 last_strip_start
= LLVMBuildAdd(builder
, last_strip_start
, ctx
->ac
.i32_1
, "");
583 struct si_thread0_section section
;
584 si_enter_thread0_section(ctx
, §ion
, thread_id
);
586 /* This must be done in the thread 0 section, because
587 * we expect PrimID to be 0 for the whole first wave
588 * in this expression.
590 * NOTE: This will need to be different if we wanna support
591 * instancing with primitive restart.
593 is_first_wave
= LLVMBuildICmp(builder
, LLVMIntEQ
, prim_id
, ctx
->ac
.i32_0
, "");
594 is_first_wave
= LLVMBuildAnd(builder
, is_first_wave
,
595 LLVMBuildNot(builder
,
596 gds_prim_restart_continue
, ""), "");
597 current_wave_resets_index
= LLVMBuildICmp(builder
, LLVMIntNE
,
598 last_strip_start
, ctx
->ac
.i32_0
, "");
600 ret
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "prev_state");
602 /* Save the last strip start primitive index in GDS and read
603 * the value that previous waves stored.
605 * if (is_first_wave || current_wave_resets_strip)
606 * // Read the value that previous waves stored and store a new one.
607 * first_is_odd = ds.ordered.swap(last_strip_start);
609 * // Just read the value that previous waves stored.
610 * first_is_odd = ds.ordered.add(0);
612 ac_build_ifcc(&ctx
->ac
,
613 LLVMBuildOr(builder
, is_first_wave
,
614 current_wave_resets_index
, ""), 12602);
616 /* The GDS address is always 0 with ordered append. */
617 tmp
= si_build_ds_ordered_op(ctx
, "swap",
618 ordered_wave_id
, last_strip_start
,
620 LLVMBuildStore(builder
, tmp
, ret
);
622 ac_build_else(&ctx
->ac
, 12603);
624 /* Just read the value from GDS. */
625 tmp
= si_build_ds_ordered_op(ctx
, "add",
626 ordered_wave_id
, ctx
->ac
.i32_0
,
628 LLVMBuildStore(builder
, tmp
, ret
);
630 ac_build_endif(&ctx
->ac
, 12602);
632 prev_wave_state
= LLVMBuildLoad(builder
, ret
, "");
633 /* Ignore the return value if this is the first wave. */
634 prev_wave_state
= LLVMBuildSelect(builder
, is_first_wave
,
635 ctx
->ac
.i32_0
, prev_wave_state
, "");
636 si_exit_thread0_section(§ion
, &prev_wave_state
);
637 prev_wave_state
= LLVMBuildTrunc(builder
, prev_wave_state
, ctx
->ac
.i1
, "");
639 /* If the strip start appears to be on thread 0 for the current primitive
640 * (meaning the reset index is not present in this wave and might have
641 * appeared in previous waves), use the value from GDS to determine
642 * primitive orientation.
644 * If the strip start is in this wave for the current primitive, use
645 * the value from the current wave to determine primitive orientation.
647 LLVMValueRef strip_start_is0
= LLVMBuildICmp(builder
, LLVMIntEQ
,
648 strip_start
, ctx
->ac
.i32_0
, "");
649 first_is_odd
= LLVMBuildSelect(builder
, strip_start_is0
, prev_wave_state
,
653 /* prim_is_odd = (first_is_odd + current_is_odd) % 2. */
654 LLVMValueRef prim_is_odd
=
655 LLVMBuildXor(builder
, first_is_odd
,
656 LLVMBuildTrunc(builder
, thread_id
, ctx
->ac
.i1
, ""), "");
658 /* Convert triangle strip indices to triangle indices. */
659 ac_build_triangle_strip_indices_to_triangle(&ctx
->ac
, prim_is_odd
,
660 LLVMConstInt(ctx
->ac
.i1
, key
->opt
.cs_provoking_vertex_first
, 0),
664 /* Execute the vertex shader for each vertex to get vertex positions. */
665 LLVMValueRef pos
[3][4];
666 for (unsigned i
= 0; i
< vertices_per_prim
; i
++) {
667 vs_params
[param_vertex_id
] = index
[i
];
668 vs_params
[param_instance_id
] = instance_id
;
670 LLVMValueRef ret
= ac_build_call(&ctx
->ac
, vs
, vs_params
, num_vs_params
);
671 for (unsigned chan
= 0; chan
< 4; chan
++)
672 pos
[i
][chan
] = LLVMBuildExtractValue(builder
, ret
, chan
, "");
675 /* Divide XYZ by W. */
676 for (unsigned i
= 0; i
< vertices_per_prim
; i
++) {
677 for (unsigned chan
= 0; chan
< 3; chan
++)
678 pos
[i
][chan
] = ac_build_fdiv(&ctx
->ac
, pos
[i
][chan
], pos
[i
][3]);
681 /* Load the viewport state. */
682 LLVMValueRef vp
= ac_build_load_invariant(&ctx
->ac
, index_buffers_and_constants
,
683 LLVMConstInt(ctx
->ac
.i32
, 2, 0));
684 vp
= LLVMBuildBitCast(builder
, vp
, ctx
->ac
.v4f32
, "");
685 LLVMValueRef vp_scale
[2], vp_translate
[2];
686 vp_scale
[0] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 0);
687 vp_scale
[1] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 1);
688 vp_translate
[0] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 2);
689 vp_translate
[1] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 3);
692 struct ac_cull_options options
= {};
693 options
.cull_front
= key
->opt
.cs_cull_front
;
694 options
.cull_back
= key
->opt
.cs_cull_back
;
695 options
.cull_view_xy
= true;
696 options
.cull_view_near_z
= CULL_Z
&& key
->opt
.cs_cull_z
;
697 options
.cull_view_far_z
= CULL_Z
&& key
->opt
.cs_cull_z
;
698 options
.cull_small_prims
= true;
699 options
.cull_zero_area
= true;
700 options
.cull_w
= true;
701 options
.use_halfz_clip_space
= key
->opt
.cs_halfz_clip_space
;
703 LLVMValueRef accepted
=
704 ac_cull_triangle(&ctx
->ac
, pos
, prim_restart_accepted
,
705 vp_scale
, vp_translate
,
706 ac_get_arg(&ctx
->ac
, param_smallprim_precision
),
709 ac_build_optimization_barrier(&ctx
->ac
, &accepted
);
710 LLVMValueRef accepted_threadmask
= ac_get_i1_sgpr_mask(&ctx
->ac
, accepted
);
712 /* Count the number of active threads by doing bitcount(accepted). */
713 LLVMValueRef num_prims_accepted
=
714 ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i64", ctx
->ac
.i64
,
715 &accepted_threadmask
, 1, AC_FUNC_ATTR_READNONE
);
716 num_prims_accepted
= LLVMBuildTrunc(builder
, num_prims_accepted
, ctx
->ac
.i32
, "");
720 /* Execute atomic_add on the vertex count. */
721 struct si_thread0_section section
;
722 si_enter_thread0_section(ctx
, §ion
, thread_id
);
724 if (VERTEX_COUNTER_GDS_MODE
== 0) {
725 LLVMValueRef num_indices
= LLVMBuildMul(builder
, num_prims_accepted
,
726 LLVMConstInt(ctx
->ac
.i32
, vertices_per_prim
, 0), "");
727 vertex_counter
= si_expand_32bit_pointer(ctx
, vertex_counter
);
728 start
= LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
729 vertex_counter
, num_indices
,
730 LLVMAtomicOrderingMonotonic
, false);
731 } else if (VERTEX_COUNTER_GDS_MODE
== 1) {
732 LLVMValueRef num_indices
= LLVMBuildMul(builder
, num_prims_accepted
,
733 LLVMConstInt(ctx
->ac
.i32
, vertices_per_prim
, 0), "");
734 vertex_counter
= LLVMBuildIntToPtr(builder
, vertex_counter
,
735 LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
), "");
736 start
= LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
737 vertex_counter
, num_indices
,
738 LLVMAtomicOrderingMonotonic
, false);
739 } else if (VERTEX_COUNTER_GDS_MODE
== 2) {
740 LLVMValueRef tmp_store
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
742 /* If the draw call was split into multiple subdraws, each using
743 * a separate draw packet, we need to start counting from 0 for
744 * the first compute wave of the subdraw.
746 * vertex_counter contains the primitive ID of the first thread
749 * This is only correct with VERTEX_COUNTER_GDS_MODE == 2:
751 LLVMValueRef is_first_wave
=
752 LLVMBuildICmp(builder
, LLVMIntEQ
, global_thread_id
,
755 /* Store the primitive count for ordered append, not vertex count.
756 * The idea is to avoid GDS initialization via CP DMA. The shader
757 * effectively stores the first count using "swap".
760 * ds.ordered.swap(num_prims_accepted); // store the first primitive count
763 * previous = ds.ordered.add(num_prims_accepted) // add the primitive count
766 ac_build_ifcc(&ctx
->ac
, is_first_wave
, 12604);
768 /* The GDS address is always 0 with ordered append. */
769 si_build_ds_ordered_op(ctx
, "swap", ordered_wave_id
,
770 num_prims_accepted
, 0, true, true);
771 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, tmp_store
);
773 ac_build_else(&ctx
->ac
, 12605);
775 LLVMBuildStore(builder
,
776 si_build_ds_ordered_op(ctx
, "add", ordered_wave_id
,
777 num_prims_accepted
, 0,
781 ac_build_endif(&ctx
->ac
, 12604);
783 start
= LLVMBuildLoad(builder
, tmp_store
, "");
786 si_exit_thread0_section(§ion
, &start
);
788 /* Write the final vertex count to memory. An EOS/EOP event could do this,
789 * but those events are super slow and should be avoided if performance
790 * is a concern. Thanks to GDS ordered append, we can emulate a CS_DONE
793 if (VERTEX_COUNTER_GDS_MODE
== 2) {
794 ac_build_ifcc(&ctx
->ac
,
795 LLVMBuildICmp(builder
, LLVMIntEQ
, global_thread_id
,
796 ac_get_arg(&ctx
->ac
, param_last_wave_prim_id
), ""),
798 LLVMValueRef count
= LLVMBuildAdd(builder
, start
, num_prims_accepted
, "");
799 count
= LLVMBuildMul(builder
, count
,
800 LLVMConstInt(ctx
->ac
.i32
, vertices_per_prim
, 0), "");
802 /* GFX8 needs to disable caching, so that the CP can see the stored value.
803 * MTYPE=3 bypasses TC L2.
805 if (ctx
->screen
->info
.chip_class
<= GFX8
) {
806 LLVMValueRef desc
[] = {
807 ac_get_arg(&ctx
->ac
, param_vertex_count_addr
),
808 LLVMConstInt(ctx
->ac
.i32
,
809 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0),
810 LLVMConstInt(ctx
->ac
.i32
, 4, 0),
811 LLVMConstInt(ctx
->ac
.i32
, S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
812 S_008F0C_MTYPE(3 /* uncached */), 0),
814 LLVMValueRef rsrc
= ac_build_gather_values(&ctx
->ac
, desc
, 4);
815 ac_build_buffer_store_dword(&ctx
->ac
, rsrc
, count
, 1, ctx
->ac
.i32_0
,
816 ctx
->ac
.i32_0
, 0, ac_glc
| ac_slc
);
818 LLVMBuildStore(builder
, count
,
819 si_expand_32bit_pointer(ctx
,
821 param_vertex_count_addr
)));
823 ac_build_endif(&ctx
->ac
, 12606);
825 /* For unordered modes that increment a vertex count instead of
826 * primitive count, convert it into the primitive index.
828 start
= LLVMBuildUDiv(builder
, start
,
829 LLVMConstInt(ctx
->ac
.i32
, vertices_per_prim
, 0), "");
832 /* Now we need to store the indices of accepted primitives into
833 * the output index buffer.
835 ac_build_ifcc(&ctx
->ac
, accepted
, 16607);
837 /* Get the number of bits set before the index of this thread. */
838 LLVMValueRef prim_index
= ac_build_mbcnt(&ctx
->ac
, accepted_threadmask
);
840 /* We have lowered instancing. Pack the instance ID into vertex ID. */
841 if (key
->opt
.cs_instancing
) {
842 instance_id
= LLVMBuildShl(builder
, instance_id
,
843 LLVMConstInt(ctx
->ac
.i32
, 16, 0), "");
845 for (unsigned i
= 0; i
< vertices_per_prim
; i
++)
846 index
[i
] = LLVMBuildOr(builder
, index
[i
], instance_id
, "");
849 if (VERTEX_COUNTER_GDS_MODE
== 2) {
850 /* vertex_counter contains the first primitive ID
851 * for this dispatch. If the draw call was split into
852 * multiple subdraws, the first primitive ID is > 0
853 * for subsequent subdraws. Each subdraw uses a different
854 * portion of the output index buffer. Offset the store
855 * vindex by the first primitive ID to get the correct
856 * store address for the subdraw.
858 start
= LLVMBuildAdd(builder
, start
, vertex_counter
, "");
861 /* Write indices for accepted primitives. */
862 LLVMValueRef vindex
= LLVMBuildAdd(builder
, start
, prim_index
, "");
863 LLVMValueRef vdata
= ac_build_gather_values(&ctx
->ac
, index
, 3);
865 if (!ac_has_vec3_support(ctx
->ac
.chip_class
, true))
866 vdata
= ac_build_expand_to_vec4(&ctx
->ac
, vdata
, 3);
868 ac_build_buffer_store_format(&ctx
->ac
, output_indexbuf
, vdata
,
869 vindex
, ctx
->ac
.i32_0
, 3,
870 ac_glc
| (INDEX_STORES_USE_SLC
? ac_slc
: 0));
872 ac_build_endif(&ctx
->ac
, 16607);
874 LLVMBuildRetVoid(builder
);
877 /* Return false if the shader isn't ready. */
878 static bool si_shader_select_prim_discard_cs(struct si_context
*sctx
,
879 const struct pipe_draw_info
*info
,
880 bool primitive_restart
)
882 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
883 struct si_shader_key key
;
885 /* Primitive restart needs ordered counters. */
886 assert(!primitive_restart
|| VERTEX_COUNTER_GDS_MODE
== 2);
887 assert(!primitive_restart
|| info
->instance_count
== 1);
889 memset(&key
, 0, sizeof(key
));
890 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
, &key
, &key
.part
.vs
.prolog
);
891 assert(!key
.part
.vs
.prolog
.instance_divisor_is_fetched
);
893 key
.part
.vs
.prolog
.unpack_instance_id_from_vertex_id
= 0;
894 key
.opt
.vs_as_prim_discard_cs
= 1;
895 key
.opt
.cs_prim_type
= info
->mode
;
896 key
.opt
.cs_indexed
= info
->index_size
!= 0;
897 key
.opt
.cs_instancing
= info
->instance_count
> 1;
898 key
.opt
.cs_primitive_restart
= primitive_restart
;
899 key
.opt
.cs_provoking_vertex_first
= rs
->provoking_vertex_first
;
901 /* Primitive restart with triangle strips needs to preserve primitive
902 * orientation for cases where front and back primitive orientation matters.
904 if (primitive_restart
) {
905 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
907 key
.opt
.cs_need_correct_orientation
=
908 rs
->cull_front
!= rs
->cull_back
||
909 ps
->info
.uses_frontface
||
910 (rs
->two_side
&& ps
->info
.colors_read
);
913 if (rs
->rasterizer_discard
) {
914 /* Just for performance testing and analysis of trivial bottlenecks.
915 * This should result in a very short compute shader. */
916 key
.opt
.cs_cull_front
= 1;
917 key
.opt
.cs_cull_back
= 1;
919 key
.opt
.cs_cull_front
=
920 sctx
->viewports
.y_inverted
? rs
->cull_back
: rs
->cull_front
;
921 key
.opt
.cs_cull_back
=
922 sctx
->viewports
.y_inverted
? rs
->cull_front
: rs
->cull_back
;
925 if (!rs
->depth_clamp_any
&& CULL_Z
) {
926 key
.opt
.cs_cull_z
= 1;
927 key
.opt
.cs_halfz_clip_space
= rs
->clip_halfz
;
930 sctx
->cs_prim_discard_state
.cso
= sctx
->vs_shader
.cso
;
931 sctx
->cs_prim_discard_state
.current
= NULL
;
933 if (!sctx
->compiler
.passes
)
934 si_init_compiler(sctx
->screen
, &sctx
->compiler
);
936 struct si_compiler_ctx_state compiler_state
;
937 compiler_state
.compiler
= &sctx
->compiler
;
938 compiler_state
.debug
= sctx
->debug
;
939 compiler_state
.is_debug_context
= sctx
->is_debug
;
941 return si_shader_select_with_key(sctx
->screen
, &sctx
->cs_prim_discard_state
,
942 &compiler_state
, &key
, -1, true) == 0 &&
943 /* Disallow compute shaders using the scratch buffer. */
944 sctx
->cs_prim_discard_state
.current
->config
.scratch_bytes_per_wave
== 0;
947 static bool si_initialize_prim_discard_cmdbuf(struct si_context
*sctx
)
949 if (sctx
->index_ring
)
952 if (!sctx
->prim_discard_compute_cs
) {
953 struct radeon_winsys
*ws
= sctx
->ws
;
954 unsigned gds_size
= VERTEX_COUNTER_GDS_MODE
== 1 ? GDS_SIZE_UNORDERED
:
955 VERTEX_COUNTER_GDS_MODE
== 2 ? 8 : 0;
956 unsigned num_oa_counters
= VERTEX_COUNTER_GDS_MODE
== 2 ? 2 : 0;
959 sctx
->gds
= ws
->buffer_create(ws
, gds_size
, 4,
960 RADEON_DOMAIN_GDS
, 0);
964 ws
->cs_add_buffer(sctx
->gfx_cs
, sctx
->gds
,
965 RADEON_USAGE_READWRITE
, 0, 0);
967 if (num_oa_counters
) {
969 sctx
->gds_oa
= ws
->buffer_create(ws
, num_oa_counters
,
970 1, RADEON_DOMAIN_OA
, 0);
974 ws
->cs_add_buffer(sctx
->gfx_cs
, sctx
->gds_oa
,
975 RADEON_USAGE_READWRITE
, 0, 0);
978 sctx
->prim_discard_compute_cs
=
979 ws
->cs_add_parallel_compute_ib(sctx
->gfx_cs
,
980 num_oa_counters
> 0);
981 if (!sctx
->prim_discard_compute_cs
)
985 if (!sctx
->index_ring
) {
987 si_aligned_buffer_create(sctx
->b
.screen
,
988 SI_RESOURCE_FLAG_UNMAPPABLE
,
990 sctx
->index_ring_size_per_ib
* 2,
991 sctx
->screen
->info
.pte_fragment_size
);
992 if (!sctx
->index_ring
)
998 static bool si_check_ring_space(struct si_context
*sctx
, unsigned out_indexbuf_size
)
1000 return sctx
->index_ring_offset
+
1001 align(out_indexbuf_size
, sctx
->screen
->info
.tcc_cache_line_size
) <=
1002 sctx
->index_ring_size_per_ib
;
1005 enum si_prim_discard_outcome
1006 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
,
1007 const struct pipe_draw_info
*info
,
1008 bool primitive_restart
)
1010 /* If the compute shader compilation isn't finished, this returns false. */
1011 if (!si_shader_select_prim_discard_cs(sctx
, info
, primitive_restart
))
1012 return SI_PRIM_DISCARD_DISABLED
;
1014 if (!si_initialize_prim_discard_cmdbuf(sctx
))
1015 return SI_PRIM_DISCARD_DISABLED
;
1017 struct radeon_cmdbuf
*gfx_cs
= sctx
->gfx_cs
;
1018 unsigned prim
= info
->mode
;
1019 unsigned count
= info
->count
;
1020 unsigned instance_count
= info
->instance_count
;
1021 unsigned num_prims_per_instance
= u_decomposed_prims_for_vertices(prim
, count
);
1022 unsigned num_prims
= num_prims_per_instance
* instance_count
;
1023 unsigned out_indexbuf_size
= num_prims
* 12;
1024 bool ring_full
= !si_check_ring_space(sctx
, out_indexbuf_size
);
1025 const unsigned split_prims_draw_level
= SPLIT_PRIMS_DRAW_LEVEL
;
1027 /* Split draws at the draw call level if the ring is full. This makes
1028 * better use of the ring space.
1031 num_prims
> split_prims_draw_level
&&
1032 instance_count
== 1 && /* TODO: support splitting instanced draws */
1033 (1 << prim
) & ((1 << PIPE_PRIM_TRIANGLES
) |
1034 (1 << PIPE_PRIM_TRIANGLE_STRIP
))) {
1036 struct pipe_draw_info split_draw
= *info
;
1037 split_draw
.primitive_restart
= primitive_restart
;
1039 unsigned base_start
= split_draw
.start
;
1041 if (prim
== PIPE_PRIM_TRIANGLES
) {
1042 unsigned vert_count_per_subdraw
= split_prims_draw_level
* 3;
1043 assert(vert_count_per_subdraw
< count
);
1045 for (unsigned start
= 0; start
< count
; start
+= vert_count_per_subdraw
) {
1046 split_draw
.start
= base_start
+ start
;
1047 split_draw
.count
= MIN2(count
- start
, vert_count_per_subdraw
);
1049 sctx
->b
.draw_vbo(&sctx
->b
, &split_draw
);
1051 } else if (prim
== PIPE_PRIM_TRIANGLE_STRIP
) {
1052 /* No primitive pair can be split, because strips reverse orientation
1053 * for odd primitives. */
1054 STATIC_ASSERT(split_prims_draw_level
% 2 == 0);
1056 unsigned vert_count_per_subdraw
= split_prims_draw_level
;
1058 for (unsigned start
= 0; start
< count
- 2; start
+= vert_count_per_subdraw
) {
1059 split_draw
.start
= base_start
+ start
;
1060 split_draw
.count
= MIN2(count
- start
, vert_count_per_subdraw
+ 2);
1062 sctx
->b
.draw_vbo(&sctx
->b
, &split_draw
);
1065 primitive_restart
&&
1066 sctx
->cs_prim_discard_state
.current
->key
.opt
.cs_need_correct_orientation
)
1067 sctx
->preserve_prim_restart_gds_at_flush
= true;
1069 sctx
->preserve_prim_restart_gds_at_flush
= false;
1074 return SI_PRIM_DISCARD_DRAW_SPLIT
;
1077 /* Just quit if the draw call doesn't fit into the ring and can't be split. */
1078 if (out_indexbuf_size
> sctx
->index_ring_size_per_ib
) {
1079 if (SI_PRIM_DISCARD_DEBUG
)
1080 puts("PD failed: draw call too big, can't be split");
1081 return SI_PRIM_DISCARD_DISABLED
;
1084 unsigned num_subdraws
= DIV_ROUND_UP(num_prims
, SPLIT_PRIMS_PACKET_LEVEL
);
1085 unsigned need_compute_dw
= 11 /* shader */ + 34 /* first draw */ +
1086 24 * (num_subdraws
- 1) + /* subdraws */
1087 20; /* leave some space at the end */
1088 unsigned need_gfx_dw
= si_get_minimum_num_gfx_cs_dwords(sctx
);
1090 if (sctx
->chip_class
<= GFX7
|| FORCE_REWIND_EMULATION
)
1091 need_gfx_dw
+= 9; /* NOP(2) + WAIT_REG_MEM(7), then chain */
1093 need_gfx_dw
+= num_subdraws
* 8; /* use REWIND(2) + DRAW(6) */
1096 (VERTEX_COUNTER_GDS_MODE
== 1 && sctx
->compute_gds_offset
+ 8 > GDS_SIZE_UNORDERED
) ||
1097 !sctx
->ws
->cs_check_space(gfx_cs
, need_gfx_dw
, false)) {
1098 /* If the current IB is empty but the size is too small, add a NOP
1099 * packet to force a flush and get a bigger IB.
1101 if (!radeon_emitted(gfx_cs
, sctx
->initial_gfx_cs_size
) &&
1102 gfx_cs
->current
.cdw
+ need_gfx_dw
> gfx_cs
->current
.max_dw
) {
1103 radeon_emit(gfx_cs
, PKT3(PKT3_NOP
, 0, 0));
1104 radeon_emit(gfx_cs
, 0);
1107 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1110 /* The compute IB is always chained, but we need to call cs_check_space to add more space. */
1111 struct radeon_cmdbuf
*cs
= sctx
->prim_discard_compute_cs
;
1112 ASSERTED
bool compute_has_space
= sctx
->ws
->cs_check_space(cs
, need_compute_dw
, false);
1113 assert(compute_has_space
);
1114 assert(si_check_ring_space(sctx
, out_indexbuf_size
));
1115 return SI_PRIM_DISCARD_ENABLED
;
1118 void si_compute_signal_gfx(struct si_context
*sctx
)
1120 struct radeon_cmdbuf
*cs
= sctx
->prim_discard_compute_cs
;
1121 unsigned writeback_L2_flags
= 0;
1123 /* The writeback L2 flags vary with each chip generation. */
1124 /* CI needs to flush vertex indices to memory. */
1125 if (sctx
->chip_class
<= GFX7
)
1126 writeback_L2_flags
= EVENT_TC_WB_ACTION_ENA
;
1127 else if (sctx
->chip_class
== GFX8
&& VERTEX_COUNTER_GDS_MODE
== 0)
1128 writeback_L2_flags
= EVENT_TC_WB_ACTION_ENA
| EVENT_TC_NC_ACTION_ENA
;
1130 if (!sctx
->compute_num_prims_in_batch
)
1133 assert(sctx
->compute_rewind_va
);
1135 /* After the queued dispatches are done and vertex counts are written to
1136 * the gfx IB, signal the gfx IB to continue. CP doesn't wait for
1137 * the dispatches to finish, it only adds the CS_DONE event into the event
1140 si_cp_release_mem(sctx
, cs
, V_028A90_CS_DONE
, writeback_L2_flags
,
1141 sctx
->chip_class
<= GFX8
? EOP_DST_SEL_MEM
: EOP_DST_SEL_TC_L2
,
1142 writeback_L2_flags
? EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
:
1144 EOP_DATA_SEL_VALUE_32BIT
,
1146 sctx
->compute_rewind_va
|
1147 ((uint64_t)sctx
->screen
->info
.address32_hi
<< 32),
1148 REWIND_SIGNAL_BIT
, /* signaling value for the REWIND packet */
1151 sctx
->compute_rewind_va
= 0;
1152 sctx
->compute_num_prims_in_batch
= 0;
1155 /* Dispatch a primitive discard compute shader. */
1156 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1157 const struct pipe_draw_info
*info
,
1158 unsigned index_size
,
1159 unsigned base_vertex
,
1160 uint64_t input_indexbuf_va
,
1161 unsigned input_indexbuf_num_elements
)
1163 struct radeon_cmdbuf
*gfx_cs
= sctx
->gfx_cs
;
1164 struct radeon_cmdbuf
*cs
= sctx
->prim_discard_compute_cs
;
1165 unsigned num_prims_per_instance
= u_decomposed_prims_for_vertices(info
->mode
, info
->count
);
1166 if (!num_prims_per_instance
)
1169 unsigned num_prims
= num_prims_per_instance
* info
->instance_count
;
1170 unsigned vertices_per_prim
, output_indexbuf_format
;
1172 switch (info
->mode
) {
1173 case PIPE_PRIM_TRIANGLES
:
1174 case PIPE_PRIM_TRIANGLE_STRIP
:
1175 case PIPE_PRIM_TRIANGLE_FAN
:
1176 vertices_per_prim
= 3;
1177 output_indexbuf_format
= V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1180 unreachable("unsupported primitive type");
1184 unsigned out_indexbuf_offset
;
1185 uint64_t output_indexbuf_size
= num_prims
* vertices_per_prim
* 4;
1186 bool first_dispatch
= !sctx
->prim_discard_compute_ib_initialized
;
1188 /* Initialize the compute IB if it's empty. */
1189 if (!sctx
->prim_discard_compute_ib_initialized
) {
1190 /* 1) State initialization. */
1191 sctx
->compute_gds_offset
= 0;
1192 sctx
->compute_ib_last_shader
= NULL
;
1194 if (sctx
->last_ib_barrier_fence
) {
1195 assert(!sctx
->last_ib_barrier_buf
);
1196 sctx
->ws
->cs_add_fence_dependency(gfx_cs
,
1197 sctx
->last_ib_barrier_fence
,
1198 RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY
);
1201 /* 2) IB initialization. */
1203 /* This needs to be done at the beginning of IBs due to possible
1204 * TTM buffer moves in the kernel.
1206 * TODO: update for GFX10
1208 si_emit_surface_sync(sctx
, cs
,
1209 S_0085F0_TC_ACTION_ENA(1) |
1210 S_0085F0_TCL1_ACTION_ENA(1) |
1211 S_0301F0_TC_WB_ACTION_ENA(sctx
->chip_class
>= GFX8
) |
1212 S_0085F0_SH_ICACHE_ACTION_ENA(1) |
1213 S_0085F0_SH_KCACHE_ACTION_ENA(1));
1215 /* Restore the GDS prim restart counter if needed. */
1216 if (sctx
->preserve_prim_restart_gds_at_flush
) {
1217 si_cp_copy_data(sctx
, cs
,
1218 COPY_DATA_GDS
, NULL
, 4,
1219 COPY_DATA_SRC_MEM
, sctx
->wait_mem_scratch
, 4);
1222 si_emit_initial_compute_regs(sctx
, cs
);
1224 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
1225 S_00B860_WAVES(sctx
->scratch_waves
) |
1226 S_00B860_WAVESIZE(0)); /* no scratch */
1228 /* Only 1D grids are launched. */
1229 radeon_set_sh_reg_seq(cs
, R_00B820_COMPUTE_NUM_THREAD_Y
, 2);
1230 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(1) |
1231 S_00B820_NUM_THREAD_PARTIAL(1));
1232 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(1) |
1233 S_00B824_NUM_THREAD_PARTIAL(1));
1235 radeon_set_sh_reg_seq(cs
, R_00B814_COMPUTE_START_Y
, 2);
1239 /* Disable ordered alloc for OA resources. */
1240 for (unsigned i
= 0; i
< 2; i
++) {
1241 radeon_set_uconfig_reg_seq(cs
, R_031074_GDS_OA_CNTL
, 3);
1242 radeon_emit(cs
, S_031074_INDEX(i
));
1244 radeon_emit(cs
, S_03107C_ENABLE(0));
1247 if (sctx
->last_ib_barrier_buf
) {
1248 assert(!sctx
->last_ib_barrier_fence
);
1249 radeon_add_to_buffer_list(sctx
, gfx_cs
, sctx
->last_ib_barrier_buf
,
1250 RADEON_USAGE_READ
, RADEON_PRIO_FENCE
);
1251 si_cp_wait_mem(sctx
, cs
,
1252 sctx
->last_ib_barrier_buf
->gpu_address
+
1253 sctx
->last_ib_barrier_buf_offset
, 1, 1,
1254 WAIT_REG_MEM_EQUAL
);
1257 sctx
->prim_discard_compute_ib_initialized
= true;
1260 /* Allocate the output index buffer. */
1261 output_indexbuf_size
= align(output_indexbuf_size
,
1262 sctx
->screen
->info
.tcc_cache_line_size
);
1263 assert(sctx
->index_ring_offset
+ output_indexbuf_size
<= sctx
->index_ring_size_per_ib
);
1264 out_indexbuf_offset
= sctx
->index_ring_base
+ sctx
->index_ring_offset
;
1265 sctx
->index_ring_offset
+= output_indexbuf_size
;
1267 radeon_add_to_buffer_list(sctx
, gfx_cs
, sctx
->index_ring
, RADEON_USAGE_READWRITE
,
1268 RADEON_PRIO_SHADER_RW_BUFFER
);
1269 uint64_t out_indexbuf_va
= sctx
->index_ring
->gpu_address
+ out_indexbuf_offset
;
1271 /* Prepare index buffer descriptors. */
1272 struct si_resource
*indexbuf_desc
= NULL
;
1273 unsigned indexbuf_desc_offset
;
1274 unsigned desc_size
= 12 * 4;
1277 u_upload_alloc(sctx
->b
.const_uploader
, 0, desc_size
,
1278 si_optimal_tcc_alignment(sctx
, desc_size
),
1279 &indexbuf_desc_offset
, (struct pipe_resource
**)&indexbuf_desc
,
1281 radeon_add_to_buffer_list(sctx
, gfx_cs
, indexbuf_desc
, RADEON_USAGE_READ
,
1282 RADEON_PRIO_DESCRIPTORS
);
1284 /* Input index buffer. */
1285 desc
[0] = input_indexbuf_va
;
1286 desc
[1] = S_008F04_BASE_ADDRESS_HI(input_indexbuf_va
>> 32) |
1287 S_008F04_STRIDE(index_size
);
1288 desc
[2] = input_indexbuf_num_elements
* (sctx
->chip_class
== GFX8
? index_size
: 1);
1289 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1290 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
1291 S_008F0C_DATA_FORMAT(index_size
== 1 ? V_008F0C_BUF_DATA_FORMAT_8
:
1292 index_size
== 2 ? V_008F0C_BUF_DATA_FORMAT_16
:
1293 V_008F0C_BUF_DATA_FORMAT_32
);
1295 /* Output index buffer. */
1296 desc
[4] = out_indexbuf_va
;
1297 desc
[5] = S_008F04_BASE_ADDRESS_HI(out_indexbuf_va
>> 32) |
1298 S_008F04_STRIDE(vertices_per_prim
* 4);
1299 desc
[6] = num_prims
* (sctx
->chip_class
== GFX8
? vertices_per_prim
* 4 : 1);
1300 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1301 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1302 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1303 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_0
) |
1304 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
1305 S_008F0C_DATA_FORMAT(output_indexbuf_format
);
1307 /* Viewport state. */
1308 struct si_small_prim_cull_info cull_info
;
1309 si_get_small_prim_cull_info(sctx
, &cull_info
);
1311 desc
[8] = fui(cull_info
.scale
[0]);
1312 desc
[9] = fui(cull_info
.scale
[1]);
1313 desc
[10] = fui(cull_info
.translate
[0]);
1314 desc
[11] = fui(cull_info
.translate
[1]);
1316 /* Better subpixel precision increases the efficiency of small
1317 * primitive culling. */
1318 unsigned num_samples
= sctx
->framebuffer
.nr_samples
;
1319 unsigned quant_mode
= sctx
->viewports
.as_scissor
[0].quant_mode
;
1320 float small_prim_cull_precision
;
1322 if (quant_mode
== SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
)
1323 small_prim_cull_precision
= num_samples
/ 4096.0;
1324 else if (quant_mode
== SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
)
1325 small_prim_cull_precision
= num_samples
/ 1024.0;
1327 small_prim_cull_precision
= num_samples
/ 256.0;
1329 /* Set user data SGPRs. */
1330 /* This can't be greater than 14 if we want the fastest launch rate. */
1331 unsigned user_sgprs
= 13;
1333 uint64_t index_buffers_va
= indexbuf_desc
->gpu_address
+ indexbuf_desc_offset
;
1334 unsigned vs_const_desc
= si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX
);
1335 unsigned vs_sampler_desc
= si_sampler_and_image_descriptors_idx(PIPE_SHADER_VERTEX
);
1336 uint64_t vs_const_desc_va
= sctx
->descriptors
[vs_const_desc
].gpu_address
;
1337 uint64_t vs_sampler_desc_va
= sctx
->descriptors
[vs_sampler_desc
].gpu_address
;
1338 uint64_t vb_desc_va
= sctx
->vb_descriptors_buffer
?
1339 sctx
->vb_descriptors_buffer
->gpu_address
+
1340 sctx
->vb_descriptors_offset
: 0;
1341 unsigned gds_offset
, gds_size
;
1342 struct si_fast_udiv_info32 num_prims_udiv
= {};
1344 if (info
->instance_count
> 1)
1345 num_prims_udiv
= si_compute_fast_udiv_info32(num_prims_per_instance
, 31);
1347 /* Limitations on how these two are packed in the user SGPR. */
1348 assert(num_prims_udiv
.post_shift
< 32);
1349 assert(num_prims_per_instance
< 1 << 27);
1351 si_resource_reference(&indexbuf_desc
, NULL
);
1353 bool primitive_restart
= sctx
->cs_prim_discard_state
.current
->key
.opt
.cs_primitive_restart
;
1355 if (VERTEX_COUNTER_GDS_MODE
== 1) {
1356 gds_offset
= sctx
->compute_gds_offset
;
1357 gds_size
= primitive_restart
? 8 : 4;
1358 sctx
->compute_gds_offset
+= gds_size
;
1360 /* Reset the counters in GDS for the first dispatch using WRITE_DATA.
1361 * The remainder of the GDS will be cleared after the dispatch packet
1362 * in parallel with compute shaders.
1364 if (first_dispatch
) {
1365 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + gds_size
/4, 0));
1366 radeon_emit(cs
, S_370_DST_SEL(V_370_GDS
) | S_370_WR_CONFIRM(1));
1367 radeon_emit(cs
, gds_offset
);
1369 radeon_emit(cs
, 0); /* value to write */
1375 /* Set shader registers. */
1376 struct si_shader
*shader
= sctx
->cs_prim_discard_state
.current
;
1378 if (shader
!= sctx
->compute_ib_last_shader
) {
1379 radeon_add_to_buffer_list(sctx
, gfx_cs
, shader
->bo
, RADEON_USAGE_READ
,
1380 RADEON_PRIO_SHADER_BINARY
);
1381 uint64_t shader_va
= shader
->bo
->gpu_address
;
1383 assert(shader
->config
.scratch_bytes_per_wave
== 0);
1384 assert(shader
->config
.num_vgprs
* WAVES_PER_TG
<= 256 * 4);
1386 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
1387 radeon_emit(cs
, shader_va
>> 8);
1388 radeon_emit(cs
, S_00B834_DATA(shader_va
>> 40));
1390 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
1391 radeon_emit(cs
, S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1392 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1393 S_00B848_FLOAT_MODE(shader
->config
.float_mode
) |
1394 S_00B848_DX10_CLAMP(1));
1395 radeon_emit(cs
, S_00B84C_SCRATCH_EN(0 /* no scratch */) |
1396 S_00B84C_USER_SGPR(user_sgprs
) |
1397 S_00B84C_TGID_X_EN(1 /* only blockID.x is used */) |
1398 S_00B84C_TG_SIZE_EN(VERTEX_COUNTER_GDS_MODE
== 2 /* need the wave ID */) |
1399 S_00B84C_TIDIG_COMP_CNT(0 /* only threadID.x is used */) |
1400 S_00B84C_LDS_SIZE(shader
->config
.lds_size
));
1402 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
1403 ac_get_compute_resource_limits(&sctx
->screen
->info
,
1406 THREADGROUPS_PER_CU
));
1407 sctx
->compute_ib_last_shader
= shader
;
1410 STATIC_ASSERT(SPLIT_PRIMS_PACKET_LEVEL
% THREADGROUP_SIZE
== 0);
1412 /* Big draw calls are split into smaller dispatches and draw packets. */
1413 for (unsigned start_prim
= 0; start_prim
< num_prims
; start_prim
+= SPLIT_PRIMS_PACKET_LEVEL
) {
1414 unsigned num_subdraw_prims
;
1416 if (start_prim
+ SPLIT_PRIMS_PACKET_LEVEL
< num_prims
)
1417 num_subdraw_prims
= SPLIT_PRIMS_PACKET_LEVEL
;
1419 num_subdraw_prims
= num_prims
- start_prim
;
1421 /* Small dispatches are executed back to back until a specific primitive
1422 * count is reached. Then, a CS_DONE is inserted to signal the gfx IB
1423 * to start drawing the batch. This batching adds latency to the gfx IB,
1424 * but CS_DONE and REWIND are too slow.
1426 if (sctx
->compute_num_prims_in_batch
+ num_subdraw_prims
> PRIMS_PER_BATCH
)
1427 si_compute_signal_gfx(sctx
);
1429 if (sctx
->compute_num_prims_in_batch
== 0) {
1430 assert((gfx_cs
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
1431 sctx
->compute_rewind_va
= gfx_cs
->gpu_address
+ (gfx_cs
->current
.cdw
+ 1) * 4;
1433 if (sctx
->chip_class
<= GFX7
|| FORCE_REWIND_EMULATION
) {
1434 radeon_emit(gfx_cs
, PKT3(PKT3_NOP
, 0, 0));
1435 radeon_emit(gfx_cs
, 0);
1437 si_cp_wait_mem(sctx
, gfx_cs
,
1438 sctx
->compute_rewind_va
|
1439 (uint64_t)sctx
->screen
->info
.address32_hi
<< 32,
1440 REWIND_SIGNAL_BIT
, REWIND_SIGNAL_BIT
,
1441 WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_PFP
);
1443 /* Use INDIRECT_BUFFER to chain to a different buffer
1444 * to discard the CP prefetch cache.
1446 sctx
->ws
->cs_check_space(gfx_cs
, 0, true);
1448 radeon_emit(gfx_cs
, PKT3(PKT3_REWIND
, 0, 0));
1449 radeon_emit(gfx_cs
, 0);
1453 sctx
->compute_num_prims_in_batch
+= num_subdraw_prims
;
1455 uint32_t count_va
= gfx_cs
->gpu_address
+ (gfx_cs
->current
.cdw
+ 4) * 4;
1456 uint64_t index_va
= out_indexbuf_va
+ start_prim
* 12;
1458 /* Emit the draw packet into the gfx IB. */
1459 radeon_emit(gfx_cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, 0));
1460 radeon_emit(gfx_cs
, num_prims
* vertices_per_prim
);
1461 radeon_emit(gfx_cs
, index_va
);
1462 radeon_emit(gfx_cs
, index_va
>> 32);
1463 radeon_emit(gfx_cs
, 0);
1464 radeon_emit(gfx_cs
, V_0287F0_DI_SRC_SEL_DMA
);
1466 /* Continue with the compute IB. */
1467 if (start_prim
== 0) {
1468 uint32_t gds_prim_restart_continue_bit
= 0;
1470 if (sctx
->preserve_prim_restart_gds_at_flush
) {
1471 assert(primitive_restart
&&
1472 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP
);
1473 assert(start_prim
< 1 << 31);
1474 gds_prim_restart_continue_bit
= 1 << 31;
1477 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, user_sgprs
);
1478 radeon_emit(cs
, index_buffers_va
);
1480 VERTEX_COUNTER_GDS_MODE
== 0 ? count_va
:
1481 VERTEX_COUNTER_GDS_MODE
== 1 ? gds_offset
:
1483 gds_prim_restart_continue_bit
);
1484 radeon_emit(cs
, start_prim
+ num_subdraw_prims
- 1);
1485 radeon_emit(cs
, count_va
);
1486 radeon_emit(cs
, vb_desc_va
);
1487 radeon_emit(cs
, vs_const_desc_va
);
1488 radeon_emit(cs
, vs_sampler_desc_va
);
1489 radeon_emit(cs
, base_vertex
);
1490 radeon_emit(cs
, info
->start_instance
);
1491 radeon_emit(cs
, num_prims_udiv
.multiplier
);
1492 radeon_emit(cs
, num_prims_udiv
.post_shift
|
1493 (num_prims_per_instance
<< 5));
1494 radeon_emit(cs
, info
->restart_index
);
1495 /* small-prim culling precision (same as rasterizer precision = QUANT_MODE) */
1496 radeon_emit(cs
, fui(small_prim_cull_precision
));
1498 assert(VERTEX_COUNTER_GDS_MODE
== 2);
1499 /* Only update the SGPRs that changed. */
1500 radeon_set_sh_reg_seq(cs
, R_00B904_COMPUTE_USER_DATA_1
, 3);
1501 radeon_emit(cs
, start_prim
);
1502 radeon_emit(cs
, start_prim
+ num_subdraw_prims
- 1);
1503 radeon_emit(cs
, count_va
);
1506 /* Set grid dimensions. */
1507 unsigned start_block
= start_prim
/ THREADGROUP_SIZE
;
1508 unsigned num_full_blocks
= num_subdraw_prims
/ THREADGROUP_SIZE
;
1509 unsigned partial_block_size
= num_subdraw_prims
% THREADGROUP_SIZE
;
1511 radeon_set_sh_reg(cs
, R_00B810_COMPUTE_START_X
, start_block
);
1512 radeon_set_sh_reg(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
,
1513 S_00B81C_NUM_THREAD_FULL(THREADGROUP_SIZE
) |
1514 S_00B81C_NUM_THREAD_PARTIAL(partial_block_size
));
1516 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
1517 PKT3_SHADER_TYPE_S(1));
1518 radeon_emit(cs
, start_block
+ num_full_blocks
+ !!partial_block_size
);
1521 radeon_emit(cs
, S_00B800_COMPUTE_SHADER_EN(1) |
1522 S_00B800_PARTIAL_TG_EN(!!partial_block_size
) |
1523 S_00B800_ORDERED_APPEND_ENBL(VERTEX_COUNTER_GDS_MODE
== 2) |
1524 S_00B800_ORDER_MODE(0 /* launch in order */));
1526 /* This is only for unordered append. Ordered append writes this from
1529 * Note that EOP and EOS events are super slow, so emulating the event
1530 * in a shader is an important optimization.
1532 if (VERTEX_COUNTER_GDS_MODE
== 1) {
1533 si_cp_release_mem(sctx
, cs
, V_028A90_CS_DONE
, 0,
1534 sctx
->chip_class
<= GFX8
? EOP_DST_SEL_MEM
: EOP_DST_SEL_TC_L2
,
1538 count_va
| ((uint64_t)sctx
->screen
->info
.address32_hi
<< 32),
1539 EOP_DATA_GDS(gds_offset
/ 4, 1),
1542 /* Now that compute shaders are running, clear the remainder of GDS. */
1543 if (first_dispatch
) {
1544 unsigned offset
= gds_offset
+ gds_size
;
1545 si_cp_dma_clear_buffer(sctx
, cs
, NULL
, offset
,
1546 GDS_SIZE_UNORDERED
- offset
,
1548 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
1549 SI_CPDMA_SKIP_GFX_SYNC
|
1550 SI_CPDMA_SKIP_SYNC_BEFORE
,
1551 SI_COHERENCY_NONE
, L2_BYPASS
);
1554 first_dispatch
= false;
1556 assert(cs
->current
.cdw
<= cs
->current
.max_dw
);
1557 assert(gfx_cs
->current
.cdw
<= gfx_cs
->current
.max_dw
);