src/gallium/drivers/radeonsi/si_cp_dma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák <maraeo@gmail.com>
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "sid.h"
  29 #include "radeon/r600_cs.h"
  30
  31 /* Set this if you want the ME to wait until CP DMA is done.
  32  * It should be set on the last CP DMA packet. */
  33 #define CP_DMA_SYNC             (1 << 0)
  34
  35 /* Set this if the source data was used as a destination in a previous CP DMA
  36  * packet. It's for preventing a read-after-write (RAW) hazard between two
  37  * CP DMA packets. */
  38 #define CP_DMA_RAW_WAIT         (1 << 1)
  39 #define CP_DMA_USE_L2           (1 << 2) /* CIK+ */
  40 #define CP_DMA_CLEAR            (1 << 3)
  41
  42 /* The max number of bytes that can be copied per packet. */
  43 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
  44 {
  45         unsigned max = sctx->b.chip_class >= GFX9 ?
  46                                S_414_BYTE_COUNT_GFX9(~0u) :
  47                                S_414_BYTE_COUNT_GFX6(~0u);
  48
  49         /* make it aligned for optimal performance */
  50         return max & ~(SI_CPDMA_ALIGNMENT - 1);
  51 }
  52
  53
  54 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
  55  * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
  56  * clear value.
  57  */
  58 static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
  59                            uint64_t src_va, unsigned size, unsigned flags,
  60                            enum r600_coherency coher)
  61 {
  62         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  63         uint32_t header = 0, command = 0;
  64
  65         assert(size);
  66         assert(size <= cp_dma_max_byte_count(sctx));
  67
  68         if (sctx->b.chip_class >= GFX9)
  69                 command |= S_414_BYTE_COUNT_GFX9(size);
  70         else
  71                 command |= S_414_BYTE_COUNT_GFX6(size);
  72
  73         /* Sync flags. */
  74         if (flags & CP_DMA_SYNC)
  75                 header |= S_411_CP_SYNC(1);
  76         else {
  77                 if (sctx->b.chip_class >= GFX9)
  78                         command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
  79                 else
  80                         command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
  81         }
  82
  83         if (flags & CP_DMA_RAW_WAIT)
  84                 command |= S_414_RAW_WAIT(1);
  85
  86         /* Src and dst flags. */
  87         if (sctx->b.chip_class >= GFX9 && src_va == dst_va)
  88                 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
  89         else if (flags & CP_DMA_USE_L2)
  90                 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
  91
  92         if (flags & CP_DMA_CLEAR)
  93                 header |= S_411_SRC_SEL(V_411_DATA);
  94         else if (flags & CP_DMA_USE_L2)
  95                 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
  96
  97         if (sctx->b.chip_class >= CIK) {
  98                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
  99                 radeon_emit(cs, header);
 100                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 101                 radeon_emit(cs, src_va >> 32);  /* SRC_ADDR_HI [31:0] */
 102                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 103                 radeon_emit(cs, dst_va >> 32);  /* DST_ADDR_HI [31:0] */
 104                 radeon_emit(cs, command);
 105         } else {
 106                 header |= S_411_SRC_ADDR_HI(src_va >> 32);
 107
 108                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 109                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 110                 radeon_emit(cs, header);        /* SRC_ADDR_HI [15:0] + flags. */
 111                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 112                 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
 113                 radeon_emit(cs, command);
 114         }
 115
 116         /* CP DMA is executed in ME, but index buffers are read by PFP.
 117          * This ensures that ME (CP DMA) is idle before PFP starts fetching
 118          * indices. If we wanted to execute CP DMA in PFP, this packet
 119          * should precede it.
 120          */
 121         if (coher == R600_COHERENCY_SHADER && flags & CP_DMA_SYNC) {
 122                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 123                 radeon_emit(cs, 0);
 124         }
 125 }
 126
 127 static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher)
 128 {
 129         switch (coher) {
 130         default:
 131         case R600_COHERENCY_NONE:
 132                 return 0;
 133         case R600_COHERENCY_SHADER:
 134                 return SI_CONTEXT_INV_SMEM_L1 |
 135                        SI_CONTEXT_INV_VMEM_L1 |
 136                        (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 137         case R600_COHERENCY_CB_META:
 138                 return SI_CONTEXT_FLUSH_AND_INV_CB;
 139         }
 140 }
 141
 142 static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher)
 143 {
 144         return coher == R600_COHERENCY_SHADER &&
 145                sctx->b.chip_class >= CIK ? CP_DMA_USE_L2 : 0;
 146 }
 147
 148 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 149                               struct pipe_resource *src, unsigned byte_count,
 150                               uint64_t remaining_size, unsigned user_flags,
 151                               bool *is_first, unsigned *packet_flags)
 152 {
 153         /* Fast exit for a CPDMA prefetch. */
 154         if ((user_flags & SI_CPDMA_SKIP_ALL) == SI_CPDMA_SKIP_ALL) {
 155                 *is_first = false;
 156                 return;
 157         }
 158
 159         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 160                 /* Count memory usage in so that need_cs_space can take it into account. */
 161                 r600_context_add_resource_size(&sctx->b.b, dst);
 162                 if (src)
 163                         r600_context_add_resource_size(&sctx->b.b, src);
 164         }
 165
 166         if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
 167                 si_need_cs_space(sctx);
 168
 169         /* This must be done after need_cs_space. */
 170         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 171                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 172                                           (struct r600_resource*)dst,
 173                                           RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 174                 if (src)
 175                         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 176                                                   (struct r600_resource*)src,
 177                                                   RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 178         }
 179
 180         /* Flush the caches for the first copy only.
 181          * Also wait for the previous CP DMA operations.
 182          */
 183         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->b.flags)
 184                 si_emit_cache_flush(sctx);
 185
 186         if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
 187                 *packet_flags |= CP_DMA_RAW_WAIT;
 188
 189         *is_first = false;
 190
 191         /* Do the synchronization after the last dma, so that all data
 192          * is written to memory.
 193          */
 194         if (!(user_flags & SI_CPDMA_SKIP_SYNC_AFTER) &&
 195             byte_count == remaining_size)
 196                 *packet_flags |= CP_DMA_SYNC;
 197 }
 198
 199 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 200                             uint64_t offset, uint64_t size, unsigned value,
 201                             enum r600_coherency coher)
 202 {
 203         struct si_context *sctx = (struct si_context*)ctx;
 204         struct radeon_winsys *ws = sctx->b.ws;
 205         struct r600_resource *rdst = r600_resource(dst);
 206         unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
 207         unsigned flush_flags = get_flush_flags(sctx, coher);
 208         uint64_t dma_clear_size;
 209         bool is_first = true;
 210
 211         if (!size)
 212                 return;
 213
 214         dma_clear_size = size & ~3llu;
 215
 216         /* Mark the buffer range of destination as valid (initialized),
 217          * so that transfer_map knows it should wait for the GPU when mapping
 218          * that range. */
 219         util_range_add(&rdst->valid_buffer_range, offset,
 220                        offset + dma_clear_size);
 221
 222         /* dma_clear_buffer can use clear_buffer on failure. Make sure that
 223          * doesn't happen. We don't want an infinite recursion: */
 224         if (sctx->b.dma.cs &&
 225             (offset % 4 == 0) &&
 226             /* CP DMA is very slow. Always use SDMA for big clears. This
 227              * alone improves DeusEx:MD performance by 70%. */
 228             (size > 128 * 1024 ||
 229              /* Buffers not used by the GFX IB yet will be cleared by SDMA.
 230               * This happens to move most buffer clears to SDMA, including
 231               * DCC and CMASK clears, because pipe->clear clears them before
 232               * si_emit_framebuffer_state (in a draw call) adds them.
 233               * For example, DeusEx:MD has 21 buffer clears per frame and all
 234               * of them are moved to SDMA thanks to this. */
 235              !ws->cs_is_buffer_referenced(sctx->b.gfx.cs, rdst->buf,
 236                                           RADEON_USAGE_READWRITE))) {
 237                 sctx->b.dma_clear_buffer(ctx, dst, offset, dma_clear_size, value);
 238
 239                 offset += dma_clear_size;
 240                 size -= dma_clear_size;
 241         } else if (dma_clear_size >= 4) {
 242                 uint64_t va = rdst->gpu_address + offset;
 243
 244                 offset += dma_clear_size;
 245                 size -= dma_clear_size;
 246
 247                 /* Flush the caches. */
 248                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 249                                  SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 250
 251                 while (dma_clear_size) {
 252                         unsigned byte_count = MIN2(dma_clear_size, cp_dma_max_byte_count(sctx));
 253                         unsigned dma_flags = tc_l2_flag  | CP_DMA_CLEAR;
 254
 255                         si_cp_dma_prepare(sctx, dst, NULL, byte_count, dma_clear_size, 0,
 256                                           &is_first, &dma_flags);
 257
 258                         /* Emit the clear packet. */
 259                         si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, coher);
 260
 261                         dma_clear_size -= byte_count;
 262                         va += byte_count;
 263                 }
 264
 265                 if (tc_l2_flag)
 266                         rdst->TC_L2_dirty = true;
 267
 268                 /* If it's not a framebuffer fast clear... */
 269                 if (coher == R600_COHERENCY_SHADER)
 270                         sctx->b.num_cp_dma_calls++;
 271         }
 272
 273         if (size) {
 274                 /* Handle non-dword alignment.
 275                  *
 276                  * This function is called for embedded texture metadata clears,
 277                  * but those should always be properly aligned. */
 278                 assert(dst->target == PIPE_BUFFER);
 279                 assert(size < 4);
 280
 281                 pipe_buffer_write(ctx, dst, offset, size, &value);
 282         }
 283 }
 284
 285 /**
 286  * Realign the CP DMA engine. This must be done after a copy with an unaligned
 287  * size.
 288  *
 289  * \param size  Remaining size to the CP DMA alignment.
 290  */
 291 static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 292                                      unsigned user_flags, bool *is_first)
 293 {
 294         uint64_t va;
 295         unsigned dma_flags = 0;
 296         unsigned scratch_size = SI_CPDMA_ALIGNMENT * 2;
 297
 298         assert(size < SI_CPDMA_ALIGNMENT);
 299
 300         /* Use the scratch buffer as the dummy buffer. The 3D engine should be
 301          * idle at this point.
 302          */
 303         if (!sctx->scratch_buffer ||
 304             sctx->scratch_buffer->b.b.width0 < scratch_size) {
 305                 r600_resource_reference(&sctx->scratch_buffer, NULL);
 306                 sctx->scratch_buffer = (struct r600_resource*)
 307                         r600_aligned_buffer_create(&sctx->screen->b.b,
 308                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 309                                                    PIPE_USAGE_DEFAULT,
 310                                                    scratch_size, 256);
 311                 if (!sctx->scratch_buffer)
 312                         return;
 313
 314                 si_mark_atom_dirty(sctx, &sctx->scratch_state);
 315         }
 316
 317         si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
 318                           &sctx->scratch_buffer->b.b, size, size, user_flags,
 319                           is_first, &dma_flags);
 320
 321         va = sctx->scratch_buffer->gpu_address;
 322         si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
 323                        R600_COHERENCY_SHADER);
 324 }
 325
 326 /**
 327  * Do memcpy between buffers using CP DMA.
 328  *
 329  * \param user_flags    bitmask of SI_CPDMA_*
 330  */
 331 void si_copy_buffer(struct si_context *sctx,
 332                     struct pipe_resource *dst, struct pipe_resource *src,
 333                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 334                     unsigned user_flags)
 335 {
 336         uint64_t main_dst_offset, main_src_offset;
 337         unsigned skipped_size = 0;
 338         unsigned realign_size = 0;
 339         unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER);
 340         unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER);
 341         bool is_first = true;
 342
 343         if (!size)
 344                 return;
 345
 346         if (dst != src || dst_offset != src_offset) {
 347                 /* Mark the buffer range of destination as valid (initialized),
 348                  * so that transfer_map knows it should wait for the GPU when mapping
 349                  * that range. */
 350                 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
 351                                dst_offset + size);
 352         }
 353
 354         dst_offset += r600_resource(dst)->gpu_address;
 355         src_offset += r600_resource(src)->gpu_address;
 356
 357         /* The workarounds aren't needed on Fiji and beyond. */
 358         if (sctx->b.family <= CHIP_CARRIZO ||
 359             sctx->b.family == CHIP_STONEY) {
 360                 /* If the size is not aligned, we must add a dummy copy at the end
 361                  * just to align the internal counter. Otherwise, the DMA engine
 362                  * would slow down by an order of magnitude for following copies.
 363                  */
 364                 if (size % SI_CPDMA_ALIGNMENT)
 365                         realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
 366
 367                 /* If the copy begins unaligned, we must start copying from the next
 368                  * aligned block and the skipped part should be copied after everything
 369                  * else has been copied. Only the src alignment matters, not dst.
 370                  */
 371                 if (src_offset % SI_CPDMA_ALIGNMENT) {
 372                         skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT);
 373                         /* The main part will be skipped if the size is too small. */
 374                         skipped_size = MIN2(skipped_size, size);
 375                         size -= skipped_size;
 376                 }
 377         }
 378
 379         /* Flush the caches. */
 380         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC))
 381                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 382                                  SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 383
 384         /* This is the main part doing the copying. Src is always aligned. */
 385         main_dst_offset = dst_offset + skipped_size;
 386         main_src_offset = src_offset + skipped_size;
 387
 388         while (size) {
 389                 unsigned dma_flags = tc_l2_flag;
 390                 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
 391
 392                 si_cp_dma_prepare(sctx, dst, src, byte_count,
 393                                   size + skipped_size + realign_size,
 394                                   user_flags, &is_first, &dma_flags);
 395
 396                 si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
 397                                byte_count, dma_flags, R600_COHERENCY_SHADER);
 398
 399                 size -= byte_count;
 400                 main_src_offset += byte_count;
 401                 main_dst_offset += byte_count;
 402         }
 403
 404         /* Copy the part we skipped because src wasn't aligned. */
 405         if (skipped_size) {
 406                 unsigned dma_flags = tc_l2_flag;
 407
 408                 si_cp_dma_prepare(sctx, dst, src, skipped_size,
 409                                   skipped_size + realign_size, user_flags,
 410                                   &is_first, &dma_flags);
 411
 412                 si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
 413                                dma_flags, R600_COHERENCY_SHADER);
 414         }
 415
 416         /* Finally, realign the engine if the size wasn't aligned. */
 417         if (realign_size)
 418                 si_cp_dma_realign_engine(sctx, realign_size, user_flags,
 419                                          &is_first);
 420
 421         if (tc_l2_flag)
 422                 r600_resource(dst)->TC_L2_dirty = true;
 423
 424         /* If it's not a prefetch... */
 425         if (dst_offset != src_offset)
 426                 sctx->b.num_cp_dma_calls++;
 427 }
 428
 429 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 430                               uint64_t offset, unsigned size)
 431 {
 432         assert(sctx->b.chip_class >= CIK);
 433
 434         si_copy_buffer(sctx, buf, buf, offset, offset, size, SI_CPDMA_SKIP_ALL);
 435 }
 436
 437 static void cik_prefetch_shader_async(struct si_context *sctx,
 438                                       struct si_pm4_state *state)
 439 {
 440         if (state) {
 441                 struct pipe_resource *bo = &state->bo[0]->b.b;
 442                 assert(state->nbo == 1);
 443
 444                 cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
 445         }
 446 }
 447
 448 static void cik_emit_prefetch_L2(struct si_context *sctx, struct r600_atom *atom)
 449 {
 450         /* Prefetch shaders and VBO descriptors to TC L2. */
 451         if (si_pm4_state_changed(sctx, ls))
 452                 cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
 453         if (si_pm4_state_changed(sctx, hs))
 454                 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 455         if (si_pm4_state_changed(sctx, es))
 456                 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
 457         if (si_pm4_state_changed(sctx, gs))
 458                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 459         if (si_pm4_state_changed(sctx, vs))
 460                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 461
 462         /* Vertex buffer descriptors are uploaded uncached, so prefetch
 463          * them right after the VS binary. */
 464         if (sctx->vertex_buffer_pointer_dirty) {
 465                 cik_prefetch_TC_L2_async(sctx, &sctx->vertex_buffers.buffer->b.b,
 466                                          sctx->vertex_buffers.buffer_offset,
 467                                          sctx->vertex_elements->desc_list_byte_size);
 468         }
 469         if (si_pm4_state_changed(sctx, ps))
 470                 cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
 471 }
 472
 473 void si_init_cp_dma_functions(struct si_context *sctx)
 474 {
 475         sctx->b.clear_buffer = si_clear_buffer;
 476
 477         si_init_atom(sctx, &sctx->prefetch_L2, &sctx->atoms.s.prefetch_L2,
 478                      cik_emit_prefetch_L2);
 479 }