src/gallium/drivers/radeonsi/si_cp_dma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák <maraeo@gmail.com>
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "sid.h"
  29 #include "radeon/r600_cs.h"
  30
  31 /* Alignment for optimal performance. */
  32 #define CP_DMA_ALIGNMENT        32
  33 /* The max number of bytes to copy per packet. */
  34 #define CP_DMA_MAX_BYTE_COUNT   ((1 << 21) - CP_DMA_ALIGNMENT)
  35
  36 /* Set this if you want the ME to wait until CP DMA is done.
  37  * It should be set on the last CP DMA packet. */
  38 #define CP_DMA_SYNC             (1 << 0)
  39
  40 /* Set this if the source data was used as a destination in a previous CP DMA
  41  * packet. It's for preventing a read-after-write (RAW) hazard between two
  42  * CP DMA packets. */
  43 #define CP_DMA_RAW_WAIT         (1 << 1)
  44 #define CP_DMA_USE_L2           (1 << 2) /* CIK+ */
  45 #define CP_DMA_CLEAR            (1 << 3)
  46
  47 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
  48  * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
  49  * clear value.
  50  */
  51 static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
  52                            uint64_t src_va, unsigned size, unsigned flags,
  53                            enum r600_coherency coher)
  54 {
  55         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  56         uint32_t header = 0, command = S_414_BYTE_COUNT(size);
  57
  58         assert(size);
  59         assert(size <= CP_DMA_MAX_BYTE_COUNT);
  60
  61         /* Sync flags. */
  62         if (flags & CP_DMA_SYNC)
  63                 header |= S_411_CP_SYNC(1);
  64         else
  65                 command |= S_414_DISABLE_WR_CONFIRM(1);
  66
  67         if (flags & CP_DMA_RAW_WAIT)
  68                 command |= S_414_RAW_WAIT(1);
  69
  70         /* Src and dst flags. */
  71         if (flags & CP_DMA_USE_L2)
  72                 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
  73
  74         if (flags & CP_DMA_CLEAR)
  75                 header |= S_411_SRC_SEL(V_411_DATA);
  76         else if (flags & CP_DMA_USE_L2)
  77                 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
  78
  79         if (sctx->b.chip_class >= CIK) {
  80                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
  81                 radeon_emit(cs, header);
  82                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
  83                 radeon_emit(cs, src_va >> 32);  /* SRC_ADDR_HI [31:0] */
  84                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
  85                 radeon_emit(cs, dst_va >> 32);  /* DST_ADDR_HI [31:0] */
  86                 radeon_emit(cs, command);
  87         } else {
  88                 header |= S_411_SRC_ADDR_HI(src_va >> 32);
  89
  90                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
  91                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
  92                 radeon_emit(cs, header);        /* SRC_ADDR_HI [15:0] + flags. */
  93                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
  94                 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
  95                 radeon_emit(cs, command);
  96         }
  97
  98         /* CP DMA is executed in ME, but index buffers are read by PFP.
  99          * This ensures that ME (CP DMA) is idle before PFP starts fetching
 100          * indices. If we wanted to execute CP DMA in PFP, this packet
 101          * should precede it.
 102          */
 103         if (coher == R600_COHERENCY_SHADER && flags & CP_DMA_SYNC) {
 104                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 105                 radeon_emit(cs, 0);
 106         }
 107 }
 108
 109 static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher)
 110 {
 111         switch (coher) {
 112         default:
 113         case R600_COHERENCY_NONE:
 114                 return 0;
 115         case R600_COHERENCY_SHADER:
 116                 return SI_CONTEXT_INV_SMEM_L1 |
 117                        SI_CONTEXT_INV_VMEM_L1 |
 118                        (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 119         case R600_COHERENCY_CB_META:
 120                 return SI_CONTEXT_FLUSH_AND_INV_CB |
 121                        SI_CONTEXT_FLUSH_AND_INV_CB_META;
 122         }
 123 }
 124
 125 static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher)
 126 {
 127         return coher == R600_COHERENCY_SHADER &&
 128                sctx->b.chip_class >= CIK ? CP_DMA_USE_L2 : 0;
 129 }
 130
 131 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 132                               struct pipe_resource *src, unsigned byte_count,
 133                               uint64_t remaining_size,
 134                               bool *is_first, unsigned *packet_flags)
 135 {
 136         /* Count memory usage in so that need_cs_space can take it into account. */
 137         r600_context_add_resource_size(&sctx->b.b, dst);
 138         if (src)
 139                 r600_context_add_resource_size(&sctx->b.b, src);
 140
 141         si_need_cs_space(sctx);
 142
 143         /* This must be done after need_cs_space. */
 144         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 145                                   (struct r600_resource*)dst,
 146                                   RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 147         if (src)
 148                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 149                                           (struct r600_resource*)src,
 150                                           RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 151
 152         /* Flush the caches for the first copy only.
 153          * Also wait for the previous CP DMA operations.
 154          */
 155         if (sctx->b.flags)
 156                 si_emit_cache_flush(sctx);
 157
 158         if (*is_first)
 159                 *packet_flags |= CP_DMA_RAW_WAIT;
 160
 161         *is_first = false;
 162
 163         /* Do the synchronization after the last dma, so that all data
 164          * is written to memory.
 165          */
 166         if (byte_count == remaining_size)
 167                 *packet_flags |= CP_DMA_SYNC;
 168 }
 169
 170 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 171                             uint64_t offset, uint64_t size, unsigned value,
 172                             enum r600_coherency coher)
 173 {
 174         struct si_context *sctx = (struct si_context*)ctx;
 175         struct radeon_winsys *ws = sctx->b.ws;
 176         struct r600_resource *rdst = r600_resource(dst);
 177         unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
 178         unsigned flush_flags = get_flush_flags(sctx, coher);
 179         bool is_first = true;
 180
 181         if (!size)
 182                 return;
 183
 184         /* Mark the buffer range of destination as valid (initialized),
 185          * so that transfer_map knows it should wait for the GPU when mapping
 186          * that range. */
 187         util_range_add(&rdst->valid_buffer_range, offset,
 188                        offset + size);
 189
 190         /* Fallback for unaligned clears. */
 191         if (offset % 4 != 0 || size % 4 != 0) {
 192                 uint8_t *map = r600_buffer_map_sync_with_rings(&sctx->b, rdst,
 193                                                                PIPE_TRANSFER_WRITE);
 194                 map += offset;
 195                 for (uint64_t i = 0; i < size; i++) {
 196                         unsigned byte_within_dword = (offset + i) % 4;
 197                         *map++ = (value >> (byte_within_dword * 8)) & 0xff;
 198                 }
 199                 return;
 200         }
 201
 202         /* dma_clear_buffer can use clear_buffer on failure. Make sure that
 203          * doesn't happen. We don't want an infinite recursion: */
 204         if (sctx->b.dma.cs &&
 205             /* CP DMA is very slow. Always use SDMA for big clears. This
 206              * alone improves DeusEx:MD performance by 70%. */
 207             (size > 128 * 1024 ||
 208              /* Buffers not used by the GFX IB yet will be cleared by SDMA.
 209               * This happens to move most buffer clears to SDMA, including
 210               * DCC and CMASK clears, because pipe->clear clears them before
 211               * si_emit_framebuffer_state (in a draw call) adds them.
 212               * For example, DeusEx:MD has 21 buffer clears per frame and all
 213               * of them are moved to SDMA thanks to this. */
 214              !ws->cs_is_buffer_referenced(sctx->b.gfx.cs, rdst->buf,
 215                                           RADEON_USAGE_READWRITE))) {
 216                 sctx->b.dma_clear_buffer(ctx, dst, offset, size, value);
 217                 return;
 218         }
 219
 220         uint64_t va = rdst->gpu_address + offset;
 221
 222         /* Flush the caches. */
 223         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 224                          SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 225
 226         while (size) {
 227                 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
 228                 unsigned dma_flags = tc_l2_flag  | CP_DMA_CLEAR;
 229
 230                 si_cp_dma_prepare(sctx, dst, NULL, byte_count, size,
 231                                   &is_first, &dma_flags);
 232
 233                 /* Emit the clear packet. */
 234                 si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, coher);
 235
 236                 size -= byte_count;
 237                 va += byte_count;
 238         }
 239
 240         if (tc_l2_flag)
 241                 rdst->TC_L2_dirty = true;
 242
 243         /* If it's not a framebuffer fast clear... */
 244         if (coher == R600_COHERENCY_SHADER)
 245                 sctx->b.num_cp_dma_calls++;
 246 }
 247
 248 /**
 249  * Realign the CP DMA engine. This must be done after a copy with an unaligned
 250  * size.
 251  *
 252  * \param size  Remaining size to the CP DMA alignment.
 253  */
 254 static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 255                                      bool *is_first)
 256 {
 257         uint64_t va;
 258         unsigned dma_flags = 0;
 259         unsigned scratch_size = CP_DMA_ALIGNMENT * 2;
 260
 261         assert(size < CP_DMA_ALIGNMENT);
 262
 263         /* Use the scratch buffer as the dummy buffer. The 3D engine should be
 264          * idle at this point.
 265          */
 266         if (!sctx->scratch_buffer ||
 267             sctx->scratch_buffer->b.b.width0 < scratch_size) {
 268                 r600_resource_reference(&sctx->scratch_buffer, NULL);
 269                 sctx->scratch_buffer = (struct r600_resource*)
 270                         pipe_buffer_create(&sctx->screen->b.b, 0,
 271                                            PIPE_USAGE_DEFAULT, scratch_size);
 272                 if (!sctx->scratch_buffer)
 273                         return;
 274                 sctx->emit_scratch_reloc = true;
 275         }
 276
 277         si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
 278                           &sctx->scratch_buffer->b.b, size, size,
 279                           is_first, &dma_flags);
 280
 281         va = sctx->scratch_buffer->gpu_address;
 282         si_emit_cp_dma(sctx, va, va + CP_DMA_ALIGNMENT, size, dma_flags,
 283                        R600_COHERENCY_SHADER);
 284 }
 285
 286 void si_copy_buffer(struct si_context *sctx,
 287                     struct pipe_resource *dst, struct pipe_resource *src,
 288                     uint64_t dst_offset, uint64_t src_offset, unsigned size)
 289 {
 290         uint64_t main_dst_offset, main_src_offset;
 291         unsigned skipped_size = 0;
 292         unsigned realign_size = 0;
 293         unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER);
 294         unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER);
 295         bool is_first = true;
 296
 297         if (!size)
 298                 return;
 299
 300         /* Mark the buffer range of destination as valid (initialized),
 301          * so that transfer_map knows it should wait for the GPU when mapping
 302          * that range. */
 303         util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
 304                        dst_offset + size);
 305
 306         dst_offset += r600_resource(dst)->gpu_address;
 307         src_offset += r600_resource(src)->gpu_address;
 308
 309         /* The workarounds aren't needed on Fiji and beyond. */
 310         if (sctx->b.family <= CHIP_CARRIZO ||
 311             sctx->b.family == CHIP_STONEY) {
 312                 /* If the size is not aligned, we must add a dummy copy at the end
 313                  * just to align the internal counter. Otherwise, the DMA engine
 314                  * would slow down by an order of magnitude for following copies.
 315                  */
 316                 if (size % CP_DMA_ALIGNMENT)
 317                         realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
 318
 319                 /* If the copy begins unaligned, we must start copying from the next
 320                  * aligned block and the skipped part should be copied after everything
 321                  * else has been copied. Only the src alignment matters, not dst.
 322                  */
 323                 if (src_offset % CP_DMA_ALIGNMENT) {
 324                         skipped_size = CP_DMA_ALIGNMENT - (src_offset % CP_DMA_ALIGNMENT);
 325                         /* The main part will be skipped if the size is too small. */
 326                         skipped_size = MIN2(skipped_size, size);
 327                         size -= skipped_size;
 328                 }
 329         }
 330
 331         /* Flush the caches. */
 332         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 333                          SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 334
 335         /* This is the main part doing the copying. Src is always aligned. */
 336         main_dst_offset = dst_offset + skipped_size;
 337         main_src_offset = src_offset + skipped_size;
 338
 339         while (size) {
 340                 unsigned dma_flags = tc_l2_flag;
 341                 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
 342
 343                 si_cp_dma_prepare(sctx, dst, src, byte_count,
 344                                   size + skipped_size + realign_size,
 345                                   &is_first, &dma_flags);
 346
 347                 si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
 348                                byte_count, dma_flags, R600_COHERENCY_SHADER);
 349
 350                 size -= byte_count;
 351                 main_src_offset += byte_count;
 352                 main_dst_offset += byte_count;
 353         }
 354
 355         /* Copy the part we skipped because src wasn't aligned. */
 356         if (skipped_size) {
 357                 unsigned dma_flags = tc_l2_flag;
 358
 359                 si_cp_dma_prepare(sctx, dst, src, skipped_size,
 360                                   skipped_size + realign_size,
 361                                   &is_first, &dma_flags);
 362
 363                 si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
 364                                dma_flags, R600_COHERENCY_SHADER);
 365         }
 366
 367         /* Finally, realign the engine if the size wasn't aligned. */
 368         if (realign_size)
 369                 si_cp_dma_realign_engine(sctx, realign_size,
 370                                          &is_first);
 371
 372         if (tc_l2_flag)
 373                 r600_resource(dst)->TC_L2_dirty = true;
 374
 375         /* If it's not a prefetch... */
 376         if (dst_offset != src_offset)
 377                 sctx->b.num_cp_dma_calls++;
 378 }
 379
 380 void si_init_cp_dma_functions(struct si_context *sctx)
 381 {
 382         sctx->b.clear_buffer = si_clear_buffer;
 383 }