src/gallium/drivers/radeonsi/si_cp_dma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák <maraeo@gmail.com>
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "sid.h"
  29 #include "radeon/r600_cs.h"
  30
  31
  32 /* Set this if you want the 3D engine to wait until CP DMA is done.
  33  * It should be set on the last CP DMA packet. */
  34 #define R600_CP_DMA_SYNC        (1 << 0) /* R600+ */
  35
  36 /* Set this if the source data was used as a destination in a previous CP DMA
  37  * packet. It's for preventing a read-after-write (RAW) hazard between two
  38  * CP DMA packets. */
  39 #define SI_CP_DMA_RAW_WAIT      (1 << 1) /* SI+ */
  40 #define CIK_CP_DMA_USE_L2       (1 << 2)
  41
  42 /* Emit a CP DMA packet to do a copy from one buffer to another.
  43  * The size must fit in bits [20:0].
  44  */
  45 static void si_emit_cp_dma_copy_buffer(struct si_context *sctx,
  46                                        uint64_t dst_va, uint64_t src_va,
  47                                        unsigned size, unsigned flags)
  48 {
  49         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  50         uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
  51         uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
  52         uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
  53         uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
  54                            S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
  55                            S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
  56
  57         assert(size);
  58         assert((size & ((1<<21)-1)) == size);
  59
  60         if (sctx->b.chip_class >= CIK) {
  61                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
  62                 radeon_emit(cs, sync_flag | sel);       /* CP_SYNC [31] */
  63                 radeon_emit(cs, src_va);                /* SRC_ADDR_LO [31:0] */
  64                 radeon_emit(cs, src_va >> 32);          /* SRC_ADDR_HI [31:0] */
  65                 radeon_emit(cs, dst_va);                /* DST_ADDR_LO [31:0] */
  66                 radeon_emit(cs, dst_va >> 32);          /* DST_ADDR_HI [31:0] */
  67                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
  68         } else {
  69                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
  70                 radeon_emit(cs, src_va);                        /* SRC_ADDR_LO [31:0] */
  71                 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
  72                 radeon_emit(cs, dst_va);                        /* DST_ADDR_LO [31:0] */
  73                 radeon_emit(cs, (dst_va >> 32) & 0xffff);       /* DST_ADDR_HI [15:0] */
  74                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
  75         }
  76 }
  77
  78 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
  79 static void si_emit_cp_dma_clear_buffer(struct si_context *sctx,
  80                                         uint64_t dst_va, unsigned size,
  81                                         uint32_t clear_value, unsigned flags)
  82 {
  83         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  84         uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
  85         uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
  86         uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
  87         uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
  88
  89         assert(size);
  90         assert((size & ((1<<21)-1)) == size);
  91
  92         if (sctx->b.chip_class >= CIK) {
  93                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
  94                 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
  95                 radeon_emit(cs, clear_value);           /* DATA [31:0] */
  96                 radeon_emit(cs, 0);
  97                 radeon_emit(cs, dst_va);                /* DST_ADDR_LO [31:0] */
  98                 radeon_emit(cs, dst_va >> 32);          /* DST_ADDR_HI [15:0] */
  99                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
 100         } else {
 101                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 102                 radeon_emit(cs, clear_value);           /* DATA [31:0] */
 103                 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
 104                 radeon_emit(cs, dst_va);                        /* DST_ADDR_LO [31:0] */
 105                 radeon_emit(cs, (dst_va >> 32) & 0xffff);       /* DST_ADDR_HI [15:0] */
 106                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
 107         }
 108 }
 109
 110 static unsigned get_flush_flags(struct si_context *sctx, bool is_framebuffer)
 111 {
 112         if (is_framebuffer)
 113                 return SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
 114
 115         return SI_CONTEXT_INV_SMEM_L1 |
 116                SI_CONTEXT_INV_VMEM_L1 |
 117                (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 118 }
 119
 120 static unsigned get_tc_l2_flag(struct si_context *sctx, bool is_framebuffer)
 121 {
 122         return is_framebuffer || sctx->b.chip_class == SI ? 0 : CIK_CP_DMA_USE_L2;
 123 }
 124
 125 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 126                               struct pipe_resource *src, unsigned byte_count,
 127                               uint64_t remaining_size, unsigned *flags)
 128 {
 129         si_need_cs_space(sctx);
 130
 131         /* This must be done after need_cs_space. */
 132         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 133                                   (struct r600_resource*)dst,
 134                                   RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 135         if (src)
 136                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 137                                           (struct r600_resource*)src,
 138                                           RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 139
 140         /* Flush the caches for the first copy only.
 141          * Also wait for the previous CP DMA operations.
 142          */
 143         if (sctx->b.flags) {
 144                 si_emit_cache_flush(sctx, NULL);
 145                 *flags |= SI_CP_DMA_RAW_WAIT;
 146         }
 147
 148         /* Do the synchronization after the last dma, so that all data
 149          * is written to memory.
 150          */
 151         if (byte_count == remaining_size)
 152                 *flags |= R600_CP_DMA_SYNC;
 153 }
 154
 155 /* Alignment for optimal performance. */
 156 #define CP_DMA_ALIGNMENT        32
 157 /* The max number of bytes to copy per packet. */
 158 #define CP_DMA_MAX_BYTE_COUNT   ((1 << 21) - CP_DMA_ALIGNMENT)
 159
 160 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 161                             uint64_t offset, uint64_t size, unsigned value,
 162                             bool is_framebuffer)
 163 {
 164         struct si_context *sctx = (struct si_context*)ctx;
 165         unsigned tc_l2_flag = get_tc_l2_flag(sctx, is_framebuffer);
 166         unsigned flush_flags = get_flush_flags(sctx, is_framebuffer);
 167
 168         if (!size)
 169                 return;
 170
 171         /* Mark the buffer range of destination as valid (initialized),
 172          * so that transfer_map knows it should wait for the GPU when mapping
 173          * that range. */
 174         util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
 175                        offset + size);
 176
 177         /* Fallback for unaligned clears. */
 178         if (offset % 4 != 0 || size % 4 != 0) {
 179                 uint8_t *map = sctx->b.ws->buffer_map(r600_resource(dst)->buf,
 180                                                       sctx->b.gfx.cs,
 181                                                       PIPE_TRANSFER_WRITE);
 182                 map += offset;
 183                 for (uint64_t i = 0; i < size; i++) {
 184                         unsigned byte_within_dword = (offset + i) % 4;
 185                         *map++ = (value >> (byte_within_dword * 8)) & 0xff;
 186                 }
 187                 return;
 188         }
 189
 190         uint64_t va = r600_resource(dst)->gpu_address + offset;
 191
 192         /* Flush the caches. */
 193         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 194                          SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 195
 196         while (size) {
 197                 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
 198                 unsigned dma_flags = tc_l2_flag;
 199
 200                 si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, &dma_flags);
 201
 202                 /* Emit the clear packet. */
 203                 si_emit_cp_dma_clear_buffer(sctx, va, byte_count, value, dma_flags);
 204
 205                 size -= byte_count;
 206                 va += byte_count;
 207         }
 208
 209         /* Flush the caches again in case the 3D engine has been prefetching
 210          * the resource. */
 211         sctx->b.flags |= flush_flags;
 212
 213         if (tc_l2_flag)
 214                 r600_resource(dst)->TC_L2_dirty = true;
 215 }
 216
 217 /**
 218  * Realign the CP DMA engine. This must be done after a copy with an unaligned
 219  * size.
 220  *
 221  * \param size  Remaining size to the CP DMA alignment.
 222  */
 223 static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size)
 224 {
 225         uint64_t va;
 226         unsigned dma_flags = 0;
 227         unsigned scratch_size = CP_DMA_ALIGNMENT * 2;
 228
 229         assert(size < CP_DMA_ALIGNMENT);
 230
 231         /* Use the scratch buffer as the dummy buffer. The 3D engine should be
 232          * idle at this point.
 233          */
 234         if (!sctx->scratch_buffer ||
 235             sctx->scratch_buffer->b.b.width0 < scratch_size) {
 236                 r600_resource_reference(&sctx->scratch_buffer, NULL);
 237                 sctx->scratch_buffer =
 238                         si_resource_create_custom(&sctx->screen->b.b,
 239                                                   PIPE_USAGE_DEFAULT,
 240                                                   scratch_size);
 241                 if (!sctx->scratch_buffer)
 242                         return;
 243                 sctx->emit_scratch_reloc = true;
 244         }
 245
 246         si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
 247                           &sctx->scratch_buffer->b.b, size, size, &dma_flags);
 248
 249         va = sctx->scratch_buffer->gpu_address;
 250         si_emit_cp_dma_copy_buffer(sctx, va, va + CP_DMA_ALIGNMENT, size,
 251                                    dma_flags);
 252 }
 253
 254 void si_copy_buffer(struct si_context *sctx,
 255                     struct pipe_resource *dst, struct pipe_resource *src,
 256                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 257                     bool is_framebuffer)
 258 {
 259         uint64_t main_dst_offset, main_src_offset;
 260         unsigned skipped_size = 0;
 261         unsigned realign_size = 0;
 262         unsigned tc_l2_flag = get_tc_l2_flag(sctx, is_framebuffer);
 263         unsigned flush_flags = get_flush_flags(sctx, is_framebuffer);
 264
 265         if (!size)
 266                 return;
 267
 268         /* Mark the buffer range of destination as valid (initialized),
 269          * so that transfer_map knows it should wait for the GPU when mapping
 270          * that range. */
 271         util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
 272                        dst_offset + size);
 273
 274         dst_offset += r600_resource(dst)->gpu_address;
 275         src_offset += r600_resource(src)->gpu_address;
 276
 277         /* The workarounds aren't needed on Fiji and beyond. */
 278         if (sctx->b.family <= CHIP_CARRIZO ||
 279             sctx->b.family == CHIP_STONEY) {
 280                 /* If the size is not aligned, we must add a dummy copy at the end
 281                  * just to align the internal counter. Otherwise, the DMA engine
 282                  * would slow down by an order of magnitude for following copies.
 283                  */
 284                 if (size % CP_DMA_ALIGNMENT)
 285                         realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
 286
 287                 /* If the copy begins unaligned, we must start copying from the next
 288                  * aligned block and the skipped part should be copied after everything
 289                  * else has been copied. Only the src alignment matters, not dst.
 290                  */
 291                 if (src_offset % CP_DMA_ALIGNMENT) {
 292                         skipped_size = CP_DMA_ALIGNMENT - (src_offset % CP_DMA_ALIGNMENT);
 293                         /* The main part will be skipped if the size is too small. */
 294                         skipped_size = MIN2(skipped_size, size);
 295                         size -= skipped_size;
 296                 }
 297         }
 298
 299         /* Flush the caches. */
 300         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 301                          SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 302
 303         /* This is the main part doing the copying. Src is always aligned. */
 304         main_dst_offset = dst_offset + skipped_size;
 305         main_src_offset = src_offset + skipped_size;
 306
 307         while (size) {
 308                 unsigned dma_flags = tc_l2_flag;
 309                 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
 310
 311                 si_cp_dma_prepare(sctx, dst, src, byte_count,
 312                                   size + skipped_size + realign_size,
 313                                   &dma_flags);
 314
 315                 si_emit_cp_dma_copy_buffer(sctx, main_dst_offset, main_src_offset,
 316                                            byte_count, dma_flags);
 317
 318                 size -= byte_count;
 319                 main_src_offset += byte_count;
 320                 main_dst_offset += byte_count;
 321         }
 322
 323         /* Copy the part we skipped because src wasn't aligned. */
 324         if (skipped_size) {
 325                 unsigned dma_flags = tc_l2_flag;
 326
 327                 si_cp_dma_prepare(sctx, dst, src, skipped_size,
 328                                   skipped_size + realign_size,
 329                                   &dma_flags);
 330
 331                 si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset,
 332                                            skipped_size, dma_flags);
 333         }
 334
 335         /* Finally, realign the engine if the size wasn't aligned. */
 336         if (realign_size)
 337                 si_cp_dma_realign_engine(sctx, realign_size);
 338
 339         /* Flush the caches again in case the 3D engine has been prefetching
 340          * the resource. */
 341         sctx->b.flags |= flush_flags;
 342
 343         if (tc_l2_flag)
 344                 r600_resource(dst)->TC_L2_dirty = true;
 345 }
 346
 347 void si_init_cp_dma_functions(struct si_context *sctx)
 348 {
 349         sctx->b.clear_buffer = si_clear_buffer;
 350 }