src/gallium/drivers/radeonsi/si_cp_dma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák <maraeo@gmail.com>
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "sid.h"
  29 #include "radeon/r600_cs.h"
  30
  31
  32 /* Set this if you want the 3D engine to wait until CP DMA is done.
  33  * It should be set on the last CP DMA packet. */
  34 #define R600_CP_DMA_SYNC        (1 << 0) /* R600+ */
  35
  36 /* Set this if the source data was used as a destination in a previous CP DMA
  37  * packet. It's for preventing a read-after-write (RAW) hazard between two
  38  * CP DMA packets. */
  39 #define SI_CP_DMA_RAW_WAIT      (1 << 1) /* SI+ */
  40 #define CIK_CP_DMA_USE_L2       (1 << 2)
  41
  42 /* Emit a CP DMA packet to do a copy from one buffer to another.
  43  * The size must fit in bits [20:0].
  44  */
  45 static void si_emit_cp_dma_copy_buffer(struct si_context *sctx,
  46                                        uint64_t dst_va, uint64_t src_va,
  47                                        unsigned size, unsigned flags)
  48 {
  49         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  50         uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
  51         uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
  52         uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
  53         uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
  54                            S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
  55                            S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
  56
  57         assert(size);
  58         assert((size & ((1<<21)-1)) == size);
  59
  60         if (sctx->b.chip_class >= CIK) {
  61                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
  62                 radeon_emit(cs, sync_flag | sel);       /* CP_SYNC [31] */
  63                 radeon_emit(cs, src_va);                /* SRC_ADDR_LO [31:0] */
  64                 radeon_emit(cs, src_va >> 32);          /* SRC_ADDR_HI [31:0] */
  65                 radeon_emit(cs, dst_va);                /* DST_ADDR_LO [31:0] */
  66                 radeon_emit(cs, dst_va >> 32);          /* DST_ADDR_HI [31:0] */
  67                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
  68         } else {
  69                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
  70                 radeon_emit(cs, src_va);                        /* SRC_ADDR_LO [31:0] */
  71                 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
  72                 radeon_emit(cs, dst_va);                        /* DST_ADDR_LO [31:0] */
  73                 radeon_emit(cs, (dst_va >> 32) & 0xffff);       /* DST_ADDR_HI [15:0] */
  74                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
  75         }
  76
  77         /* CP DMA is executed in ME, but index buffers are read by PFP.
  78          * This ensures that ME (CP DMA) is idle before PFP starts fetching
  79          * indices. If we wanted to execute CP DMA in PFP, this packet
  80          * should precede it.
  81          */
  82         if (sync_flag) {
  83                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
  84                 radeon_emit(cs, 0);
  85         }
  86 }
  87
  88 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
  89 static void si_emit_cp_dma_clear_buffer(struct si_context *sctx,
  90                                         uint64_t dst_va, unsigned size,
  91                                         uint32_t clear_value, unsigned flags,
  92                                         enum r600_coherency coher)
  93 {
  94         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
  95         uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
  96         uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
  97         uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
  98         uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
  99
 100         assert(size);
 101         assert((size & ((1<<21)-1)) == size);
 102
 103         if (sctx->b.chip_class >= CIK) {
 104                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
 105                 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
 106                 radeon_emit(cs, clear_value);           /* DATA [31:0] */
 107                 radeon_emit(cs, 0);
 108                 radeon_emit(cs, dst_va);                /* DST_ADDR_LO [31:0] */
 109                 radeon_emit(cs, dst_va >> 32);          /* DST_ADDR_HI [15:0] */
 110                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
 111         } else {
 112                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 113                 radeon_emit(cs, clear_value);           /* DATA [31:0] */
 114                 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
 115                 radeon_emit(cs, dst_va);                        /* DST_ADDR_LO [31:0] */
 116                 radeon_emit(cs, (dst_va >> 32) & 0xffff);       /* DST_ADDR_HI [15:0] */
 117                 radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND [29:22] | BYTE_COUNT [20:0] */
 118         }
 119
 120         /* See "copy_buffer" for explanation. */
 121         if (coher == R600_COHERENCY_SHADER && sync_flag) {
 122                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 123                 radeon_emit(cs, 0);
 124         }
 125 }
 126
 127 static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher)
 128 {
 129         switch (coher) {
 130         default:
 131         case R600_COHERENCY_NONE:
 132                 return 0;
 133         case R600_COHERENCY_SHADER:
 134                 return SI_CONTEXT_INV_SMEM_L1 |
 135                        SI_CONTEXT_INV_VMEM_L1 |
 136                        (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 137         case R600_COHERENCY_CB_META:
 138                 return SI_CONTEXT_FLUSH_AND_INV_CB |
 139                        SI_CONTEXT_FLUSH_AND_INV_CB_META;
 140         }
 141 }
 142
 143 static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher)
 144 {
 145         return coher == R600_COHERENCY_SHADER &&
 146                sctx->b.chip_class >= CIK ? CIK_CP_DMA_USE_L2 : 0;
 147 }
 148
 149 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 150                               struct pipe_resource *src, unsigned byte_count,
 151                               uint64_t remaining_size, unsigned *flags)
 152 {
 153         si_need_cs_space(sctx);
 154
 155         /* This must be done after need_cs_space. */
 156         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 157                                   (struct r600_resource*)dst,
 158                                   RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 159         if (src)
 160                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 161                                           (struct r600_resource*)src,
 162                                           RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 163
 164         /* Flush the caches for the first copy only.
 165          * Also wait for the previous CP DMA operations.
 166          */
 167         if (sctx->b.flags) {
 168                 si_emit_cache_flush(sctx, NULL);
 169                 *flags |= SI_CP_DMA_RAW_WAIT;
 170         }
 171
 172         /* Do the synchronization after the last dma, so that all data
 173          * is written to memory.
 174          */
 175         if (byte_count == remaining_size)
 176                 *flags |= R600_CP_DMA_SYNC;
 177 }
 178
 179 /* Alignment for optimal performance. */
 180 #define CP_DMA_ALIGNMENT        32
 181 /* The max number of bytes to copy per packet. */
 182 #define CP_DMA_MAX_BYTE_COUNT   ((1 << 21) - CP_DMA_ALIGNMENT)
 183
 184 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 185                             uint64_t offset, uint64_t size, unsigned value,
 186                             enum r600_coherency coher)
 187 {
 188         struct si_context *sctx = (struct si_context*)ctx;
 189         unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
 190         unsigned flush_flags = get_flush_flags(sctx, coher);
 191
 192         if (!size)
 193                 return;
 194
 195         /* Mark the buffer range of destination as valid (initialized),
 196          * so that transfer_map knows it should wait for the GPU when mapping
 197          * that range. */
 198         util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
 199                        offset + size);
 200
 201         /* Fallback for unaligned clears. */
 202         if (offset % 4 != 0 || size % 4 != 0) {
 203                 uint8_t *map = sctx->b.ws->buffer_map(r600_resource(dst)->buf,
 204                                                       sctx->b.gfx.cs,
 205                                                       PIPE_TRANSFER_WRITE);
 206                 map += offset;
 207                 for (uint64_t i = 0; i < size; i++) {
 208                         unsigned byte_within_dword = (offset + i) % 4;
 209                         *map++ = (value >> (byte_within_dword * 8)) & 0xff;
 210                 }
 211                 return;
 212         }
 213
 214         uint64_t va = r600_resource(dst)->gpu_address + offset;
 215
 216         /* Flush the caches. */
 217         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 218                          SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 219
 220         while (size) {
 221                 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
 222                 unsigned dma_flags = tc_l2_flag;
 223
 224                 si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, &dma_flags);
 225
 226                 /* Emit the clear packet. */
 227                 si_emit_cp_dma_clear_buffer(sctx, va, byte_count, value,
 228                                             dma_flags, coher);
 229
 230                 size -= byte_count;
 231                 va += byte_count;
 232         }
 233
 234         if (tc_l2_flag)
 235                 r600_resource(dst)->TC_L2_dirty = true;
 236 }
 237
 238 /**
 239  * Realign the CP DMA engine. This must be done after a copy with an unaligned
 240  * size.
 241  *
 242  * \param size  Remaining size to the CP DMA alignment.
 243  */
 244 static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size)
 245 {
 246         uint64_t va;
 247         unsigned dma_flags = 0;
 248         unsigned scratch_size = CP_DMA_ALIGNMENT * 2;
 249
 250         assert(size < CP_DMA_ALIGNMENT);
 251
 252         /* Use the scratch buffer as the dummy buffer. The 3D engine should be
 253          * idle at this point.
 254          */
 255         if (!sctx->scratch_buffer ||
 256             sctx->scratch_buffer->b.b.width0 < scratch_size) {
 257                 r600_resource_reference(&sctx->scratch_buffer, NULL);
 258                 sctx->scratch_buffer =
 259                         si_resource_create_custom(&sctx->screen->b.b,
 260                                                   PIPE_USAGE_DEFAULT,
 261                                                   scratch_size);
 262                 if (!sctx->scratch_buffer)
 263                         return;
 264                 sctx->emit_scratch_reloc = true;
 265         }
 266
 267         si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
 268                           &sctx->scratch_buffer->b.b, size, size, &dma_flags);
 269
 270         va = sctx->scratch_buffer->gpu_address;
 271         si_emit_cp_dma_copy_buffer(sctx, va, va + CP_DMA_ALIGNMENT, size,
 272                                    dma_flags);
 273 }
 274
 275 void si_copy_buffer(struct si_context *sctx,
 276                     struct pipe_resource *dst, struct pipe_resource *src,
 277                     uint64_t dst_offset, uint64_t src_offset, unsigned size)
 278 {
 279         uint64_t main_dst_offset, main_src_offset;
 280         unsigned skipped_size = 0;
 281         unsigned realign_size = 0;
 282         unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER);
 283         unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER);
 284
 285         if (!size)
 286                 return;
 287
 288         /* Mark the buffer range of destination as valid (initialized),
 289          * so that transfer_map knows it should wait for the GPU when mapping
 290          * that range. */
 291         util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
 292                        dst_offset + size);
 293
 294         dst_offset += r600_resource(dst)->gpu_address;
 295         src_offset += r600_resource(src)->gpu_address;
 296
 297         /* The workarounds aren't needed on Fiji and beyond. */
 298         if (sctx->b.family <= CHIP_CARRIZO ||
 299             sctx->b.family == CHIP_STONEY) {
 300                 /* If the size is not aligned, we must add a dummy copy at the end
 301                  * just to align the internal counter. Otherwise, the DMA engine
 302                  * would slow down by an order of magnitude for following copies.
 303                  */
 304                 if (size % CP_DMA_ALIGNMENT)
 305                         realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
 306
 307                 /* If the copy begins unaligned, we must start copying from the next
 308                  * aligned block and the skipped part should be copied after everything
 309                  * else has been copied. Only the src alignment matters, not dst.
 310                  */
 311                 if (src_offset % CP_DMA_ALIGNMENT) {
 312                         skipped_size = CP_DMA_ALIGNMENT - (src_offset % CP_DMA_ALIGNMENT);
 313                         /* The main part will be skipped if the size is too small. */
 314                         skipped_size = MIN2(skipped_size, size);
 315                         size -= skipped_size;
 316                 }
 317         }
 318
 319         /* Flush the caches. */
 320         sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 321                          SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 322
 323         /* This is the main part doing the copying. Src is always aligned. */
 324         main_dst_offset = dst_offset + skipped_size;
 325         main_src_offset = src_offset + skipped_size;
 326
 327         while (size) {
 328                 unsigned dma_flags = tc_l2_flag;
 329                 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
 330
 331                 si_cp_dma_prepare(sctx, dst, src, byte_count,
 332                                   size + skipped_size + realign_size,
 333                                   &dma_flags);
 334
 335                 si_emit_cp_dma_copy_buffer(sctx, main_dst_offset, main_src_offset,
 336                                            byte_count, dma_flags);
 337
 338                 size -= byte_count;
 339                 main_src_offset += byte_count;
 340                 main_dst_offset += byte_count;
 341         }
 342
 343         /* Copy the part we skipped because src wasn't aligned. */
 344         if (skipped_size) {
 345                 unsigned dma_flags = tc_l2_flag;
 346
 347                 si_cp_dma_prepare(sctx, dst, src, skipped_size,
 348                                   skipped_size + realign_size,
 349                                   &dma_flags);
 350
 351                 si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset,
 352                                            skipped_size, dma_flags);
 353         }
 354
 355         /* Finally, realign the engine if the size wasn't aligned. */
 356         if (realign_size)
 357                 si_cp_dma_realign_engine(sctx, realign_size);
 358
 359         if (tc_l2_flag)
 360                 r600_resource(dst)->TC_L2_dirty = true;
 361 }
 362
 363 void si_init_cp_dma_functions(struct si_context *sctx)
 364 {
 365         sctx->b.clear_buffer = si_clear_buffer;
 366 }