2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <maraeo@gmail.com>
29 #include "radeon/r600_cs.h"
31 /* The max number of bytes to copy per packet. */
32 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - SI_CPDMA_ALIGNMENT)
34 /* Set this if you want the ME to wait until CP DMA is done.
35 * It should be set on the last CP DMA packet. */
36 #define CP_DMA_SYNC (1 << 0)
38 /* Set this if the source data was used as a destination in a previous CP DMA
39 * packet. It's for preventing a read-after-write (RAW) hazard between two
41 #define CP_DMA_RAW_WAIT (1 << 1)
42 #define CP_DMA_USE_L2 (1 << 2) /* CIK+ */
43 #define CP_DMA_CLEAR (1 << 3)
45 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
46 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
49 static void si_emit_cp_dma(struct si_context
*sctx
, uint64_t dst_va
,
50 uint64_t src_va
, unsigned size
, unsigned flags
,
51 enum r600_coherency coher
)
53 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
54 uint32_t header
= 0, command
= S_414_BYTE_COUNT_GFX6(size
);
57 assert(size
<= CP_DMA_MAX_BYTE_COUNT
);
60 if (flags
& CP_DMA_SYNC
)
61 header
|= S_411_CP_SYNC(1);
63 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
65 if (flags
& CP_DMA_RAW_WAIT
)
66 command
|= S_414_RAW_WAIT(1);
68 /* Src and dst flags. */
69 if (flags
& CP_DMA_USE_L2
)
70 header
|= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2
);
72 if (flags
& CP_DMA_CLEAR
)
73 header
|= S_411_SRC_SEL(V_411_DATA
);
74 else if (flags
& CP_DMA_USE_L2
)
75 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
77 if (sctx
->b
.chip_class
>= CIK
) {
78 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
79 radeon_emit(cs
, header
);
80 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
81 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
82 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
83 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
84 radeon_emit(cs
, command
);
86 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
88 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
89 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
90 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
91 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
92 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
93 radeon_emit(cs
, command
);
96 /* CP DMA is executed in ME, but index buffers are read by PFP.
97 * This ensures that ME (CP DMA) is idle before PFP starts fetching
98 * indices. If we wanted to execute CP DMA in PFP, this packet
101 if (coher
== R600_COHERENCY_SHADER
&& flags
& CP_DMA_SYNC
) {
102 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
107 static unsigned get_flush_flags(struct si_context
*sctx
, enum r600_coherency coher
)
111 case R600_COHERENCY_NONE
:
113 case R600_COHERENCY_SHADER
:
114 return SI_CONTEXT_INV_SMEM_L1
|
115 SI_CONTEXT_INV_VMEM_L1
|
116 (sctx
->b
.chip_class
== SI
? SI_CONTEXT_INV_GLOBAL_L2
: 0);
117 case R600_COHERENCY_CB_META
:
118 return SI_CONTEXT_FLUSH_AND_INV_CB
;
122 static unsigned get_tc_l2_flag(struct si_context
*sctx
, enum r600_coherency coher
)
124 return coher
== R600_COHERENCY_SHADER
&&
125 sctx
->b
.chip_class
>= CIK
? CP_DMA_USE_L2
: 0;
128 static void si_cp_dma_prepare(struct si_context
*sctx
, struct pipe_resource
*dst
,
129 struct pipe_resource
*src
, unsigned byte_count
,
130 uint64_t remaining_size
, unsigned user_flags
,
131 bool *is_first
, unsigned *packet_flags
)
133 /* Fast exit for a CPDMA prefetch. */
134 if ((user_flags
& SI_CPDMA_SKIP_ALL
) == SI_CPDMA_SKIP_ALL
) {
139 if (!(user_flags
& SI_CPDMA_SKIP_BO_LIST_UPDATE
)) {
140 /* Count memory usage in so that need_cs_space can take it into account. */
141 r600_context_add_resource_size(&sctx
->b
.b
, dst
);
143 r600_context_add_resource_size(&sctx
->b
.b
, src
);
146 if (!(user_flags
& SI_CPDMA_SKIP_CHECK_CS_SPACE
))
147 si_need_cs_space(sctx
);
149 /* This must be done after need_cs_space. */
150 if (!(user_flags
& SI_CPDMA_SKIP_BO_LIST_UPDATE
)) {
151 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
152 (struct r600_resource
*)dst
,
153 RADEON_USAGE_WRITE
, RADEON_PRIO_CP_DMA
);
155 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
156 (struct r600_resource
*)src
,
157 RADEON_USAGE_READ
, RADEON_PRIO_CP_DMA
);
160 /* Flush the caches for the first copy only.
161 * Also wait for the previous CP DMA operations.
163 if (!(user_flags
& SI_CPDMA_SKIP_GFX_SYNC
) && sctx
->b
.flags
)
164 si_emit_cache_flush(sctx
);
166 if (!(user_flags
& SI_CPDMA_SKIP_SYNC_BEFORE
) && *is_first
)
167 *packet_flags
|= CP_DMA_RAW_WAIT
;
171 /* Do the synchronization after the last dma, so that all data
172 * is written to memory.
174 if (!(user_flags
& SI_CPDMA_SKIP_SYNC_AFTER
) &&
175 byte_count
== remaining_size
)
176 *packet_flags
|= CP_DMA_SYNC
;
179 static void si_clear_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
180 uint64_t offset
, uint64_t size
, unsigned value
,
181 enum r600_coherency coher
)
183 struct si_context
*sctx
= (struct si_context
*)ctx
;
184 struct radeon_winsys
*ws
= sctx
->b
.ws
;
185 struct r600_resource
*rdst
= r600_resource(dst
);
186 unsigned tc_l2_flag
= get_tc_l2_flag(sctx
, coher
);
187 unsigned flush_flags
= get_flush_flags(sctx
, coher
);
188 uint64_t dma_clear_size
;
189 bool is_first
= true;
194 dma_clear_size
= size
& ~3llu;
196 /* Mark the buffer range of destination as valid (initialized),
197 * so that transfer_map knows it should wait for the GPU when mapping
199 util_range_add(&rdst
->valid_buffer_range
, offset
,
200 offset
+ dma_clear_size
);
202 /* dma_clear_buffer can use clear_buffer on failure. Make sure that
203 * doesn't happen. We don't want an infinite recursion: */
204 if (sctx
->b
.dma
.cs
&&
206 /* CP DMA is very slow. Always use SDMA for big clears. This
207 * alone improves DeusEx:MD performance by 70%. */
208 (size
> 128 * 1024 ||
209 /* Buffers not used by the GFX IB yet will be cleared by SDMA.
210 * This happens to move most buffer clears to SDMA, including
211 * DCC and CMASK clears, because pipe->clear clears them before
212 * si_emit_framebuffer_state (in a draw call) adds them.
213 * For example, DeusEx:MD has 21 buffer clears per frame and all
214 * of them are moved to SDMA thanks to this. */
215 !ws
->cs_is_buffer_referenced(sctx
->b
.gfx
.cs
, rdst
->buf
,
216 RADEON_USAGE_READWRITE
))) {
217 sctx
->b
.dma_clear_buffer(ctx
, dst
, offset
, dma_clear_size
, value
);
219 offset
+= dma_clear_size
;
220 size
-= dma_clear_size
;
221 } else if (dma_clear_size
>= 4) {
222 uint64_t va
= rdst
->gpu_address
+ offset
;
224 offset
+= dma_clear_size
;
225 size
-= dma_clear_size
;
227 /* Flush the caches. */
228 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
229 SI_CONTEXT_CS_PARTIAL_FLUSH
| flush_flags
;
231 while (dma_clear_size
) {
232 unsigned byte_count
= MIN2(dma_clear_size
, CP_DMA_MAX_BYTE_COUNT
);
233 unsigned dma_flags
= tc_l2_flag
| CP_DMA_CLEAR
;
235 si_cp_dma_prepare(sctx
, dst
, NULL
, byte_count
, dma_clear_size
, 0,
236 &is_first
, &dma_flags
);
238 /* Emit the clear packet. */
239 si_emit_cp_dma(sctx
, va
, value
, byte_count
, dma_flags
, coher
);
241 dma_clear_size
-= byte_count
;
246 rdst
->TC_L2_dirty
= true;
248 /* If it's not a framebuffer fast clear... */
249 if (coher
== R600_COHERENCY_SHADER
)
250 sctx
->b
.num_cp_dma_calls
++;
254 /* Handle non-dword alignment.
256 * This function is called for embedded texture metadata clears,
257 * but those should always be properly aligned. */
258 assert(dst
->target
== PIPE_BUFFER
);
261 pipe_buffer_write(ctx
, dst
, offset
, size
, &value
);
266 * Realign the CP DMA engine. This must be done after a copy with an unaligned
269 * \param size Remaining size to the CP DMA alignment.
271 static void si_cp_dma_realign_engine(struct si_context
*sctx
, unsigned size
,
272 unsigned user_flags
, bool *is_first
)
275 unsigned dma_flags
= 0;
276 unsigned scratch_size
= SI_CPDMA_ALIGNMENT
* 2;
278 assert(size
< SI_CPDMA_ALIGNMENT
);
280 /* Use the scratch buffer as the dummy buffer. The 3D engine should be
281 * idle at this point.
283 if (!sctx
->scratch_buffer
||
284 sctx
->scratch_buffer
->b
.b
.width0
< scratch_size
) {
285 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
286 sctx
->scratch_buffer
= (struct r600_resource
*)
287 r600_aligned_buffer_create(&sctx
->screen
->b
.b
,
288 R600_RESOURCE_FLAG_UNMAPPABLE
,
291 if (!sctx
->scratch_buffer
)
294 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
297 si_cp_dma_prepare(sctx
, &sctx
->scratch_buffer
->b
.b
,
298 &sctx
->scratch_buffer
->b
.b
, size
, size
, user_flags
,
299 is_first
, &dma_flags
);
301 va
= sctx
->scratch_buffer
->gpu_address
;
302 si_emit_cp_dma(sctx
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
, dma_flags
,
303 R600_COHERENCY_SHADER
);
307 * Do memcpy between buffers using CP DMA.
309 * \param user_flags bitmask of SI_CPDMA_*
311 void si_copy_buffer(struct si_context
*sctx
,
312 struct pipe_resource
*dst
, struct pipe_resource
*src
,
313 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
316 uint64_t main_dst_offset
, main_src_offset
;
317 unsigned skipped_size
= 0;
318 unsigned realign_size
= 0;
319 unsigned tc_l2_flag
= get_tc_l2_flag(sctx
, R600_COHERENCY_SHADER
);
320 unsigned flush_flags
= get_flush_flags(sctx
, R600_COHERENCY_SHADER
);
321 bool is_first
= true;
326 if (dst
!= src
|| dst_offset
!= src_offset
) {
327 /* Mark the buffer range of destination as valid (initialized),
328 * so that transfer_map knows it should wait for the GPU when mapping
330 util_range_add(&r600_resource(dst
)->valid_buffer_range
, dst_offset
,
334 dst_offset
+= r600_resource(dst
)->gpu_address
;
335 src_offset
+= r600_resource(src
)->gpu_address
;
337 /* The workarounds aren't needed on Fiji and beyond. */
338 if (sctx
->b
.family
<= CHIP_CARRIZO
||
339 sctx
->b
.family
== CHIP_STONEY
) {
340 /* If the size is not aligned, we must add a dummy copy at the end
341 * just to align the internal counter. Otherwise, the DMA engine
342 * would slow down by an order of magnitude for following copies.
344 if (size
% SI_CPDMA_ALIGNMENT
)
345 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
347 /* If the copy begins unaligned, we must start copying from the next
348 * aligned block and the skipped part should be copied after everything
349 * else has been copied. Only the src alignment matters, not dst.
351 if (src_offset
% SI_CPDMA_ALIGNMENT
) {
352 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_offset
% SI_CPDMA_ALIGNMENT
);
353 /* The main part will be skipped if the size is too small. */
354 skipped_size
= MIN2(skipped_size
, size
);
355 size
-= skipped_size
;
359 /* Flush the caches. */
360 if (!(user_flags
& SI_CPDMA_SKIP_GFX_SYNC
))
361 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
362 SI_CONTEXT_CS_PARTIAL_FLUSH
| flush_flags
;
364 /* This is the main part doing the copying. Src is always aligned. */
365 main_dst_offset
= dst_offset
+ skipped_size
;
366 main_src_offset
= src_offset
+ skipped_size
;
369 unsigned dma_flags
= tc_l2_flag
;
370 unsigned byte_count
= MIN2(size
, CP_DMA_MAX_BYTE_COUNT
);
372 si_cp_dma_prepare(sctx
, dst
, src
, byte_count
,
373 size
+ skipped_size
+ realign_size
,
374 user_flags
, &is_first
, &dma_flags
);
376 si_emit_cp_dma(sctx
, main_dst_offset
, main_src_offset
,
377 byte_count
, dma_flags
, R600_COHERENCY_SHADER
);
380 main_src_offset
+= byte_count
;
381 main_dst_offset
+= byte_count
;
384 /* Copy the part we skipped because src wasn't aligned. */
386 unsigned dma_flags
= tc_l2_flag
;
388 si_cp_dma_prepare(sctx
, dst
, src
, skipped_size
,
389 skipped_size
+ realign_size
, user_flags
,
390 &is_first
, &dma_flags
);
392 si_emit_cp_dma(sctx
, dst_offset
, src_offset
, skipped_size
,
393 dma_flags
, R600_COHERENCY_SHADER
);
396 /* Finally, realign the engine if the size wasn't aligned. */
398 si_cp_dma_realign_engine(sctx
, realign_size
, user_flags
,
402 r600_resource(dst
)->TC_L2_dirty
= true;
404 /* If it's not a prefetch... */
405 if (dst_offset
!= src_offset
)
406 sctx
->b
.num_cp_dma_calls
++;
409 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
410 uint64_t offset
, unsigned size
)
412 assert(sctx
->b
.chip_class
>= CIK
);
414 si_copy_buffer(sctx
, buf
, buf
, offset
, offset
, size
, SI_CPDMA_SKIP_ALL
);
417 static void cik_prefetch_shader_async(struct si_context
*sctx
,
418 struct si_pm4_state
*state
)
421 struct pipe_resource
*bo
= &state
->bo
[0]->b
.b
;
422 assert(state
->nbo
== 1);
424 cik_prefetch_TC_L2_async(sctx
, bo
, 0, bo
->width0
);
428 static void cik_emit_prefetch_L2(struct si_context
*sctx
, struct r600_atom
*atom
)
430 /* Prefetch shaders and VBO descriptors to TC L2. */
431 if (si_pm4_state_changed(sctx
, ls
))
432 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.ls
);
433 if (si_pm4_state_changed(sctx
, hs
))
434 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.hs
);
435 if (si_pm4_state_changed(sctx
, es
))
436 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.es
);
437 if (si_pm4_state_changed(sctx
, gs
))
438 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
439 if (si_pm4_state_changed(sctx
, vs
))
440 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
442 /* Vertex buffer descriptors are uploaded uncached, so prefetch
443 * them right after the VS binary. */
444 if (sctx
->vertex_buffer_pointer_dirty
) {
445 cik_prefetch_TC_L2_async(sctx
, &sctx
->vertex_buffers
.buffer
->b
.b
,
446 sctx
->vertex_buffers
.buffer_offset
,
447 sctx
->vertex_elements
->desc_list_byte_size
);
449 if (si_pm4_state_changed(sctx
, ps
))
450 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.ps
);
453 void si_init_cp_dma_functions(struct si_context
*sctx
)
455 sctx
->b
.clear_buffer
= si_clear_buffer
;
457 si_init_atom(sctx
, &sctx
->prefetch_L2
, &sctx
->atoms
.s
.prefetch_L2
,
458 cik_emit_prefetch_L2
);