2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 /* Recommended maximum sizes for optimal performance.
29 * Fall back to compute or SDMA if the size is greater.
31 #define CP_DMA_COPY_PERF_THRESHOLD (64 * 1024) /* copied from Vulkan */
32 #define CP_DMA_CLEAR_PERF_THRESHOLD (32 * 1024) /* guess (clear is much slower) */
34 /* Set this if you want the ME to wait until CP DMA is done.
35 * It should be set on the last CP DMA packet. */
36 #define CP_DMA_SYNC (1 << 0)
38 /* Set this if the source data was used as a destination in a previous CP DMA
39 * packet. It's for preventing a read-after-write (RAW) hazard between two
41 #define CP_DMA_RAW_WAIT (1 << 1)
42 #define CP_DMA_USE_L2 (1 << 2) /* CIK+ */
43 #define CP_DMA_CLEAR (1 << 3)
45 /* The max number of bytes that can be copied per packet. */
46 static inline unsigned cp_dma_max_byte_count(struct si_context
*sctx
)
48 unsigned max
= sctx
->chip_class
>= GFX9
?
49 S_414_BYTE_COUNT_GFX9(~0u) :
50 S_414_BYTE_COUNT_GFX6(~0u);
52 /* make it aligned for optimal performance */
53 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
57 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
58 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
61 static void si_emit_cp_dma(struct si_context
*sctx
, uint64_t dst_va
,
62 uint64_t src_va
, unsigned size
, unsigned flags
,
63 enum si_coherency coher
)
65 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
66 uint32_t header
= 0, command
= 0;
68 assert(size
<= cp_dma_max_byte_count(sctx
));
70 if (sctx
->chip_class
>= GFX9
)
71 command
|= S_414_BYTE_COUNT_GFX9(size
);
73 command
|= S_414_BYTE_COUNT_GFX6(size
);
76 if (flags
& CP_DMA_SYNC
)
77 header
|= S_411_CP_SYNC(1);
79 if (sctx
->chip_class
>= GFX9
)
80 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
82 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
85 if (flags
& CP_DMA_RAW_WAIT
)
86 command
|= S_414_RAW_WAIT(1);
88 /* Src and dst flags. */
89 if (sctx
->chip_class
>= GFX9
&& !(flags
& CP_DMA_CLEAR
) &&
91 header
|= S_411_DSL_SEL(V_411_NOWHERE
); /* prefetch only */
92 else if (flags
& CP_DMA_USE_L2
)
93 header
|= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2
);
95 if (flags
& CP_DMA_CLEAR
)
96 header
|= S_411_SRC_SEL(V_411_DATA
);
97 else if (flags
& CP_DMA_USE_L2
)
98 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
100 if (sctx
->chip_class
>= CIK
) {
101 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
102 radeon_emit(cs
, header
);
103 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
104 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
105 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
106 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
107 radeon_emit(cs
, command
);
109 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
111 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
112 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
113 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
114 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
115 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
116 radeon_emit(cs
, command
);
119 /* CP DMA is executed in ME, but index buffers are read by PFP.
120 * This ensures that ME (CP DMA) is idle before PFP starts fetching
121 * indices. If we wanted to execute CP DMA in PFP, this packet
124 if (coher
== SI_COHERENCY_SHADER
&& flags
& CP_DMA_SYNC
) {
125 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
130 void si_cp_dma_wait_for_idle(struct si_context
*sctx
)
132 /* Issue a dummy DMA that copies zero bytes.
134 * The DMA engine will see that there's no work to do and skip this
135 * DMA request, however, the CP will see the sync flag and still wait
136 * for all DMAs to complete.
138 si_emit_cp_dma(sctx
, 0, 0, 0, CP_DMA_SYNC
, SI_COHERENCY_NONE
);
141 static unsigned get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
)
145 case SI_COHERENCY_NONE
:
147 case SI_COHERENCY_SHADER
:
148 return SI_CONTEXT_INV_SMEM_L1
|
149 SI_CONTEXT_INV_VMEM_L1
|
150 (sctx
->chip_class
== SI
? SI_CONTEXT_INV_GLOBAL_L2
: 0);
151 case SI_COHERENCY_CB_META
:
152 return SI_CONTEXT_FLUSH_AND_INV_CB
;
156 static unsigned get_tc_l2_flag(struct si_context
*sctx
, enum si_coherency coher
)
158 if ((sctx
->chip_class
>= GFX9
&& coher
== SI_COHERENCY_CB_META
) ||
159 (sctx
->chip_class
>= CIK
&& coher
== SI_COHERENCY_SHADER
))
160 return CP_DMA_USE_L2
;
165 static void si_cp_dma_prepare(struct si_context
*sctx
, struct pipe_resource
*dst
,
166 struct pipe_resource
*src
, unsigned byte_count
,
167 uint64_t remaining_size
, unsigned user_flags
,
168 bool *is_first
, unsigned *packet_flags
)
170 /* Fast exit for a CPDMA prefetch. */
171 if ((user_flags
& SI_CPDMA_SKIP_ALL
) == SI_CPDMA_SKIP_ALL
) {
176 if (!(user_flags
& SI_CPDMA_SKIP_BO_LIST_UPDATE
)) {
177 /* Count memory usage in so that need_cs_space can take it into account. */
178 si_context_add_resource_size(sctx
, dst
);
180 si_context_add_resource_size(sctx
, src
);
183 if (!(user_flags
& SI_CPDMA_SKIP_CHECK_CS_SPACE
))
184 si_need_gfx_cs_space(sctx
);
186 /* This must be done after need_cs_space. */
187 if (!(user_flags
& SI_CPDMA_SKIP_BO_LIST_UPDATE
)) {
188 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
190 RADEON_USAGE_WRITE
, RADEON_PRIO_CP_DMA
);
192 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
194 RADEON_USAGE_READ
, RADEON_PRIO_CP_DMA
);
197 /* Flush the caches for the first copy only.
198 * Also wait for the previous CP DMA operations.
200 if (!(user_flags
& SI_CPDMA_SKIP_GFX_SYNC
) && sctx
->flags
)
201 si_emit_cache_flush(sctx
);
203 if (!(user_flags
& SI_CPDMA_SKIP_SYNC_BEFORE
) && *is_first
)
204 *packet_flags
|= CP_DMA_RAW_WAIT
;
208 /* Do the synchronization after the last dma, so that all data
209 * is written to memory.
211 if (!(user_flags
& SI_CPDMA_SKIP_SYNC_AFTER
) &&
212 byte_count
== remaining_size
)
213 *packet_flags
|= CP_DMA_SYNC
;
216 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
217 uint64_t offset
, uint64_t size
, unsigned value
,
218 enum si_coherency coher
)
220 struct radeon_winsys
*ws
= sctx
->ws
;
221 struct r600_resource
*rdst
= r600_resource(dst
);
222 unsigned tc_l2_flag
= get_tc_l2_flag(sctx
, coher
);
223 unsigned flush_flags
= get_flush_flags(sctx
, coher
);
224 uint64_t dma_clear_size
;
225 bool is_first
= true;
230 dma_clear_size
= size
& ~3ull;
232 /* Mark the buffer range of destination as valid (initialized),
233 * so that transfer_map knows it should wait for the GPU when mapping
235 util_range_add(&rdst
->valid_buffer_range
, offset
,
236 offset
+ dma_clear_size
);
238 /* dma_clear_buffer can use clear_buffer on failure. Make sure that
239 * doesn't happen. We don't want an infinite recursion: */
241 !(dst
->flags
& PIPE_RESOURCE_FLAG_SPARSE
) &&
243 /* CP DMA is very slow. Always use SDMA for big clears. This
244 * alone improves DeusEx:MD performance by 70%. */
245 (size
> CP_DMA_CLEAR_PERF_THRESHOLD
||
246 /* Buffers not used by the GFX IB yet will be cleared by SDMA.
247 * This happens to move most buffer clears to SDMA, including
248 * DCC and CMASK clears, because pipe->clear clears them before
249 * si_emit_framebuffer_state (in a draw call) adds them.
250 * For example, DeusEx:MD has 21 buffer clears per frame and all
251 * of them are moved to SDMA thanks to this. */
252 !ws
->cs_is_buffer_referenced(sctx
->gfx_cs
, rdst
->buf
,
253 RADEON_USAGE_READWRITE
))) {
254 sctx
->dma_clear_buffer(sctx
, dst
, offset
, dma_clear_size
, value
);
256 offset
+= dma_clear_size
;
257 size
-= dma_clear_size
;
258 } else if (dma_clear_size
>= 4) {
259 uint64_t va
= rdst
->gpu_address
+ offset
;
261 offset
+= dma_clear_size
;
262 size
-= dma_clear_size
;
264 /* Flush the caches. */
265 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
266 SI_CONTEXT_CS_PARTIAL_FLUSH
| flush_flags
;
268 while (dma_clear_size
) {
269 unsigned byte_count
= MIN2(dma_clear_size
, cp_dma_max_byte_count(sctx
));
270 unsigned dma_flags
= tc_l2_flag
| CP_DMA_CLEAR
;
272 si_cp_dma_prepare(sctx
, dst
, NULL
, byte_count
, dma_clear_size
, 0,
273 &is_first
, &dma_flags
);
275 /* Emit the clear packet. */
276 si_emit_cp_dma(sctx
, va
, value
, byte_count
, dma_flags
, coher
);
278 dma_clear_size
-= byte_count
;
283 rdst
->TC_L2_dirty
= true;
285 /* If it's not a framebuffer fast clear... */
286 if (coher
== SI_COHERENCY_SHADER
)
287 sctx
->num_cp_dma_calls
++;
291 /* Handle non-dword alignment.
293 * This function is called for embedded texture metadata clears,
294 * but those should always be properly aligned. */
295 assert(dst
->target
== PIPE_BUFFER
);
298 pipe_buffer_write(&sctx
->b
, dst
, offset
, size
, &value
);
302 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
303 struct pipe_resource
*dst
,
304 unsigned offset
, unsigned size
,
305 const void *clear_value_ptr
,
306 int clear_value_size
)
308 struct si_context
*sctx
= (struct si_context
*)ctx
;
309 uint32_t dword_value
;
312 assert(offset
% clear_value_size
== 0);
313 assert(size
% clear_value_size
== 0);
315 if (clear_value_size
> 4) {
316 const uint32_t *u32
= clear_value_ptr
;
317 bool clear_dword_duplicated
= true;
319 /* See if we can lower large fills to dword fills. */
320 for (i
= 1; i
< clear_value_size
/ 4; i
++)
321 if (u32
[0] != u32
[i
]) {
322 clear_dword_duplicated
= false;
326 if (!clear_dword_duplicated
) {
327 /* Use transform feedback for 64-bit, 96-bit, and
330 union pipe_color_union clear_value
;
332 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
333 si_blitter_begin(sctx
, SI_DISABLE_RENDER_COND
);
334 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
335 size
, clear_value_size
/ 4,
337 si_blitter_end(sctx
);
342 /* Expand the clear value to a dword. */
343 switch (clear_value_size
) {
345 dword_value
= *(uint8_t*)clear_value_ptr
;
346 dword_value
|= (dword_value
<< 8) |
347 (dword_value
<< 16) |
351 dword_value
= *(uint16_t*)clear_value_ptr
;
352 dword_value
|= dword_value
<< 16;
355 dword_value
= *(uint32_t*)clear_value_ptr
;
358 si_clear_buffer(sctx
, dst
, offset
, size
, dword_value
,
359 SI_COHERENCY_SHADER
);
363 * Realign the CP DMA engine. This must be done after a copy with an unaligned
366 * \param size Remaining size to the CP DMA alignment.
368 static void si_cp_dma_realign_engine(struct si_context
*sctx
, unsigned size
,
369 unsigned user_flags
, bool *is_first
)
372 unsigned dma_flags
= 0;
373 unsigned scratch_size
= SI_CPDMA_ALIGNMENT
* 2;
375 assert(size
< SI_CPDMA_ALIGNMENT
);
377 /* Use the scratch buffer as the dummy buffer. The 3D engine should be
378 * idle at this point.
380 if (!sctx
->scratch_buffer
||
381 sctx
->scratch_buffer
->b
.b
.width0
< scratch_size
) {
382 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
383 sctx
->scratch_buffer
=
384 si_aligned_buffer_create(&sctx
->screen
->b
,
385 SI_RESOURCE_FLAG_UNMAPPABLE
,
388 if (!sctx
->scratch_buffer
)
391 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
394 si_cp_dma_prepare(sctx
, &sctx
->scratch_buffer
->b
.b
,
395 &sctx
->scratch_buffer
->b
.b
, size
, size
, user_flags
,
396 is_first
, &dma_flags
);
398 va
= sctx
->scratch_buffer
->gpu_address
;
399 si_emit_cp_dma(sctx
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
, dma_flags
,
400 SI_COHERENCY_SHADER
);
404 * Do memcpy between buffers using CP DMA.
406 * \param user_flags bitmask of SI_CPDMA_*
408 void si_copy_buffer(struct si_context
*sctx
,
409 struct pipe_resource
*dst
, struct pipe_resource
*src
,
410 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
413 uint64_t main_dst_offset
, main_src_offset
;
414 unsigned skipped_size
= 0;
415 unsigned realign_size
= 0;
416 unsigned tc_l2_flag
= get_tc_l2_flag(sctx
, SI_COHERENCY_SHADER
);
417 unsigned flush_flags
= get_flush_flags(sctx
, SI_COHERENCY_SHADER
);
418 bool is_first
= true;
423 if (dst
!= src
|| dst_offset
!= src_offset
) {
424 /* Mark the buffer range of destination as valid (initialized),
425 * so that transfer_map knows it should wait for the GPU when mapping
427 util_range_add(&r600_resource(dst
)->valid_buffer_range
, dst_offset
,
431 dst_offset
+= r600_resource(dst
)->gpu_address
;
432 src_offset
+= r600_resource(src
)->gpu_address
;
434 /* The workarounds aren't needed on Fiji and beyond. */
435 if (sctx
->family
<= CHIP_CARRIZO
||
436 sctx
->family
== CHIP_STONEY
) {
437 /* If the size is not aligned, we must add a dummy copy at the end
438 * just to align the internal counter. Otherwise, the DMA engine
439 * would slow down by an order of magnitude for following copies.
441 if (size
% SI_CPDMA_ALIGNMENT
)
442 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
444 /* If the copy begins unaligned, we must start copying from the next
445 * aligned block and the skipped part should be copied after everything
446 * else has been copied. Only the src alignment matters, not dst.
448 if (src_offset
% SI_CPDMA_ALIGNMENT
) {
449 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_offset
% SI_CPDMA_ALIGNMENT
);
450 /* The main part will be skipped if the size is too small. */
451 skipped_size
= MIN2(skipped_size
, size
);
452 size
-= skipped_size
;
456 /* Flush the caches. */
457 if (!(user_flags
& SI_CPDMA_SKIP_GFX_SYNC
))
458 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
459 SI_CONTEXT_CS_PARTIAL_FLUSH
| flush_flags
;
461 /* This is the main part doing the copying. Src is always aligned. */
462 main_dst_offset
= dst_offset
+ skipped_size
;
463 main_src_offset
= src_offset
+ skipped_size
;
466 unsigned dma_flags
= tc_l2_flag
;
467 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(sctx
));
469 si_cp_dma_prepare(sctx
, dst
, src
, byte_count
,
470 size
+ skipped_size
+ realign_size
,
471 user_flags
, &is_first
, &dma_flags
);
473 si_emit_cp_dma(sctx
, main_dst_offset
, main_src_offset
,
474 byte_count
, dma_flags
, SI_COHERENCY_SHADER
);
477 main_src_offset
+= byte_count
;
478 main_dst_offset
+= byte_count
;
481 /* Copy the part we skipped because src wasn't aligned. */
483 unsigned dma_flags
= tc_l2_flag
;
485 si_cp_dma_prepare(sctx
, dst
, src
, skipped_size
,
486 skipped_size
+ realign_size
, user_flags
,
487 &is_first
, &dma_flags
);
489 si_emit_cp_dma(sctx
, dst_offset
, src_offset
, skipped_size
,
490 dma_flags
, SI_COHERENCY_SHADER
);
493 /* Finally, realign the engine if the size wasn't aligned. */
495 si_cp_dma_realign_engine(sctx
, realign_size
, user_flags
,
499 r600_resource(dst
)->TC_L2_dirty
= true;
501 /* If it's not a prefetch... */
502 if (dst_offset
!= src_offset
)
503 sctx
->num_cp_dma_calls
++;
506 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
507 uint64_t offset
, unsigned size
)
509 assert(sctx
->chip_class
>= CIK
);
511 si_copy_buffer(sctx
, buf
, buf
, offset
, offset
, size
, SI_CPDMA_SKIP_ALL
);
514 static void cik_prefetch_shader_async(struct si_context
*sctx
,
515 struct si_pm4_state
*state
)
517 struct pipe_resource
*bo
= &state
->bo
[0]->b
.b
;
518 assert(state
->nbo
== 1);
520 cik_prefetch_TC_L2_async(sctx
, bo
, 0, bo
->width0
);
523 static void cik_prefetch_VBO_descriptors(struct si_context
*sctx
)
525 if (!sctx
->vertex_elements
)
528 cik_prefetch_TC_L2_async(sctx
, &sctx
->vb_descriptors_buffer
->b
.b
,
529 sctx
->vb_descriptors_offset
,
530 sctx
->vertex_elements
->desc_list_byte_size
);
534 * Prefetch shaders and VBO descriptors.
536 * \param vertex_stage_only Whether only the the API VS and VBO descriptors
537 * should be prefetched.
539 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
)
541 unsigned mask
= sctx
->prefetch_L2_mask
;
544 /* Prefetch shaders and VBO descriptors to TC L2. */
545 if (sctx
->chip_class
>= GFX9
) {
546 /* Choose the right spot for the VBO prefetch. */
547 if (sctx
->tes_shader
.cso
) {
548 if (mask
& SI_PREFETCH_HS
)
549 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.hs
);
550 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
551 cik_prefetch_VBO_descriptors(sctx
);
552 if (vertex_stage_only
) {
553 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_HS
|
554 SI_PREFETCH_VBO_DESCRIPTORS
);
558 if (mask
& SI_PREFETCH_GS
)
559 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
560 if (mask
& SI_PREFETCH_VS
)
561 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
562 } else if (sctx
->gs_shader
.cso
) {
563 if (mask
& SI_PREFETCH_GS
)
564 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
565 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
566 cik_prefetch_VBO_descriptors(sctx
);
567 if (vertex_stage_only
) {
568 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_GS
|
569 SI_PREFETCH_VBO_DESCRIPTORS
);
573 if (mask
& SI_PREFETCH_VS
)
574 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
576 if (mask
& SI_PREFETCH_VS
)
577 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
578 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
579 cik_prefetch_VBO_descriptors(sctx
);
580 if (vertex_stage_only
) {
581 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_VS
|
582 SI_PREFETCH_VBO_DESCRIPTORS
);
588 /* Choose the right spot for the VBO prefetch. */
589 if (sctx
->tes_shader
.cso
) {
590 if (mask
& SI_PREFETCH_LS
)
591 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.ls
);
592 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
593 cik_prefetch_VBO_descriptors(sctx
);
594 if (vertex_stage_only
) {
595 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_LS
|
596 SI_PREFETCH_VBO_DESCRIPTORS
);
600 if (mask
& SI_PREFETCH_HS
)
601 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.hs
);
602 if (mask
& SI_PREFETCH_ES
)
603 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.es
);
604 if (mask
& SI_PREFETCH_GS
)
605 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
606 if (mask
& SI_PREFETCH_VS
)
607 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
608 } else if (sctx
->gs_shader
.cso
) {
609 if (mask
& SI_PREFETCH_ES
)
610 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.es
);
611 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
612 cik_prefetch_VBO_descriptors(sctx
);
613 if (vertex_stage_only
) {
614 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_ES
|
615 SI_PREFETCH_VBO_DESCRIPTORS
);
619 if (mask
& SI_PREFETCH_GS
)
620 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
621 if (mask
& SI_PREFETCH_VS
)
622 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
624 if (mask
& SI_PREFETCH_VS
)
625 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
626 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
627 cik_prefetch_VBO_descriptors(sctx
);
628 if (vertex_stage_only
) {
629 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_VS
|
630 SI_PREFETCH_VBO_DESCRIPTORS
);
636 if (mask
& SI_PREFETCH_PS
)
637 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.ps
);
639 sctx
->prefetch_L2_mask
= 0;
642 void si_init_cp_dma_functions(struct si_context
*sctx
)
644 sctx
->b
.clear_buffer
= si_pipe_clear_buffer
;