src/gallium/drivers/radeonsi/si_cp_dma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "sid.h"
  27
  28 /* Recommended maximum sizes for optimal performance.
  29  * Fall back to compute or SDMA if the size is greater.
  30  */
  31 #define CP_DMA_COPY_PERF_THRESHOLD      (64 * 1024) /* copied from Vulkan */
  32 #define CP_DMA_CLEAR_PERF_THRESHOLD     (32 * 1024) /* guess (clear is much slower) */
  33
  34 /* Set this if you want the ME to wait until CP DMA is done.
  35  * It should be set on the last CP DMA packet. */
  36 #define CP_DMA_SYNC             (1 << 0)
  37
  38 /* Set this if the source data was used as a destination in a previous CP DMA
  39  * packet. It's for preventing a read-after-write (RAW) hazard between two
  40  * CP DMA packets. */
  41 #define CP_DMA_RAW_WAIT         (1 << 1)
  42 #define CP_DMA_CLEAR            (1 << 3)
  43 #define CP_DMA_PFP_SYNC_ME      (1 << 4)
  44
  45 /* The max number of bytes that can be copied per packet. */
  46 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
  47 {
  48         unsigned max = sctx->chip_class >= GFX9 ?
  49                                S_414_BYTE_COUNT_GFX9(~0u) :
  50                                S_414_BYTE_COUNT_GFX6(~0u);
  51
  52         /* make it aligned for optimal performance */
  53         return max & ~(SI_CPDMA_ALIGNMENT - 1);
  54 }
  55
  56
  57 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
  58  * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
  59  * clear value.
  60  */
  61 static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
  62                            uint64_t src_va, unsigned size, unsigned flags,
  63                            enum si_cache_policy cache_policy)
  64 {
  65         struct radeon_cmdbuf *cs = sctx->gfx_cs;
  66         uint32_t header = 0, command = 0;
  67
  68         assert(size <= cp_dma_max_byte_count(sctx));
  69         assert(sctx->chip_class != SI || cache_policy == L2_BYPASS);
  70
  71         if (sctx->chip_class >= GFX9)
  72                 command |= S_414_BYTE_COUNT_GFX9(size);
  73         else
  74                 command |= S_414_BYTE_COUNT_GFX6(size);
  75
  76         /* Sync flags. */
  77         if (flags & CP_DMA_SYNC)
  78                 header |= S_411_CP_SYNC(1);
  79         else {
  80                 if (sctx->chip_class >= GFX9)
  81                         command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
  82                 else
  83                         command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
  84         }
  85
  86         if (flags & CP_DMA_RAW_WAIT)
  87                 command |= S_414_RAW_WAIT(1);
  88
  89         /* Src and dst flags. */
  90         if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
  91             src_va == dst_va) {
  92                 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
  93         } else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
  94                 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2) |
  95                           S_500_DST_CACHE_POLICY(cache_policy == L2_STREAM);
  96         }
  97
  98         if (flags & CP_DMA_CLEAR) {
  99                 header |= S_411_SRC_SEL(V_411_DATA);
 100         } else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
 101                 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
 102                           S_500_SRC_CACHE_POLICY(cache_policy == L2_STREAM);
 103         }
 104
 105         if (sctx->chip_class >= CIK) {
 106                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
 107                 radeon_emit(cs, header);
 108                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 109                 radeon_emit(cs, src_va >> 32);  /* SRC_ADDR_HI [31:0] */
 110                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 111                 radeon_emit(cs, dst_va >> 32);  /* DST_ADDR_HI [31:0] */
 112                 radeon_emit(cs, command);
 113         } else {
 114                 header |= S_411_SRC_ADDR_HI(src_va >> 32);
 115
 116                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 117                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 118                 radeon_emit(cs, header);        /* SRC_ADDR_HI [15:0] + flags. */
 119                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 120                 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
 121                 radeon_emit(cs, command);
 122         }
 123
 124         /* CP DMA is executed in ME, but index buffers are read by PFP.
 125          * This ensures that ME (CP DMA) is idle before PFP starts fetching
 126          * indices. If we wanted to execute CP DMA in PFP, this packet
 127          * should precede it.
 128          */
 129         if (flags & CP_DMA_PFP_SYNC_ME) {
 130                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 131                 radeon_emit(cs, 0);
 132         }
 133 }
 134
 135 void si_cp_dma_wait_for_idle(struct si_context *sctx)
 136 {
 137         /* Issue a dummy DMA that copies zero bytes.
 138          *
 139          * The DMA engine will see that there's no work to do and skip this
 140          * DMA request, however, the CP will see the sync flag and still wait
 141          * for all DMAs to complete.
 142          */
 143         si_emit_cp_dma(sctx, 0, 0, 0, CP_DMA_SYNC, L2_BYPASS);
 144 }
 145
 146 static unsigned get_flush_flags(struct si_context *sctx, enum si_coherency coher,
 147                                 enum si_cache_policy cache_policy)
 148 {
 149         switch (coher) {
 150         default:
 151         case SI_COHERENCY_NONE:
 152                 return 0;
 153         case SI_COHERENCY_SHADER:
 154                 assert(sctx->chip_class != SI || cache_policy == L2_BYPASS);
 155                 return SI_CONTEXT_INV_SMEM_L1 |
 156                        SI_CONTEXT_INV_VMEM_L1 |
 157                        (cache_policy == L2_BYPASS ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 158         case SI_COHERENCY_CB_META:
 159                 assert(sctx->chip_class >= GFX9 ? cache_policy != L2_BYPASS :
 160                                                   cache_policy == L2_BYPASS);
 161                 return SI_CONTEXT_FLUSH_AND_INV_CB;
 162         }
 163 }
 164
 165 static enum si_cache_policy get_cache_policy(struct si_context *sctx,
 166                                              enum si_coherency coher)
 167 {
 168         if ((sctx->chip_class >= GFX9 && coher == SI_COHERENCY_CB_META) ||
 169             (sctx->chip_class >= CIK && coher == SI_COHERENCY_SHADER))
 170                 return L2_LRU;
 171
 172         return L2_BYPASS;
 173 }
 174
 175 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 176                               struct pipe_resource *src, unsigned byte_count,
 177                               uint64_t remaining_size, unsigned user_flags,
 178                               enum si_coherency coher, bool *is_first,
 179                               unsigned *packet_flags)
 180 {
 181         /* Fast exit for a CPDMA prefetch. */
 182         if ((user_flags & SI_CPDMA_SKIP_ALL) == SI_CPDMA_SKIP_ALL) {
 183                 *is_first = false;
 184                 return;
 185         }
 186
 187         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 188                 /* Count memory usage in so that need_cs_space can take it into account. */
 189                 si_context_add_resource_size(sctx, dst);
 190                 if (src)
 191                         si_context_add_resource_size(sctx, src);
 192         }
 193
 194         if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
 195                 si_need_gfx_cs_space(sctx);
 196
 197         /* This must be done after need_cs_space. */
 198         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 199                 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
 200                                           r600_resource(dst),
 201                                           RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 202                 if (src)
 203                         radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
 204                                                   r600_resource(src),
 205                                                   RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 206         }
 207
 208         /* Flush the caches for the first copy only.
 209          * Also wait for the previous CP DMA operations.
 210          */
 211         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->flags)
 212                 si_emit_cache_flush(sctx);
 213
 214         if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
 215                 *packet_flags |= CP_DMA_RAW_WAIT;
 216
 217         *is_first = false;
 218
 219         /* Do the synchronization after the last dma, so that all data
 220          * is written to memory.
 221          */
 222         if (!(user_flags & SI_CPDMA_SKIP_SYNC_AFTER) &&
 223             byte_count == remaining_size) {
 224                 *packet_flags |= CP_DMA_SYNC;
 225
 226                 if (coher == SI_COHERENCY_SHADER)
 227                         *packet_flags |= CP_DMA_PFP_SYNC_ME;
 228         }
 229 }
 230
 231 void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 232                             uint64_t offset, uint64_t size, unsigned value,
 233                             enum si_coherency coher,
 234                             enum si_cache_policy cache_policy)
 235 {
 236         struct r600_resource *rdst = r600_resource(dst);
 237         uint64_t va = rdst->gpu_address + offset;
 238         bool is_first = true;
 239
 240         assert(size && size % 4 == 0);
 241
 242         /* Mark the buffer range of destination as valid (initialized),
 243          * so that transfer_map knows it should wait for the GPU when mapping
 244          * that range. */
 245         util_range_add(&rdst->valid_buffer_range, offset, offset + size);
 246
 247         /* Flush the caches. */
 248         sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 249                        SI_CONTEXT_CS_PARTIAL_FLUSH |
 250                        get_flush_flags(sctx, coher, cache_policy);
 251
 252         while (size) {
 253                 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
 254                 unsigned dma_flags = CP_DMA_CLEAR;
 255
 256                 si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 0, coher,
 257                                   &is_first, &dma_flags);
 258
 259                 /* Emit the clear packet. */
 260                 si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, cache_policy);
 261
 262                 size -= byte_count;
 263                 va += byte_count;
 264         }
 265
 266         if (cache_policy != L2_BYPASS)
 267                 rdst->TC_L2_dirty = true;
 268
 269         /* If it's not a framebuffer fast clear... */
 270         if (coher == SI_COHERENCY_SHADER)
 271                 sctx->num_cp_dma_calls++;
 272 }
 273
 274 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 275                      uint64_t offset, uint64_t size, unsigned value,
 276                      enum si_coherency coher)
 277 {
 278         struct radeon_winsys *ws = sctx->ws;
 279         struct r600_resource *rdst = r600_resource(dst);
 280         enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
 281         uint64_t dma_clear_size;
 282
 283         if (!size)
 284                 return;
 285
 286         dma_clear_size = size & ~3ull;
 287
 288         /* dma_clear_buffer can use clear_buffer on failure. Make sure that
 289          * doesn't happen. We don't want an infinite recursion: */
 290         if (sctx->dma_cs &&
 291             !(dst->flags & PIPE_RESOURCE_FLAG_SPARSE) &&
 292             (offset % 4 == 0) &&
 293             /* CP DMA is very slow. Always use SDMA for big clears. This
 294              * alone improves DeusEx:MD performance by 70%. */
 295             (size > CP_DMA_CLEAR_PERF_THRESHOLD ||
 296              /* Buffers not used by the GFX IB yet will be cleared by SDMA.
 297               * This happens to move most buffer clears to SDMA, including
 298               * DCC and CMASK clears, because pipe->clear clears them before
 299               * si_emit_framebuffer_state (in a draw call) adds them.
 300               * For example, DeusEx:MD has 21 buffer clears per frame and all
 301               * of them are moved to SDMA thanks to this. */
 302              !ws->cs_is_buffer_referenced(sctx->gfx_cs, rdst->buf,
 303                                           RADEON_USAGE_READWRITE))) {
 304                 si_sdma_clear_buffer(sctx, dst, offset, dma_clear_size, value);
 305
 306                 offset += dma_clear_size;
 307                 size -= dma_clear_size;
 308         } else if (dma_clear_size >= 4) {
 309                 si_cp_dma_clear_buffer(sctx, dst, offset, dma_clear_size, value,
 310                                        coher, cache_policy);
 311
 312                 offset += dma_clear_size;
 313                 size -= dma_clear_size;
 314         }
 315
 316         if (size) {
 317                 /* Handle non-dword alignment.
 318                  *
 319                  * This function is called for embedded texture metadata clears,
 320                  * but those should always be properly aligned. */
 321                 assert(dst->target == PIPE_BUFFER);
 322                 assert(size < 4);
 323
 324                 pipe_buffer_write(&sctx->b, dst, offset, size, &value);
 325         }
 326 }
 327
 328 static void si_pipe_clear_buffer(struct pipe_context *ctx,
 329                                  struct pipe_resource *dst,
 330                                  unsigned offset, unsigned size,
 331                                  const void *clear_value_ptr,
 332                                  int clear_value_size)
 333 {
 334         struct si_context *sctx = (struct si_context*)ctx;
 335         uint32_t dword_value;
 336         unsigned i;
 337
 338         assert(offset % clear_value_size == 0);
 339         assert(size % clear_value_size == 0);
 340
 341         if (clear_value_size > 4) {
 342                 const uint32_t *u32 = clear_value_ptr;
 343                 bool clear_dword_duplicated = true;
 344
 345                 /* See if we can lower large fills to dword fills. */
 346                 for (i = 1; i < clear_value_size / 4; i++)
 347                         if (u32[0] != u32[i]) {
 348                                 clear_dword_duplicated = false;
 349                                 break;
 350                         }
 351
 352                 if (!clear_dword_duplicated) {
 353                         /* Use transform feedback for 64-bit, 96-bit, and
 354                          * 128-bit fills.
 355                          */
 356                         union pipe_color_union clear_value;
 357
 358                         memcpy(&clear_value, clear_value_ptr, clear_value_size);
 359                         si_blitter_begin(sctx, SI_DISABLE_RENDER_COND);
 360                         util_blitter_clear_buffer(sctx->blitter, dst, offset,
 361                                                   size, clear_value_size / 4,
 362                                                   &clear_value);
 363                         si_blitter_end(sctx);
 364                         return;
 365                 }
 366         }
 367
 368         /* Expand the clear value to a dword. */
 369         switch (clear_value_size) {
 370         case 1:
 371                 dword_value = *(uint8_t*)clear_value_ptr;
 372                 dword_value |= (dword_value << 8) |
 373                                (dword_value << 16) |
 374                                (dword_value << 24);
 375                 break;
 376         case 2:
 377                 dword_value = *(uint16_t*)clear_value_ptr;
 378                 dword_value |= dword_value << 16;
 379                 break;
 380         default:
 381                 dword_value = *(uint32_t*)clear_value_ptr;
 382         }
 383
 384         si_clear_buffer(sctx, dst, offset, size, dword_value,
 385                         SI_COHERENCY_SHADER);
 386 }
 387
 388 /**
 389  * Realign the CP DMA engine. This must be done after a copy with an unaligned
 390  * size.
 391  *
 392  * \param size  Remaining size to the CP DMA alignment.
 393  */
 394 static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 395                                      unsigned user_flags, enum si_coherency coher,
 396                                      enum si_cache_policy cache_policy,
 397                                      bool *is_first)
 398 {
 399         uint64_t va;
 400         unsigned dma_flags = 0;
 401         unsigned scratch_size = SI_CPDMA_ALIGNMENT * 2;
 402
 403         assert(size < SI_CPDMA_ALIGNMENT);
 404
 405         /* Use the scratch buffer as the dummy buffer. The 3D engine should be
 406          * idle at this point.
 407          */
 408         if (!sctx->scratch_buffer ||
 409             sctx->scratch_buffer->b.b.width0 < scratch_size) {
 410                 r600_resource_reference(&sctx->scratch_buffer, NULL);
 411                 sctx->scratch_buffer =
 412                         si_aligned_buffer_create(&sctx->screen->b,
 413                                                    SI_RESOURCE_FLAG_UNMAPPABLE,
 414                                                    PIPE_USAGE_DEFAULT,
 415                                                    scratch_size, 256);
 416                 if (!sctx->scratch_buffer)
 417                         return;
 418
 419                 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
 420         }
 421
 422         si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
 423                           &sctx->scratch_buffer->b.b, size, size, user_flags,
 424                           coher, is_first, &dma_flags);
 425
 426         va = sctx->scratch_buffer->gpu_address;
 427         si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
 428                        cache_policy);
 429 }
 430
 431 /**
 432  * Do memcpy between buffers using CP DMA.
 433  *
 434  * \param user_flags    bitmask of SI_CPDMA_*
 435  */
 436 void si_copy_buffer(struct si_context *sctx,
 437                     struct pipe_resource *dst, struct pipe_resource *src,
 438                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 439                     unsigned user_flags, enum si_cache_policy cache_policy)
 440 {
 441         uint64_t main_dst_offset, main_src_offset;
 442         unsigned skipped_size = 0;
 443         unsigned realign_size = 0;
 444         enum si_coherency coher = SI_COHERENCY_SHADER;
 445         bool is_first = true;
 446
 447         if (!size)
 448                 return;
 449
 450         if (cache_policy == -1)
 451                 cache_policy = get_cache_policy(sctx, coher);
 452
 453         if (dst != src || dst_offset != src_offset) {
 454                 /* Mark the buffer range of destination as valid (initialized),
 455                  * so that transfer_map knows it should wait for the GPU when mapping
 456                  * that range. */
 457                 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
 458                                dst_offset + size);
 459         }
 460
 461         dst_offset += r600_resource(dst)->gpu_address;
 462         src_offset += r600_resource(src)->gpu_address;
 463
 464         /* The workarounds aren't needed on Fiji and beyond. */
 465         if (sctx->family <= CHIP_CARRIZO ||
 466             sctx->family == CHIP_STONEY) {
 467                 /* If the size is not aligned, we must add a dummy copy at the end
 468                  * just to align the internal counter. Otherwise, the DMA engine
 469                  * would slow down by an order of magnitude for following copies.
 470                  */
 471                 if (size % SI_CPDMA_ALIGNMENT)
 472                         realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
 473
 474                 /* If the copy begins unaligned, we must start copying from the next
 475                  * aligned block and the skipped part should be copied after everything
 476                  * else has been copied. Only the src alignment matters, not dst.
 477                  */
 478                 if (src_offset % SI_CPDMA_ALIGNMENT) {
 479                         skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT);
 480                         /* The main part will be skipped if the size is too small. */
 481                         skipped_size = MIN2(skipped_size, size);
 482                         size -= skipped_size;
 483                 }
 484         }
 485
 486         /* Flush the caches. */
 487         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
 488                 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 489                                SI_CONTEXT_CS_PARTIAL_FLUSH |
 490                                get_flush_flags(sctx, coher, cache_policy);
 491         }
 492
 493         /* This is the main part doing the copying. Src is always aligned. */
 494         main_dst_offset = dst_offset + skipped_size;
 495         main_src_offset = src_offset + skipped_size;
 496
 497         while (size) {
 498                 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
 499                 unsigned dma_flags = 0;
 500
 501                 si_cp_dma_prepare(sctx, dst, src, byte_count,
 502                                   size + skipped_size + realign_size,
 503                                   user_flags, coher, &is_first, &dma_flags);
 504
 505                 si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
 506                                byte_count, dma_flags, cache_policy);
 507
 508                 size -= byte_count;
 509                 main_src_offset += byte_count;
 510                 main_dst_offset += byte_count;
 511         }
 512
 513         /* Copy the part we skipped because src wasn't aligned. */
 514         if (skipped_size) {
 515                 unsigned dma_flags = 0;
 516
 517                 si_cp_dma_prepare(sctx, dst, src, skipped_size,
 518                                   skipped_size + realign_size, user_flags,
 519                                   coher, &is_first, &dma_flags);
 520
 521                 si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
 522                                dma_flags, cache_policy);
 523         }
 524
 525         /* Finally, realign the engine if the size wasn't aligned. */
 526         if (realign_size) {
 527                 si_cp_dma_realign_engine(sctx, realign_size, user_flags, coher,
 528                                          cache_policy, &is_first);
 529         }
 530
 531         if (cache_policy != L2_BYPASS)
 532                 r600_resource(dst)->TC_L2_dirty = true;
 533
 534         /* If it's not a prefetch... */
 535         if (dst_offset != src_offset)
 536                 sctx->num_cp_dma_calls++;
 537 }
 538
 539 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 540                               uint64_t offset, unsigned size)
 541 {
 542         assert(sctx->chip_class >= CIK);
 543
 544         si_copy_buffer(sctx, buf, buf, offset, offset, size, SI_CPDMA_SKIP_ALL, L2_LRU);
 545 }
 546
 547 static void cik_prefetch_shader_async(struct si_context *sctx,
 548                                       struct si_pm4_state *state)
 549 {
 550         struct pipe_resource *bo = &state->bo[0]->b.b;
 551         assert(state->nbo == 1);
 552
 553         cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
 554 }
 555
 556 static void cik_prefetch_VBO_descriptors(struct si_context *sctx)
 557 {
 558         if (!sctx->vertex_elements)
 559                 return;
 560
 561         cik_prefetch_TC_L2_async(sctx, &sctx->vb_descriptors_buffer->b.b,
 562                                  sctx->vb_descriptors_offset,
 563                                  sctx->vertex_elements->desc_list_byte_size);
 564 }
 565
 566 /**
 567  * Prefetch shaders and VBO descriptors.
 568  *
 569  * \param vertex_stage_only  Whether only the the API VS and VBO descriptors
 570  *                           should be prefetched.
 571  */
 572 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only)
 573 {
 574         unsigned mask = sctx->prefetch_L2_mask;
 575         assert(mask);
 576
 577         /* Prefetch shaders and VBO descriptors to TC L2. */
 578         if (sctx->chip_class >= GFX9) {
 579                 /* Choose the right spot for the VBO prefetch. */
 580                 if (sctx->tes_shader.cso) {
 581                         if (mask & SI_PREFETCH_HS)
 582                                 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 583                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 584                                 cik_prefetch_VBO_descriptors(sctx);
 585                         if (vertex_stage_only) {
 586                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_HS |
 587                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 588                                 return;
 589                         }
 590
 591                         if (mask & SI_PREFETCH_GS)
 592                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 593                         if (mask & SI_PREFETCH_VS)
 594                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 595                 } else if (sctx->gs_shader.cso) {
 596                         if (mask & SI_PREFETCH_GS)
 597                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 598                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 599                                 cik_prefetch_VBO_descriptors(sctx);
 600                         if (vertex_stage_only) {
 601                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_GS |
 602                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 603                                 return;
 604                         }
 605
 606                         if (mask & SI_PREFETCH_VS)
 607                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 608                 } else {
 609                         if (mask & SI_PREFETCH_VS)
 610                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 611                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 612                                 cik_prefetch_VBO_descriptors(sctx);
 613                         if (vertex_stage_only) {
 614                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_VS |
 615                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 616                                 return;
 617                         }
 618                 }
 619         } else {
 620                 /* SI-CI-VI */
 621                 /* Choose the right spot for the VBO prefetch. */
 622                 if (sctx->tes_shader.cso) {
 623                         if (mask & SI_PREFETCH_LS)
 624                                 cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
 625                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 626                                 cik_prefetch_VBO_descriptors(sctx);
 627                         if (vertex_stage_only) {
 628                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_LS |
 629                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 630                                 return;
 631                         }
 632
 633                         if (mask & SI_PREFETCH_HS)
 634                                 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 635                         if (mask & SI_PREFETCH_ES)
 636                                 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
 637                         if (mask & SI_PREFETCH_GS)
 638                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 639                         if (mask & SI_PREFETCH_VS)
 640                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 641                 } else if (sctx->gs_shader.cso) {
 642                         if (mask & SI_PREFETCH_ES)
 643                                 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
 644                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 645                                 cik_prefetch_VBO_descriptors(sctx);
 646                         if (vertex_stage_only) {
 647                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_ES |
 648                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 649                                 return;
 650                         }
 651
 652                         if (mask & SI_PREFETCH_GS)
 653                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 654                         if (mask & SI_PREFETCH_VS)
 655                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 656                 } else {
 657                         if (mask & SI_PREFETCH_VS)
 658                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 659                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 660                                 cik_prefetch_VBO_descriptors(sctx);
 661                         if (vertex_stage_only) {
 662                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_VS |
 663                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 664                                 return;
 665                         }
 666                 }
 667         }
 668
 669         if (mask & SI_PREFETCH_PS)
 670                 cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
 671
 672         sctx->prefetch_L2_mask = 0;
 673 }
 674
 675 void si_init_cp_dma_functions(struct si_context *sctx)
 676 {
 677         sctx->b.clear_buffer = si_pipe_clear_buffer;
 678 }