src/gallium/drivers/radeonsi/si_cp_dma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "sid.h"
  27 #include "radeon/r600_cs.h"
  28
  29 /* Recommended maximum sizes for optimal performance.
  30  * Fall back to compute or SDMA if the size is greater.
  31  */
  32 #define CP_DMA_COPY_PERF_THRESHOLD      (64 * 1024) /* copied from Vulkan */
  33 #define CP_DMA_CLEAR_PERF_THRESHOLD     (32 * 1024) /* guess (clear is much slower) */
  34
  35 /* Set this if you want the ME to wait until CP DMA is done.
  36  * It should be set on the last CP DMA packet. */
  37 #define CP_DMA_SYNC             (1 << 0)
  38
  39 /* Set this if the source data was used as a destination in a previous CP DMA
  40  * packet. It's for preventing a read-after-write (RAW) hazard between two
  41  * CP DMA packets. */
  42 #define CP_DMA_RAW_WAIT         (1 << 1)
  43 #define CP_DMA_USE_L2           (1 << 2) /* CIK+ */
  44 #define CP_DMA_CLEAR            (1 << 3)
  45
  46 /* The max number of bytes that can be copied per packet. */
  47 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
  48 {
  49         unsigned max = sctx->b.chip_class >= GFX9 ?
  50                                S_414_BYTE_COUNT_GFX9(~0u) :
  51                                S_414_BYTE_COUNT_GFX6(~0u);
  52
  53         /* make it aligned for optimal performance */
  54         return max & ~(SI_CPDMA_ALIGNMENT - 1);
  55 }
  56
  57
  58 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
  59  * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
  60  * clear value.
  61  */
  62 static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
  63                            uint64_t src_va, unsigned size, unsigned flags,
  64                            enum r600_coherency coher)
  65 {
  66         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
  67         uint32_t header = 0, command = 0;
  68
  69         assert(size);
  70         assert(size <= cp_dma_max_byte_count(sctx));
  71
  72         if (sctx->b.chip_class >= GFX9)
  73                 command |= S_414_BYTE_COUNT_GFX9(size);
  74         else
  75                 command |= S_414_BYTE_COUNT_GFX6(size);
  76
  77         /* Sync flags. */
  78         if (flags & CP_DMA_SYNC)
  79                 header |= S_411_CP_SYNC(1);
  80         else {
  81                 if (sctx->b.chip_class >= GFX9)
  82                         command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
  83                 else
  84                         command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
  85         }
  86
  87         if (flags & CP_DMA_RAW_WAIT)
  88                 command |= S_414_RAW_WAIT(1);
  89
  90         /* Src and dst flags. */
  91         if (sctx->b.chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
  92             src_va == dst_va)
  93                 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
  94         else if (flags & CP_DMA_USE_L2)
  95                 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
  96
  97         if (flags & CP_DMA_CLEAR)
  98                 header |= S_411_SRC_SEL(V_411_DATA);
  99         else if (flags & CP_DMA_USE_L2)
 100                 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
 101
 102         if (sctx->b.chip_class >= CIK) {
 103                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
 104                 radeon_emit(cs, header);
 105                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 106                 radeon_emit(cs, src_va >> 32);  /* SRC_ADDR_HI [31:0] */
 107                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 108                 radeon_emit(cs, dst_va >> 32);  /* DST_ADDR_HI [31:0] */
 109                 radeon_emit(cs, command);
 110         } else {
 111                 header |= S_411_SRC_ADDR_HI(src_va >> 32);
 112
 113                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 114                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 115                 radeon_emit(cs, header);        /* SRC_ADDR_HI [15:0] + flags. */
 116                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 117                 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
 118                 radeon_emit(cs, command);
 119         }
 120
 121         /* CP DMA is executed in ME, but index buffers are read by PFP.
 122          * This ensures that ME (CP DMA) is idle before PFP starts fetching
 123          * indices. If we wanted to execute CP DMA in PFP, this packet
 124          * should precede it.
 125          */
 126         if (coher == R600_COHERENCY_SHADER && flags & CP_DMA_SYNC) {
 127                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 128                 radeon_emit(cs, 0);
 129         }
 130 }
 131
 132 static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher)
 133 {
 134         switch (coher) {
 135         default:
 136         case R600_COHERENCY_NONE:
 137                 return 0;
 138         case R600_COHERENCY_SHADER:
 139                 return SI_CONTEXT_INV_SMEM_L1 |
 140                        SI_CONTEXT_INV_VMEM_L1 |
 141                        (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 142         case R600_COHERENCY_CB_META:
 143                 return SI_CONTEXT_FLUSH_AND_INV_CB;
 144         }
 145 }
 146
 147 static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher)
 148 {
 149         if ((sctx->b.chip_class >= GFX9 && coher == R600_COHERENCY_CB_META) ||
 150             (sctx->b.chip_class >= CIK && coher == R600_COHERENCY_SHADER))
 151                 return CP_DMA_USE_L2;
 152
 153         return 0;
 154 }
 155
 156 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 157                               struct pipe_resource *src, unsigned byte_count,
 158                               uint64_t remaining_size, unsigned user_flags,
 159                               bool *is_first, unsigned *packet_flags)
 160 {
 161         /* Fast exit for a CPDMA prefetch. */
 162         if ((user_flags & SI_CPDMA_SKIP_ALL) == SI_CPDMA_SKIP_ALL) {
 163                 *is_first = false;
 164                 return;
 165         }
 166
 167         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 168                 /* Count memory usage in so that need_cs_space can take it into account. */
 169                 si_context_add_resource_size(sctx, dst);
 170                 if (src)
 171                         si_context_add_resource_size(sctx, src);
 172         }
 173
 174         if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
 175                 si_need_gfx_cs_space(sctx);
 176
 177         /* This must be done after need_cs_space. */
 178         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 179                 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
 180                                           (struct r600_resource*)dst,
 181                                           RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 182                 if (src)
 183                         radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
 184                                                   (struct r600_resource*)src,
 185                                                   RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 186         }
 187
 188         /* Flush the caches for the first copy only.
 189          * Also wait for the previous CP DMA operations.
 190          */
 191         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->b.flags)
 192                 si_emit_cache_flush(sctx);
 193
 194         if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
 195                 *packet_flags |= CP_DMA_RAW_WAIT;
 196
 197         *is_first = false;
 198
 199         /* Do the synchronization after the last dma, so that all data
 200          * is written to memory.
 201          */
 202         if (!(user_flags & SI_CPDMA_SKIP_SYNC_AFTER) &&
 203             byte_count == remaining_size)
 204                 *packet_flags |= CP_DMA_SYNC;
 205 }
 206
 207 void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 208                      uint64_t offset, uint64_t size, unsigned value,
 209                      enum r600_coherency coher)
 210 {
 211         struct si_context *sctx = (struct si_context*)ctx;
 212         struct radeon_winsys *ws = sctx->b.ws;
 213         struct r600_resource *rdst = r600_resource(dst);
 214         unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
 215         unsigned flush_flags = get_flush_flags(sctx, coher);
 216         uint64_t dma_clear_size;
 217         bool is_first = true;
 218
 219         if (!size)
 220                 return;
 221
 222        dma_clear_size = size & ~3ull;
 223
 224         /* Mark the buffer range of destination as valid (initialized),
 225          * so that transfer_map knows it should wait for the GPU when mapping
 226          * that range. */
 227         util_range_add(&rdst->valid_buffer_range, offset,
 228                        offset + dma_clear_size);
 229
 230         /* dma_clear_buffer can use clear_buffer on failure. Make sure that
 231          * doesn't happen. We don't want an infinite recursion: */
 232         if (sctx->b.dma_cs &&
 233             !(dst->flags & PIPE_RESOURCE_FLAG_SPARSE) &&
 234             (offset % 4 == 0) &&
 235             /* CP DMA is very slow. Always use SDMA for big clears. This
 236              * alone improves DeusEx:MD performance by 70%. */
 237             (size > CP_DMA_CLEAR_PERF_THRESHOLD ||
 238              /* Buffers not used by the GFX IB yet will be cleared by SDMA.
 239               * This happens to move most buffer clears to SDMA, including
 240               * DCC and CMASK clears, because pipe->clear clears them before
 241               * si_emit_framebuffer_state (in a draw call) adds them.
 242               * For example, DeusEx:MD has 21 buffer clears per frame and all
 243               * of them are moved to SDMA thanks to this. */
 244              !ws->cs_is_buffer_referenced(sctx->b.gfx_cs, rdst->buf,
 245                                           RADEON_USAGE_READWRITE))) {
 246                 sctx->b.dma_clear_buffer(ctx, dst, offset, dma_clear_size, value);
 247
 248                 offset += dma_clear_size;
 249                 size -= dma_clear_size;
 250         } else if (dma_clear_size >= 4) {
 251                 uint64_t va = rdst->gpu_address + offset;
 252
 253                 offset += dma_clear_size;
 254                 size -= dma_clear_size;
 255
 256                 /* Flush the caches. */
 257                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 258                                  SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 259
 260                 while (dma_clear_size) {
 261                         unsigned byte_count = MIN2(dma_clear_size, cp_dma_max_byte_count(sctx));
 262                         unsigned dma_flags = tc_l2_flag  | CP_DMA_CLEAR;
 263
 264                         si_cp_dma_prepare(sctx, dst, NULL, byte_count, dma_clear_size, 0,
 265                                           &is_first, &dma_flags);
 266
 267                         /* Emit the clear packet. */
 268                         si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, coher);
 269
 270                         dma_clear_size -= byte_count;
 271                         va += byte_count;
 272                 }
 273
 274                 if (tc_l2_flag)
 275                         rdst->TC_L2_dirty = true;
 276
 277                 /* If it's not a framebuffer fast clear... */
 278                 if (coher == R600_COHERENCY_SHADER)
 279                         sctx->b.num_cp_dma_calls++;
 280         }
 281
 282         if (size) {
 283                 /* Handle non-dword alignment.
 284                  *
 285                  * This function is called for embedded texture metadata clears,
 286                  * but those should always be properly aligned. */
 287                 assert(dst->target == PIPE_BUFFER);
 288                 assert(size < 4);
 289
 290                 pipe_buffer_write(ctx, dst, offset, size, &value);
 291         }
 292 }
 293
 294 static void si_pipe_clear_buffer(struct pipe_context *ctx,
 295                                  struct pipe_resource *dst,
 296                                  unsigned offset, unsigned size,
 297                                  const void *clear_value_ptr,
 298                                  int clear_value_size)
 299 {
 300         struct si_context *sctx = (struct si_context*)ctx;
 301         uint32_t dword_value;
 302         unsigned i;
 303
 304         assert(offset % clear_value_size == 0);
 305         assert(size % clear_value_size == 0);
 306
 307         if (clear_value_size > 4) {
 308                 const uint32_t *u32 = clear_value_ptr;
 309                 bool clear_dword_duplicated = true;
 310
 311                 /* See if we can lower large fills to dword fills. */
 312                 for (i = 1; i < clear_value_size / 4; i++)
 313                         if (u32[0] != u32[i]) {
 314                                 clear_dword_duplicated = false;
 315                                 break;
 316                         }
 317
 318                 if (!clear_dword_duplicated) {
 319                         /* Use transform feedback for 64-bit, 96-bit, and
 320                          * 128-bit fills.
 321                          */
 322                         union pipe_color_union clear_value;
 323
 324                         memcpy(&clear_value, clear_value_ptr, clear_value_size);
 325                         si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
 326                         util_blitter_clear_buffer(sctx->blitter, dst, offset,
 327                                                   size, clear_value_size / 4,
 328                                                   &clear_value);
 329                         si_blitter_end(ctx);
 330                         return;
 331                 }
 332         }
 333
 334         /* Expand the clear value to a dword. */
 335         switch (clear_value_size) {
 336         case 1:
 337                 dword_value = *(uint8_t*)clear_value_ptr;
 338                 dword_value |= (dword_value << 8) |
 339                                (dword_value << 16) |
 340                                (dword_value << 24);
 341                 break;
 342         case 2:
 343                 dword_value = *(uint16_t*)clear_value_ptr;
 344                 dword_value |= dword_value << 16;
 345                 break;
 346         default:
 347                 dword_value = *(uint32_t*)clear_value_ptr;
 348         }
 349
 350         si_clear_buffer(ctx, dst, offset, size, dword_value,
 351                         R600_COHERENCY_SHADER);
 352 }
 353
 354 /**
 355  * Realign the CP DMA engine. This must be done after a copy with an unaligned
 356  * size.
 357  *
 358  * \param size  Remaining size to the CP DMA alignment.
 359  */
 360 static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 361                                      unsigned user_flags, bool *is_first)
 362 {
 363         uint64_t va;
 364         unsigned dma_flags = 0;
 365         unsigned scratch_size = SI_CPDMA_ALIGNMENT * 2;
 366
 367         assert(size < SI_CPDMA_ALIGNMENT);
 368
 369         /* Use the scratch buffer as the dummy buffer. The 3D engine should be
 370          * idle at this point.
 371          */
 372         if (!sctx->scratch_buffer ||
 373             sctx->scratch_buffer->b.b.width0 < scratch_size) {
 374                 r600_resource_reference(&sctx->scratch_buffer, NULL);
 375                 sctx->scratch_buffer = (struct r600_resource*)
 376                         si_aligned_buffer_create(&sctx->screen->b,
 377                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 378                                                    PIPE_USAGE_DEFAULT,
 379                                                    scratch_size, 256);
 380                 if (!sctx->scratch_buffer)
 381                         return;
 382
 383                 si_mark_atom_dirty(sctx, &sctx->scratch_state);
 384         }
 385
 386         si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
 387                           &sctx->scratch_buffer->b.b, size, size, user_flags,
 388                           is_first, &dma_flags);
 389
 390         va = sctx->scratch_buffer->gpu_address;
 391         si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
 392                        R600_COHERENCY_SHADER);
 393 }
 394
 395 /**
 396  * Do memcpy between buffers using CP DMA.
 397  *
 398  * \param user_flags    bitmask of SI_CPDMA_*
 399  */
 400 void si_copy_buffer(struct si_context *sctx,
 401                     struct pipe_resource *dst, struct pipe_resource *src,
 402                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 403                     unsigned user_flags)
 404 {
 405         uint64_t main_dst_offset, main_src_offset;
 406         unsigned skipped_size = 0;
 407         unsigned realign_size = 0;
 408         unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER);
 409         unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER);
 410         bool is_first = true;
 411
 412         if (!size)
 413                 return;
 414
 415         if (dst != src || dst_offset != src_offset) {
 416                 /* Mark the buffer range of destination as valid (initialized),
 417                  * so that transfer_map knows it should wait for the GPU when mapping
 418                  * that range. */
 419                 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
 420                                dst_offset + size);
 421         }
 422
 423         dst_offset += r600_resource(dst)->gpu_address;
 424         src_offset += r600_resource(src)->gpu_address;
 425
 426         /* The workarounds aren't needed on Fiji and beyond. */
 427         if (sctx->b.family <= CHIP_CARRIZO ||
 428             sctx->b.family == CHIP_STONEY) {
 429                 /* If the size is not aligned, we must add a dummy copy at the end
 430                  * just to align the internal counter. Otherwise, the DMA engine
 431                  * would slow down by an order of magnitude for following copies.
 432                  */
 433                 if (size % SI_CPDMA_ALIGNMENT)
 434                         realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
 435
 436                 /* If the copy begins unaligned, we must start copying from the next
 437                  * aligned block and the skipped part should be copied after everything
 438                  * else has been copied. Only the src alignment matters, not dst.
 439                  */
 440                 if (src_offset % SI_CPDMA_ALIGNMENT) {
 441                         skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT);
 442                         /* The main part will be skipped if the size is too small. */
 443                         skipped_size = MIN2(skipped_size, size);
 444                         size -= skipped_size;
 445                 }
 446         }
 447
 448         /* Flush the caches. */
 449         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC))
 450                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 451                                  SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
 452
 453         /* This is the main part doing the copying. Src is always aligned. */
 454         main_dst_offset = dst_offset + skipped_size;
 455         main_src_offset = src_offset + skipped_size;
 456
 457         while (size) {
 458                 unsigned dma_flags = tc_l2_flag;
 459                 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
 460
 461                 si_cp_dma_prepare(sctx, dst, src, byte_count,
 462                                   size + skipped_size + realign_size,
 463                                   user_flags, &is_first, &dma_flags);
 464
 465                 si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
 466                                byte_count, dma_flags, R600_COHERENCY_SHADER);
 467
 468                 size -= byte_count;
 469                 main_src_offset += byte_count;
 470                 main_dst_offset += byte_count;
 471         }
 472
 473         /* Copy the part we skipped because src wasn't aligned. */
 474         if (skipped_size) {
 475                 unsigned dma_flags = tc_l2_flag;
 476
 477                 si_cp_dma_prepare(sctx, dst, src, skipped_size,
 478                                   skipped_size + realign_size, user_flags,
 479                                   &is_first, &dma_flags);
 480
 481                 si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
 482                                dma_flags, R600_COHERENCY_SHADER);
 483         }
 484
 485         /* Finally, realign the engine if the size wasn't aligned. */
 486         if (realign_size)
 487                 si_cp_dma_realign_engine(sctx, realign_size, user_flags,
 488                                          &is_first);
 489
 490         if (tc_l2_flag)
 491                 r600_resource(dst)->TC_L2_dirty = true;
 492
 493         /* If it's not a prefetch... */
 494         if (dst_offset != src_offset)
 495                 sctx->b.num_cp_dma_calls++;
 496 }
 497
 498 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 499                               uint64_t offset, unsigned size)
 500 {
 501         assert(sctx->b.chip_class >= CIK);
 502
 503         si_copy_buffer(sctx, buf, buf, offset, offset, size, SI_CPDMA_SKIP_ALL);
 504 }
 505
 506 static void cik_prefetch_shader_async(struct si_context *sctx,
 507                                       struct si_pm4_state *state)
 508 {
 509         struct pipe_resource *bo = &state->bo[0]->b.b;
 510         assert(state->nbo == 1);
 511
 512         cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
 513 }
 514
 515 static void cik_prefetch_VBO_descriptors(struct si_context *sctx)
 516 {
 517         if (!sctx->vertex_elements)
 518                 return;
 519
 520         cik_prefetch_TC_L2_async(sctx, &sctx->vb_descriptors_buffer->b.b,
 521                                  sctx->vb_descriptors_offset,
 522                                  sctx->vertex_elements->desc_list_byte_size);
 523 }
 524
 525 void cik_emit_prefetch_L2(struct si_context *sctx)
 526 {
 527         /* Prefetch shaders and VBO descriptors to TC L2. */
 528         if (sctx->b.chip_class >= GFX9) {
 529                 /* Choose the right spot for the VBO prefetch. */
 530                 if (sctx->tes_shader.cso) {
 531                         if (sctx->prefetch_L2_mask & SI_PREFETCH_HS)
 532                                 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 533                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
 534                                 cik_prefetch_VBO_descriptors(sctx);
 535                         if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
 536                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 537                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
 538                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 539                 } else if (sctx->gs_shader.cso) {
 540                         if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
 541                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 542                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
 543                                 cik_prefetch_VBO_descriptors(sctx);
 544                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
 545                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 546                 } else {
 547                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
 548                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 549                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
 550                                 cik_prefetch_VBO_descriptors(sctx);
 551                 }
 552         } else {
 553                 /* SI-CI-VI */
 554                 /* Choose the right spot for the VBO prefetch. */
 555                 if (sctx->tes_shader.cso) {
 556                         if (sctx->prefetch_L2_mask & SI_PREFETCH_LS)
 557                                 cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
 558                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
 559                                 cik_prefetch_VBO_descriptors(sctx);
 560                         if (sctx->prefetch_L2_mask & SI_PREFETCH_HS)
 561                                 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 562                         if (sctx->prefetch_L2_mask & SI_PREFETCH_ES)
 563                                 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
 564                         if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
 565                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 566                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
 567                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 568                 } else if (sctx->gs_shader.cso) {
 569                         if (sctx->prefetch_L2_mask & SI_PREFETCH_ES)
 570                                 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
 571                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
 572                                 cik_prefetch_VBO_descriptors(sctx);
 573                         if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
 574                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 575                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
 576                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 577                 } else {
 578                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
 579                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 580                         if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
 581                                 cik_prefetch_VBO_descriptors(sctx);
 582                 }
 583         }
 584
 585         if (sctx->prefetch_L2_mask & SI_PREFETCH_PS)
 586                 cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
 587
 588         sctx->prefetch_L2_mask = 0;
 589 }
 590
 591 void si_init_cp_dma_functions(struct si_context *sctx)
 592 {
 593         sctx->b.b.clear_buffer = si_pipe_clear_buffer;
 594 }