2 * Copyright 2015 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_compute.h"
29 #include "sid_tables.h"
30 #include "driver_ddebug/dd_util.h"
31 #include "util/u_dump.h"
32 #include "util/u_log.h"
33 #include "util/u_memory.h"
34 #include "util/u_string.h"
37 static void si_dump_bo_list(struct si_context
*sctx
,
38 const struct radeon_saved_cs
*saved
, FILE *f
);
40 DEBUG_GET_ONCE_OPTION(replace_shaders
, "RADEON_REPLACE_SHADERS", NULL
)
43 * Store a linearized copy of all chunks of \p cs together with the buffer
46 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
47 struct radeon_saved_cs
*saved
, bool get_buffer_list
)
52 /* Save the IB chunks. */
53 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
54 saved
->ib
= MALLOC(4 * saved
->num_dw
);
59 for (i
= 0; i
< cs
->num_prev
; ++i
) {
60 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
61 buf
+= cs
->prev
[i
].cdw
;
63 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
68 /* Save the buffer list. */
69 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
70 saved
->bo_list
= CALLOC(saved
->bo_count
,
71 sizeof(saved
->bo_list
[0]));
72 if (!saved
->bo_list
) {
76 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
81 fprintf(stderr
, "%s: out of memory\n", __func__
);
82 memset(saved
, 0, sizeof(*saved
));
85 void si_clear_saved_cs(struct radeon_saved_cs
*saved
)
90 memset(saved
, 0, sizeof(*saved
));
93 void si_destroy_saved_cs(struct si_saved_cs
*scs
)
95 si_clear_saved_cs(&scs
->gfx
);
96 si_resource_reference(&scs
->trace_buf
, NULL
);
100 static void si_dump_shader(struct si_screen
*sscreen
,
101 enum pipe_shader_type processor
,
102 const struct si_shader
*shader
, FILE *f
)
104 if (shader
->shader_log
)
105 fwrite(shader
->shader_log
, shader
->shader_log_size
, 1, f
);
107 si_shader_dump(sscreen
, shader
, NULL
, processor
, f
, false);
110 struct si_log_chunk_shader
{
111 /* The shader destroy code assumes a current context for unlinking of
114 * While we should be able to destroy shaders without a context, doing
115 * so would happen only very rarely and be therefore likely to fail
116 * just when you're trying to debug something. Let's just remember the
117 * current context in the chunk.
119 struct si_context
*ctx
;
120 struct si_shader
*shader
;
121 enum pipe_shader_type processor
;
123 /* For keep-alive reference counts */
124 struct si_shader_selector
*sel
;
125 struct si_compute
*program
;
129 si_log_chunk_shader_destroy(void *data
)
131 struct si_log_chunk_shader
*chunk
= data
;
132 si_shader_selector_reference(chunk
->ctx
, &chunk
->sel
, NULL
);
133 si_compute_reference(&chunk
->program
, NULL
);
138 si_log_chunk_shader_print(void *data
, FILE *f
)
140 struct si_log_chunk_shader
*chunk
= data
;
141 struct si_screen
*sscreen
= chunk
->ctx
->screen
;
142 si_dump_shader(sscreen
, chunk
->processor
,
146 static struct u_log_chunk_type si_log_chunk_type_shader
= {
147 .destroy
= si_log_chunk_shader_destroy
,
148 .print
= si_log_chunk_shader_print
,
151 static void si_dump_gfx_shader(struct si_context
*ctx
,
152 const struct si_shader_ctx_state
*state
,
153 struct u_log_context
*log
)
155 struct si_shader
*current
= state
->current
;
157 if (!state
->cso
|| !current
)
160 struct si_log_chunk_shader
*chunk
= CALLOC_STRUCT(si_log_chunk_shader
);
162 chunk
->processor
= state
->cso
->info
.processor
;
163 chunk
->shader
= current
;
164 si_shader_selector_reference(ctx
, &chunk
->sel
, current
->selector
);
165 u_log_chunk(log
, &si_log_chunk_type_shader
, chunk
);
168 static void si_dump_compute_shader(struct si_context
*ctx
,
169 struct u_log_context
*log
)
171 const struct si_cs_shader_state
*state
= &ctx
->cs_shader_state
;
176 struct si_log_chunk_shader
*chunk
= CALLOC_STRUCT(si_log_chunk_shader
);
178 chunk
->processor
= PIPE_SHADER_COMPUTE
;
179 chunk
->shader
= &state
->program
->shader
;
180 si_compute_reference(&chunk
->program
, state
->program
);
181 u_log_chunk(log
, &si_log_chunk_type_shader
, chunk
);
185 * Shader compiles can be overridden with arbitrary ELF objects by setting
186 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
188 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
)
190 const char *p
= debug_get_option_replace_shaders();
191 const char *semicolon
;
194 long filesize
, nread
;
196 bool replaced
= false;
204 i
= strtoul(p
, &endp
, 0);
208 fprintf(stderr
, "RADEON_REPLACE_SHADERS formatted badly.\n");
224 semicolon
= strchr(p
, ';');
226 p
= copy
= strndup(p
, semicolon
- p
);
228 fprintf(stderr
, "out of memory\n");
233 fprintf(stderr
, "radeonsi: replace shader %u by %s\n", num
, p
);
237 perror("radeonsi: failed to open file");
241 if (fseek(f
, 0, SEEK_END
) != 0)
248 if (fseek(f
, 0, SEEK_SET
) != 0)
251 buf
= MALLOC(filesize
);
253 fprintf(stderr
, "out of memory\n");
257 nread
= fread(buf
, 1, filesize
, f
);
258 if (nread
!= filesize
)
261 ac_elf_read(buf
, filesize
, binary
);
272 perror("radeonsi: reading shader");
276 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
277 * read them, or use "aha -b -f file" to convert them to html.
279 #define COLOR_RESET "\033[0m"
280 #define COLOR_RED "\033[31m"
281 #define COLOR_GREEN "\033[1;32m"
282 #define COLOR_YELLOW "\033[1;33m"
283 #define COLOR_CYAN "\033[1;36m"
285 static void si_dump_mmapped_reg(struct si_context
*sctx
, FILE *f
,
288 struct radeon_winsys
*ws
= sctx
->ws
;
291 if (ws
->read_registers(ws
, offset
, 1, &value
))
292 ac_dump_reg(f
, sctx
->chip_class
, offset
, value
, ~0);
295 static void si_dump_debug_registers(struct si_context
*sctx
, FILE *f
)
297 if (!sctx
->screen
->info
.has_read_registers_query
)
300 fprintf(f
, "Memory-mapped registers:\n");
301 si_dump_mmapped_reg(sctx
, f
, R_008010_GRBM_STATUS
);
303 /* No other registers can be read on DRM < 3.1.0. */
304 if (sctx
->screen
->info
.drm_major
< 3 ||
305 sctx
->screen
->info
.drm_minor
< 1) {
310 si_dump_mmapped_reg(sctx
, f
, R_008008_GRBM_STATUS2
);
311 si_dump_mmapped_reg(sctx
, f
, R_008014_GRBM_STATUS_SE0
);
312 si_dump_mmapped_reg(sctx
, f
, R_008018_GRBM_STATUS_SE1
);
313 si_dump_mmapped_reg(sctx
, f
, R_008038_GRBM_STATUS_SE2
);
314 si_dump_mmapped_reg(sctx
, f
, R_00803C_GRBM_STATUS_SE3
);
315 si_dump_mmapped_reg(sctx
, f
, R_00D034_SDMA0_STATUS_REG
);
316 si_dump_mmapped_reg(sctx
, f
, R_00D834_SDMA1_STATUS_REG
);
317 if (sctx
->chip_class
<= VI
) {
318 si_dump_mmapped_reg(sctx
, f
, R_000E50_SRBM_STATUS
);
319 si_dump_mmapped_reg(sctx
, f
, R_000E4C_SRBM_STATUS2
);
320 si_dump_mmapped_reg(sctx
, f
, R_000E54_SRBM_STATUS3
);
322 si_dump_mmapped_reg(sctx
, f
, R_008680_CP_STAT
);
323 si_dump_mmapped_reg(sctx
, f
, R_008674_CP_STALLED_STAT1
);
324 si_dump_mmapped_reg(sctx
, f
, R_008678_CP_STALLED_STAT2
);
325 si_dump_mmapped_reg(sctx
, f
, R_008670_CP_STALLED_STAT3
);
326 si_dump_mmapped_reg(sctx
, f
, R_008210_CP_CPC_STATUS
);
327 si_dump_mmapped_reg(sctx
, f
, R_008214_CP_CPC_BUSY_STAT
);
328 si_dump_mmapped_reg(sctx
, f
, R_008218_CP_CPC_STALLED_STAT1
);
329 si_dump_mmapped_reg(sctx
, f
, R_00821C_CP_CPF_STATUS
);
330 si_dump_mmapped_reg(sctx
, f
, R_008220_CP_CPF_BUSY_STAT
);
331 si_dump_mmapped_reg(sctx
, f
, R_008224_CP_CPF_STALLED_STAT1
);
335 struct si_log_chunk_cs
{
336 struct si_context
*ctx
;
337 struct si_saved_cs
*cs
;
339 unsigned gfx_begin
, gfx_end
;
342 static void si_log_chunk_type_cs_destroy(void *data
)
344 struct si_log_chunk_cs
*chunk
= data
;
345 si_saved_cs_reference(&chunk
->cs
, NULL
);
349 static void si_parse_current_ib(FILE *f
, struct radeon_cmdbuf
*cs
,
350 unsigned begin
, unsigned end
,
351 int *last_trace_id
, unsigned trace_id_count
,
352 const char *name
, enum chip_class chip_class
)
354 unsigned orig_end
= end
;
356 assert(begin
<= end
);
358 fprintf(f
, "------------------ %s begin (dw = %u) ------------------\n",
361 for (unsigned prev_idx
= 0; prev_idx
< cs
->num_prev
; ++prev_idx
) {
362 struct radeon_cmdbuf_chunk
*chunk
= &cs
->prev
[prev_idx
];
364 if (begin
< chunk
->cdw
) {
365 ac_parse_ib_chunk(f
, chunk
->buf
+ begin
,
366 MIN2(end
, chunk
->cdw
) - begin
,
367 last_trace_id
, trace_id_count
,
368 chip_class
, NULL
, NULL
);
371 if (end
<= chunk
->cdw
)
374 if (begin
< chunk
->cdw
)
375 fprintf(f
, "\n---------- Next %s Chunk ----------\n\n",
378 begin
-= MIN2(begin
, chunk
->cdw
);
382 assert(end
<= cs
->current
.cdw
);
384 ac_parse_ib_chunk(f
, cs
->current
.buf
+ begin
, end
- begin
, last_trace_id
,
385 trace_id_count
, chip_class
, NULL
, NULL
);
387 fprintf(f
, "------------------- %s end (dw = %u) -------------------\n\n",
391 static void si_log_chunk_type_cs_print(void *data
, FILE *f
)
393 struct si_log_chunk_cs
*chunk
= data
;
394 struct si_context
*ctx
= chunk
->ctx
;
395 struct si_saved_cs
*scs
= chunk
->cs
;
396 int last_trace_id
= -1;
398 /* We are expecting that the ddebug pipe has already
399 * waited for the context, so this buffer should be idle.
400 * If the GPU is hung, there is no point in waiting for it.
402 uint32_t *map
= ctx
->ws
->buffer_map(scs
->trace_buf
->buf
,
404 PIPE_TRANSFER_UNSYNCHRONIZED
|
407 last_trace_id
= map
[0];
409 if (chunk
->gfx_end
!= chunk
->gfx_begin
) {
410 if (chunk
->gfx_begin
== 0) {
411 if (ctx
->init_config
)
412 ac_parse_ib(f
, ctx
->init_config
->pm4
, ctx
->init_config
->ndw
,
413 NULL
, 0, "IB2: Init config", ctx
->chip_class
,
416 if (ctx
->init_config_gs_rings
)
417 ac_parse_ib(f
, ctx
->init_config_gs_rings
->pm4
,
418 ctx
->init_config_gs_rings
->ndw
,
419 NULL
, 0, "IB2: Init GS rings", ctx
->chip_class
,
424 ac_parse_ib(f
, scs
->gfx
.ib
+ chunk
->gfx_begin
,
425 chunk
->gfx_end
- chunk
->gfx_begin
,
426 &last_trace_id
, map
? 1 : 0, "IB", ctx
->chip_class
,
429 si_parse_current_ib(f
, ctx
->gfx_cs
, chunk
->gfx_begin
,
430 chunk
->gfx_end
, &last_trace_id
, map
? 1 : 0,
431 "IB", ctx
->chip_class
);
435 if (chunk
->dump_bo_list
) {
436 fprintf(f
, "Flushing. Time: ");
437 util_dump_ns(f
, scs
->time_flush
);
439 si_dump_bo_list(ctx
, &scs
->gfx
, f
);
443 static const struct u_log_chunk_type si_log_chunk_type_cs
= {
444 .destroy
= si_log_chunk_type_cs_destroy
,
445 .print
= si_log_chunk_type_cs_print
,
448 static void si_log_cs(struct si_context
*ctx
, struct u_log_context
*log
,
451 assert(ctx
->current_saved_cs
);
453 struct si_saved_cs
*scs
= ctx
->current_saved_cs
;
454 unsigned gfx_cur
= ctx
->gfx_cs
->prev_dw
+ ctx
->gfx_cs
->current
.cdw
;
457 gfx_cur
== scs
->gfx_last_dw
)
460 struct si_log_chunk_cs
*chunk
= calloc(1, sizeof(*chunk
));
463 si_saved_cs_reference(&chunk
->cs
, scs
);
464 chunk
->dump_bo_list
= dump_bo_list
;
466 chunk
->gfx_begin
= scs
->gfx_last_dw
;
467 chunk
->gfx_end
= gfx_cur
;
468 scs
->gfx_last_dw
= gfx_cur
;
470 u_log_chunk(log
, &si_log_chunk_type_cs
, chunk
);
473 void si_auto_log_cs(void *data
, struct u_log_context
*log
)
475 struct si_context
*ctx
= (struct si_context
*)data
;
476 si_log_cs(ctx
, log
, false);
479 void si_log_hw_flush(struct si_context
*sctx
)
484 si_log_cs(sctx
, sctx
->log
, true);
487 static const char *priority_to_string(enum radeon_bo_priority priority
)
489 #define ITEM(x) [RADEON_PRIO_##x] = #x
490 static const char *table
[64] = {
493 ITEM(SO_FILLED_SIZE
),
503 ITEM(SAMPLER_BUFFER
),
505 ITEM(SHADER_RW_BUFFER
),
506 ITEM(COMPUTE_GLOBAL
),
507 ITEM(SAMPLER_TEXTURE
),
508 ITEM(SHADER_RW_IMAGE
),
509 ITEM(SAMPLER_TEXTURE_MSAA
),
512 ITEM(COLOR_BUFFER_MSAA
),
513 ITEM(DEPTH_BUFFER_MSAA
),
517 ITEM(SCRATCH_BUFFER
),
521 assert(priority
< ARRAY_SIZE(table
));
522 return table
[priority
];
525 static int bo_list_compare_va(const struct radeon_bo_list_item
*a
,
526 const struct radeon_bo_list_item
*b
)
528 return a
->vm_address
< b
->vm_address
? -1 :
529 a
->vm_address
> b
->vm_address
? 1 : 0;
532 static void si_dump_bo_list(struct si_context
*sctx
,
533 const struct radeon_saved_cs
*saved
, FILE *f
)
540 /* Sort the list according to VM adddresses first. */
541 qsort(saved
->bo_list
, saved
->bo_count
,
542 sizeof(saved
->bo_list
[0]), (void*)bo_list_compare_va
);
544 fprintf(f
, "Buffer list (in units of pages = 4kB):\n"
545 COLOR_YELLOW
" Size VM start page "
546 "VM end page Usage" COLOR_RESET
"\n");
548 for (i
= 0; i
< saved
->bo_count
; i
++) {
549 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
550 const unsigned page_size
= sctx
->screen
->info
.gart_page_size
;
551 uint64_t va
= saved
->bo_list
[i
].vm_address
;
552 uint64_t size
= saved
->bo_list
[i
].bo_size
;
555 /* If there's unused virtual memory between 2 buffers, print it. */
557 uint64_t previous_va_end
= saved
->bo_list
[i
-1].vm_address
+
558 saved
->bo_list
[i
-1].bo_size
;
560 if (va
> previous_va_end
) {
561 fprintf(f
, " %10"PRIu64
" -- hole --\n",
562 (va
- previous_va_end
) / page_size
);
566 /* Print the buffer. */
567 fprintf(f
, " %10"PRIu64
" 0x%013"PRIX64
" 0x%013"PRIX64
" ",
568 size
/ page_size
, va
/ page_size
, (va
+ size
) / page_size
);
570 /* Print the usage. */
571 for (j
= 0; j
< 32; j
++) {
572 if (!(saved
->bo_list
[i
].priority_usage
& (1u << j
)))
575 fprintf(f
, "%s%s", !hit
? "" : ", ", priority_to_string(j
));
580 fprintf(f
, "\nNote: The holes represent memory not used by the IB.\n"
581 " Other buffers can still be allocated there.\n\n");
584 static void si_dump_framebuffer(struct si_context
*sctx
, struct u_log_context
*log
)
586 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
587 struct si_texture
*tex
;
590 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
591 if (!state
->cbufs
[i
])
594 tex
= (struct si_texture
*)state
->cbufs
[i
]->texture
;
595 u_log_printf(log
, COLOR_YELLOW
"Color buffer %i:" COLOR_RESET
"\n", i
);
596 si_print_texture_info(sctx
->screen
, tex
, log
);
597 u_log_printf(log
, "\n");
601 tex
= (struct si_texture
*)state
->zsbuf
->texture
;
602 u_log_printf(log
, COLOR_YELLOW
"Depth-stencil buffer:" COLOR_RESET
"\n");
603 si_print_texture_info(sctx
->screen
, tex
, log
);
604 u_log_printf(log
, "\n");
608 typedef unsigned (*slot_remap_func
)(unsigned);
610 struct si_log_chunk_desc_list
{
611 /** Pointer to memory map of buffer where the list is uploader */
613 /** Reference of buffer where the list is uploaded, so that gpu_list
615 struct si_resource
*buf
;
617 const char *shader_name
;
618 const char *elem_name
;
619 slot_remap_func slot_remap
;
620 enum chip_class chip_class
;
621 unsigned element_dw_size
;
622 unsigned num_elements
;
628 si_log_chunk_desc_list_destroy(void *data
)
630 struct si_log_chunk_desc_list
*chunk
= data
;
631 si_resource_reference(&chunk
->buf
, NULL
);
636 si_log_chunk_desc_list_print(void *data
, FILE *f
)
638 struct si_log_chunk_desc_list
*chunk
= data
;
640 for (unsigned i
= 0; i
< chunk
->num_elements
; i
++) {
641 unsigned cpu_dw_offset
= i
* chunk
->element_dw_size
;
642 unsigned gpu_dw_offset
= chunk
->slot_remap(i
) * chunk
->element_dw_size
;
643 const char *list_note
= chunk
->gpu_list
? "GPU list" : "CPU list";
644 uint32_t *cpu_list
= chunk
->list
+ cpu_dw_offset
;
645 uint32_t *gpu_list
= chunk
->gpu_list
? chunk
->gpu_list
+ gpu_dw_offset
: cpu_list
;
647 fprintf(f
, COLOR_GREEN
"%s%s slot %u (%s):" COLOR_RESET
"\n",
648 chunk
->shader_name
, chunk
->elem_name
, i
, list_note
);
650 switch (chunk
->element_dw_size
) {
652 for (unsigned j
= 0; j
< 4; j
++)
653 ac_dump_reg(f
, chunk
->chip_class
,
654 R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
655 gpu_list
[j
], 0xffffffff);
658 for (unsigned j
= 0; j
< 8; j
++)
659 ac_dump_reg(f
, chunk
->chip_class
,
660 R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
661 gpu_list
[j
], 0xffffffff);
663 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
664 for (unsigned j
= 0; j
< 4; j
++)
665 ac_dump_reg(f
, chunk
->chip_class
,
666 R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
667 gpu_list
[4+j
], 0xffffffff);
670 for (unsigned j
= 0; j
< 8; j
++)
671 ac_dump_reg(f
, chunk
->chip_class
,
672 R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
673 gpu_list
[j
], 0xffffffff);
675 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
676 for (unsigned j
= 0; j
< 4; j
++)
677 ac_dump_reg(f
, chunk
->chip_class
,
678 R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
679 gpu_list
[4+j
], 0xffffffff);
681 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
682 for (unsigned j
= 0; j
< 8; j
++)
683 ac_dump_reg(f
, chunk
->chip_class
,
684 R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
685 gpu_list
[8+j
], 0xffffffff);
687 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
688 for (unsigned j
= 0; j
< 4; j
++)
689 ac_dump_reg(f
, chunk
->chip_class
,
690 R_008F30_SQ_IMG_SAMP_WORD0
+ j
*4,
691 gpu_list
[12+j
], 0xffffffff);
695 if (memcmp(gpu_list
, cpu_list
, chunk
->element_dw_size
* 4) != 0) {
696 fprintf(f
, COLOR_RED
"!!!!! This slot was corrupted in GPU memory !!!!!"
705 static const struct u_log_chunk_type si_log_chunk_type_descriptor_list
= {
706 .destroy
= si_log_chunk_desc_list_destroy
,
707 .print
= si_log_chunk_desc_list_print
,
710 static void si_dump_descriptor_list(struct si_screen
*screen
,
711 struct si_descriptors
*desc
,
712 const char *shader_name
,
713 const char *elem_name
,
714 unsigned element_dw_size
,
715 unsigned num_elements
,
716 slot_remap_func slot_remap
,
717 struct u_log_context
*log
)
722 /* In some cases, the caller doesn't know how many elements are really
723 * uploaded. Reduce num_elements to fit in the range of active slots. */
724 unsigned active_range_dw_begin
=
725 desc
->first_active_slot
* desc
->element_dw_size
;
726 unsigned active_range_dw_end
=
727 active_range_dw_begin
+ desc
->num_active_slots
* desc
->element_dw_size
;
729 while (num_elements
> 0) {
730 int i
= slot_remap(num_elements
- 1);
731 unsigned dw_begin
= i
* element_dw_size
;
732 unsigned dw_end
= dw_begin
+ element_dw_size
;
734 if (dw_begin
>= active_range_dw_begin
&& dw_end
<= active_range_dw_end
)
740 struct si_log_chunk_desc_list
*chunk
=
741 CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list
,
742 4 * element_dw_size
* num_elements
);
743 chunk
->shader_name
= shader_name
;
744 chunk
->elem_name
= elem_name
;
745 chunk
->element_dw_size
= element_dw_size
;
746 chunk
->num_elements
= num_elements
;
747 chunk
->slot_remap
= slot_remap
;
748 chunk
->chip_class
= screen
->info
.chip_class
;
750 si_resource_reference(&chunk
->buf
, desc
->buffer
);
751 chunk
->gpu_list
= desc
->gpu_list
;
753 for (unsigned i
= 0; i
< num_elements
; ++i
) {
754 memcpy(&chunk
->list
[i
* element_dw_size
],
755 &desc
->list
[slot_remap(i
) * element_dw_size
],
756 4 * element_dw_size
);
759 u_log_chunk(log
, &si_log_chunk_type_descriptor_list
, chunk
);
762 static unsigned si_identity(unsigned slot
)
767 static void si_dump_descriptors(struct si_context
*sctx
,
768 enum pipe_shader_type processor
,
769 const struct tgsi_shader_info
*info
,
770 struct u_log_context
*log
)
772 struct si_descriptors
*descs
=
773 &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
+
774 processor
* SI_NUM_SHADER_DESCS
];
775 static const char *shader_name
[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
776 const char *name
= shader_name
[processor
];
777 unsigned enabled_constbuf
, enabled_shaderbuf
, enabled_samplers
;
778 unsigned enabled_images
;
781 enabled_constbuf
= info
->const_buffers_declared
;
782 enabled_shaderbuf
= info
->shader_buffers_declared
;
783 enabled_samplers
= info
->samplers_declared
;
784 enabled_images
= info
->images_declared
;
786 enabled_constbuf
= sctx
->const_and_shader_buffers
[processor
].enabled_mask
>>
787 SI_NUM_SHADER_BUFFERS
;
788 enabled_shaderbuf
= sctx
->const_and_shader_buffers
[processor
].enabled_mask
&
789 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
);
790 enabled_shaderbuf
= util_bitreverse(enabled_shaderbuf
) >>
791 (32 - SI_NUM_SHADER_BUFFERS
);
792 enabled_samplers
= sctx
->samplers
[processor
].enabled_mask
;
793 enabled_images
= sctx
->images
[processor
].enabled_mask
;
796 if (processor
== PIPE_SHADER_VERTEX
&&
797 sctx
->vb_descriptors_buffer
&&
798 sctx
->vb_descriptors_gpu_list
&&
799 sctx
->vertex_elements
) {
800 assert(info
); /* only CS may not have an info struct */
801 struct si_descriptors desc
= {};
803 desc
.buffer
= sctx
->vb_descriptors_buffer
;
804 desc
.list
= sctx
->vb_descriptors_gpu_list
;
805 desc
.gpu_list
= sctx
->vb_descriptors_gpu_list
;
806 desc
.element_dw_size
= 4;
807 desc
.num_active_slots
= sctx
->vertex_elements
->desc_list_byte_size
/ 16;
809 si_dump_descriptor_list(sctx
->screen
, &desc
, name
,
810 " - Vertex buffer", 4, info
->num_inputs
,
814 si_dump_descriptor_list(sctx
->screen
,
815 &descs
[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
],
816 name
, " - Constant buffer", 4,
817 util_last_bit(enabled_constbuf
),
818 si_get_constbuf_slot
, log
);
819 si_dump_descriptor_list(sctx
->screen
,
820 &descs
[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
],
821 name
, " - Shader buffer", 4,
822 util_last_bit(enabled_shaderbuf
),
823 si_get_shaderbuf_slot
, log
);
824 si_dump_descriptor_list(sctx
->screen
,
825 &descs
[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
],
826 name
, " - Sampler", 16,
827 util_last_bit(enabled_samplers
),
828 si_get_sampler_slot
, log
);
829 si_dump_descriptor_list(sctx
->screen
,
830 &descs
[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
],
832 util_last_bit(enabled_images
),
833 si_get_image_slot
, log
);
836 static void si_dump_gfx_descriptors(struct si_context
*sctx
,
837 const struct si_shader_ctx_state
*state
,
838 struct u_log_context
*log
)
840 if (!state
->cso
|| !state
->current
)
843 si_dump_descriptors(sctx
, state
->cso
->type
, &state
->cso
->info
, log
);
846 static void si_dump_compute_descriptors(struct si_context
*sctx
,
847 struct u_log_context
*log
)
849 if (!sctx
->cs_shader_state
.program
)
852 si_dump_descriptors(sctx
, PIPE_SHADER_COMPUTE
, NULL
, log
);
855 struct si_shader_inst
{
856 const char *text
; /* start of disassembly for this instruction */
858 unsigned size
; /* instruction size = 4 or 8 */
859 uint64_t addr
; /* instruction address */
863 * Split a disassembly string into instructions and add them to the array
864 * pointed to by \p instructions.
866 * Labels are considered to be part of the following instruction.
868 static void si_add_split_disasm(const char *disasm
,
871 struct si_shader_inst
*instructions
)
873 const char *semicolon
;
875 while ((semicolon
= strchr(disasm
, ';'))) {
876 struct si_shader_inst
*inst
= &instructions
[(*num
)++];
877 const char *end
= util_strchrnul(semicolon
, '\n');
880 inst
->textlen
= end
- disasm
;
883 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
884 inst
->size
= end
- semicolon
> 16 ? 8 : 4;
893 /* If the shader is being executed, print its asm instructions, and annotate
894 * those that are being executed right now with information about waves that
895 * execute them. This is most useful during a GPU hang.
897 static void si_print_annotated_shader(struct si_shader
*shader
,
898 struct ac_wave_info
*waves
,
902 if (!shader
|| !shader
->binary
.disasm_string
)
905 uint64_t start_addr
= shader
->bo
->gpu_address
;
906 uint64_t end_addr
= start_addr
+ shader
->bo
->b
.b
.width0
;
909 /* See if any wave executes the shader. */
910 for (i
= 0; i
< num_waves
; i
++) {
911 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
915 return; /* the shader is not being executed */
917 /* Remember the first found wave. The waves are sorted according to PC. */
921 /* Get the list of instructions.
922 * Buffer size / 4 is the upper bound of the instruction count.
924 unsigned num_inst
= 0;
925 uint64_t inst_addr
= start_addr
;
926 struct si_shader_inst
*instructions
=
927 calloc(shader
->bo
->b
.b
.width0
/ 4, sizeof(struct si_shader_inst
));
929 if (shader
->prolog
) {
930 si_add_split_disasm(shader
->prolog
->binary
.disasm_string
,
931 &inst_addr
, &num_inst
, instructions
);
933 if (shader
->previous_stage
) {
934 si_add_split_disasm(shader
->previous_stage
->binary
.disasm_string
,
935 &inst_addr
, &num_inst
, instructions
);
937 if (shader
->prolog2
) {
938 si_add_split_disasm(shader
->prolog2
->binary
.disasm_string
,
939 &inst_addr
, &num_inst
, instructions
);
941 si_add_split_disasm(shader
->binary
.disasm_string
,
942 &inst_addr
, &num_inst
, instructions
);
943 if (shader
->epilog
) {
944 si_add_split_disasm(shader
->epilog
->binary
.disasm_string
,
945 &inst_addr
, &num_inst
, instructions
);
948 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
949 si_get_shader_name(shader
, shader
->selector
->type
));
951 /* Print instructions with annotations. */
952 for (i
= 0; i
< num_inst
; i
++) {
953 struct si_shader_inst
*inst
= &instructions
[i
];
955 fprintf(f
, "%.*s [PC=0x%"PRIx64
", size=%u]\n",
956 inst
->textlen
, inst
->text
, inst
->addr
, inst
->size
);
958 /* Print which waves execute the instruction right now. */
959 while (num_waves
&& inst
->addr
== waves
->pc
) {
961 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
962 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
963 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
964 waves
->wave
, waves
->exec
);
966 if (inst
->size
== 4) {
967 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
970 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
971 waves
->inst_dw0
, waves
->inst_dw1
);
974 waves
->matched
= true;
984 static void si_dump_annotated_shaders(struct si_context
*sctx
, FILE *f
)
986 struct ac_wave_info waves
[AC_MAX_WAVES_PER_CHIP
];
987 unsigned num_waves
= ac_get_wave_info(waves
);
989 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
992 si_print_annotated_shader(sctx
->vs_shader
.current
, waves
, num_waves
, f
);
993 si_print_annotated_shader(sctx
->tcs_shader
.current
, waves
, num_waves
, f
);
994 si_print_annotated_shader(sctx
->tes_shader
.current
, waves
, num_waves
, f
);
995 si_print_annotated_shader(sctx
->gs_shader
.current
, waves
, num_waves
, f
);
996 si_print_annotated_shader(sctx
->ps_shader
.current
, waves
, num_waves
, f
);
998 /* Print waves executing shaders that are not currently bound. */
1001 for (i
= 0; i
< num_waves
; i
++) {
1002 if (waves
[i
].matched
)
1006 fprintf(f
, COLOR_CYAN
1007 "Waves not executing currently-bound shaders:"
1011 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
1012 " INST=%08X %08X PC=%"PRIx64
"\n",
1013 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
1014 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
1015 waves
[i
].inst_dw1
, waves
[i
].pc
);
1021 static void si_dump_command(const char *title
, const char *command
, FILE *f
)
1025 FILE *p
= popen(command
, "r");
1029 fprintf(f
, COLOR_YELLOW
"%s: " COLOR_RESET
"\n", title
);
1030 while (fgets(line
, sizeof(line
), p
))
1036 static void si_dump_debug_state(struct pipe_context
*ctx
, FILE *f
,
1039 struct si_context
*sctx
= (struct si_context
*)ctx
;
1042 u_log_flush(sctx
->log
);
1044 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
) {
1045 si_dump_debug_registers(sctx
, f
);
1047 si_dump_annotated_shaders(sctx
, f
);
1048 si_dump_command("Active waves (raw data)", "umr -O halt_waves -wa | column -t", f
);
1049 si_dump_command("Wave information", "umr -O halt_waves,bits -wa", f
);
1053 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
)
1055 struct si_shader_ctx_state
*tcs_shader
;
1060 tcs_shader
= &sctx
->tcs_shader
;
1061 if (sctx
->tes_shader
.cso
&& !sctx
->tcs_shader
.cso
)
1062 tcs_shader
= &sctx
->fixed_func_tcs_shader
;
1064 si_dump_framebuffer(sctx
, log
);
1066 si_dump_gfx_shader(sctx
, &sctx
->vs_shader
, log
);
1067 si_dump_gfx_shader(sctx
, tcs_shader
, log
);
1068 si_dump_gfx_shader(sctx
, &sctx
->tes_shader
, log
);
1069 si_dump_gfx_shader(sctx
, &sctx
->gs_shader
, log
);
1070 si_dump_gfx_shader(sctx
, &sctx
->ps_shader
, log
);
1072 si_dump_descriptor_list(sctx
->screen
,
1073 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
1074 "", "RW buffers", 4,
1075 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
,
1077 si_dump_gfx_descriptors(sctx
, &sctx
->vs_shader
, log
);
1078 si_dump_gfx_descriptors(sctx
, tcs_shader
, log
);
1079 si_dump_gfx_descriptors(sctx
, &sctx
->tes_shader
, log
);
1080 si_dump_gfx_descriptors(sctx
, &sctx
->gs_shader
, log
);
1081 si_dump_gfx_descriptors(sctx
, &sctx
->ps_shader
, log
);
1084 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
)
1089 si_dump_compute_shader(sctx
, log
);
1090 si_dump_compute_descriptors(sctx
, log
);
1093 static void si_dump_dma(struct si_context
*sctx
,
1094 struct radeon_saved_cs
*saved
, FILE *f
)
1096 static const char ib_name
[] = "sDMA IB";
1099 si_dump_bo_list(sctx
, saved
, f
);
1101 fprintf(f
, "------------------ %s begin ------------------\n", ib_name
);
1103 for (i
= 0; i
< saved
->num_dw
; ++i
) {
1104 fprintf(f
, " %08x\n", saved
->ib
[i
]);
1107 fprintf(f
, "------------------- %s end -------------------\n", ib_name
);
1110 fprintf(f
, "SDMA Dump Done.\n");
1113 void si_check_vm_faults(struct si_context
*sctx
,
1114 struct radeon_saved_cs
*saved
, enum ring_type ring
)
1116 struct pipe_screen
*screen
= sctx
->b
.screen
;
1119 char cmd_line
[4096];
1121 if (!ac_vm_fault_occured(sctx
->chip_class
,
1122 &sctx
->dmesg_timestamp
, &addr
))
1125 f
= dd_get_debug_file(false);
1129 fprintf(f
, "VM fault report.\n\n");
1130 if (os_get_command_line(cmd_line
, sizeof(cmd_line
)))
1131 fprintf(f
, "Command: %s\n", cmd_line
);
1132 fprintf(f
, "Driver vendor: %s\n", screen
->get_vendor(screen
));
1133 fprintf(f
, "Device vendor: %s\n", screen
->get_device_vendor(screen
));
1134 fprintf(f
, "Device name: %s\n\n", screen
->get_name(screen
));
1135 fprintf(f
, "Failing VM page: 0x%08"PRIx64
"\n\n", addr
);
1137 if (sctx
->apitrace_call_number
)
1138 fprintf(f
, "Last apitrace call: %u\n\n",
1139 sctx
->apitrace_call_number
);
1143 struct u_log_context log
;
1144 u_log_context_init(&log
);
1146 si_log_draw_state(sctx
, &log
);
1147 si_log_compute_state(sctx
, &log
);
1148 si_log_cs(sctx
, &log
, true);
1150 u_log_new_page_print(&log
, f
);
1151 u_log_context_destroy(&log
);
1155 si_dump_dma(sctx
, saved
, f
);
1164 fprintf(stderr
, "Detected a VM fault, exiting...\n");
1168 void si_init_debug_functions(struct si_context
*sctx
)
1170 sctx
->b
.dump_debug_state
= si_dump_debug_state
;
1172 /* Set the initial dmesg timestamp for this context, so that
1173 * only new messages will be checked for VM faults.
1175 if (sctx
->screen
->debug_flags
& DBG(CHECK_VM
))
1176 ac_vm_fault_occured(sctx
->chip_class
,
1177 &sctx
->dmesg_timestamp
, NULL
);