2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <maraeo@gmail.com>
28 #include "si_shader.h"
30 #include "sid_tables.h"
31 #include "radeon/radeon_elf_util.h"
32 #include "ddebug/dd_util.h"
33 #include "util/u_memory.h"
35 DEBUG_GET_ONCE_OPTION(replace_shaders
, "RADEON_REPLACE_SHADERS", NULL
)
37 static void si_dump_shader(struct si_screen
*sscreen
,
38 struct si_shader_ctx_state
*state
, FILE *f
)
40 if (!state
->cso
|| !state
->current
)
43 si_dump_shader_key(state
->cso
->type
, &state
->current
->key
, f
);
44 si_shader_dump(sscreen
, state
->current
, NULL
,
45 state
->cso
->info
.processor
, f
);
49 * Shader compiles can be overridden with arbitrary ELF objects by setting
50 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
52 bool si_replace_shader(unsigned num
, struct radeon_shader_binary
*binary
)
54 const char *p
= debug_get_option_replace_shaders();
55 const char *semicolon
;
60 bool replaced
= false;
68 i
= strtoul(p
, &endp
, 0);
72 fprintf(stderr
, "RADEON_REPLACE_SHADERS formatted badly.\n");
88 semicolon
= strchr(p
, ';');
90 p
= copy
= strndup(p
, semicolon
- p
);
92 fprintf(stderr
, "out of memory\n");
97 fprintf(stderr
, "radeonsi: replace shader %u by %s\n", num
, p
);
101 perror("radeonsi: failed to open file");
105 if (fseek(f
, 0, SEEK_END
) != 0)
112 if (fseek(f
, 0, SEEK_SET
) != 0)
115 buf
= MALLOC(filesize
);
117 fprintf(stderr
, "out of memory\n");
121 nread
= fread(buf
, 1, filesize
, f
);
122 if (nread
!= filesize
)
125 radeon_elf_read(buf
, filesize
, binary
);
136 perror("radeonsi: reading shader");
140 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
141 * read them, or use "aha -b -f file" to convert them to html.
143 #define COLOR_RESET "\033[0m"
144 #define COLOR_RED "\033[31m"
145 #define COLOR_GREEN "\033[1;32m"
146 #define COLOR_YELLOW "\033[1;33m"
147 #define COLOR_CYAN "\033[1;36m"
151 static void print_spaces(FILE *f
, unsigned num
)
153 fprintf(f
, "%*s", num
, "");
156 static void print_value(FILE *file
, uint32_t value
, int bits
)
158 /* Guess if it's int or float */
159 if (value
<= (1 << 15)) {
161 fprintf(file
, "%u\n", value
);
163 fprintf(file
, "%u (0x%0*x)\n", value
, bits
/ 4, value
);
165 float f
= uif(value
);
167 if (fabs(f
) < 100000 && f
*10 == floor(f
*10))
168 fprintf(file
, "%.1ff (0x%0*x)\n", f
, bits
/ 4, value
);
170 /* Don't print more leading zeros than there are bits. */
171 fprintf(file
, "0x%0*x\n", bits
/ 4, value
);
175 static void print_named_value(FILE *file
, const char *name
, uint32_t value
,
178 print_spaces(file
, INDENT_PKT
);
179 fprintf(file
, COLOR_YELLOW
"%s" COLOR_RESET
" <- ", name
);
180 print_value(file
, value
, bits
);
183 static void si_dump_reg(FILE *file
, unsigned offset
, uint32_t value
,
188 for (r
= 0; r
< ARRAY_SIZE(sid_reg_table
); r
++) {
189 const struct si_reg
*reg
= &sid_reg_table
[r
];
190 const char *reg_name
= sid_strings
+ reg
->name_offset
;
192 if (reg
->offset
== offset
) {
193 bool first_field
= true;
195 print_spaces(file
, INDENT_PKT
);
196 fprintf(file
, COLOR_YELLOW
"%s" COLOR_RESET
" <- ",
199 if (!reg
->num_fields
) {
200 print_value(file
, value
, 32);
204 for (f
= 0; f
< reg
->num_fields
; f
++) {
205 const struct si_field
*field
= sid_fields_table
+ reg
->fields_offset
+ f
;
206 const int *values_offsets
= sid_strings_offsets
+ field
->values_offset
;
207 uint32_t val
= (value
& field
->mask
) >>
208 (ffs(field
->mask
) - 1);
210 if (!(field
->mask
& field_mask
))
213 /* Indent the field. */
216 INDENT_PKT
+ strlen(reg_name
) + 4);
218 /* Print the field. */
219 fprintf(file
, "%s = ", sid_strings
+ field
->name_offset
);
221 if (val
< field
->num_values
&& values_offsets
[val
] >= 0)
222 fprintf(file
, "%s\n", sid_strings
+ values_offsets
[val
]);
224 print_value(file
, val
,
225 util_bitcount(field
->mask
));
233 fprintf(file
, COLOR_YELLOW
"0x%05x" COLOR_RESET
" = 0x%08x", offset
, value
);
236 static void si_parse_set_reg_packet(FILE *f
, uint32_t *ib
, unsigned count
,
239 unsigned reg
= (ib
[1] << 2) + reg_offset
;
242 for (i
= 0; i
< count
; i
++)
243 si_dump_reg(f
, reg
+ i
*4, ib
[2+i
], ~0);
246 static uint32_t *si_parse_packet3(FILE *f
, uint32_t *ib
, int *num_dw
,
249 unsigned count
= PKT_COUNT_G(ib
[0]);
250 unsigned op
= PKT3_IT_OPCODE_G(ib
[0]);
251 const char *predicate
= PKT3_PREDICATE(ib
[0]) ? "(predicate)" : "";
254 /* Print the name first. */
255 for (i
= 0; i
< ARRAY_SIZE(packet3_table
); i
++)
256 if (packet3_table
[i
].op
== op
)
259 if (i
< ARRAY_SIZE(packet3_table
)) {
260 const char *name
= sid_strings
+ packet3_table
[i
].name_offset
;
262 if (op
== PKT3_SET_CONTEXT_REG
||
263 op
== PKT3_SET_CONFIG_REG
||
264 op
== PKT3_SET_UCONFIG_REG
||
265 op
== PKT3_SET_SH_REG
)
266 fprintf(f
, COLOR_CYAN
"%s%s" COLOR_CYAN
":\n",
269 fprintf(f
, COLOR_GREEN
"%s%s" COLOR_RESET
":\n",
272 fprintf(f
, COLOR_RED
"PKT3_UNKNOWN 0x%x%s" COLOR_RESET
":\n",
275 /* Print the contents. */
277 case PKT3_SET_CONTEXT_REG
:
278 si_parse_set_reg_packet(f
, ib
, count
, SI_CONTEXT_REG_OFFSET
);
280 case PKT3_SET_CONFIG_REG
:
281 si_parse_set_reg_packet(f
, ib
, count
, SI_CONFIG_REG_OFFSET
);
283 case PKT3_SET_UCONFIG_REG
:
284 si_parse_set_reg_packet(f
, ib
, count
, CIK_UCONFIG_REG_OFFSET
);
286 case PKT3_SET_SH_REG
:
287 si_parse_set_reg_packet(f
, ib
, count
, SI_SH_REG_OFFSET
);
289 case PKT3_ACQUIRE_MEM
:
290 si_dump_reg(f
, R_0301F0_CP_COHER_CNTL
, ib
[1], ~0);
291 si_dump_reg(f
, R_0301F4_CP_COHER_SIZE
, ib
[2], ~0);
292 si_dump_reg(f
, R_030230_CP_COHER_SIZE_HI
, ib
[3], ~0);
293 si_dump_reg(f
, R_0301F8_CP_COHER_BASE
, ib
[4], ~0);
294 si_dump_reg(f
, R_0301E4_CP_COHER_BASE_HI
, ib
[5], ~0);
295 print_named_value(f
, "POLL_INTERVAL", ib
[6], 16);
297 case PKT3_SURFACE_SYNC
:
298 si_dump_reg(f
, R_0085F0_CP_COHER_CNTL
, ib
[1], ~0);
299 si_dump_reg(f
, R_0085F4_CP_COHER_SIZE
, ib
[2], ~0);
300 si_dump_reg(f
, R_0085F8_CP_COHER_BASE
, ib
[3], ~0);
301 print_named_value(f
, "POLL_INTERVAL", ib
[4], 16);
303 case PKT3_EVENT_WRITE
:
304 si_dump_reg(f
, R_028A90_VGT_EVENT_INITIATOR
, ib
[1],
305 S_028A90_EVENT_TYPE(~0));
306 print_named_value(f
, "EVENT_INDEX", (ib
[1] >> 8) & 0xf, 4);
307 print_named_value(f
, "INV_L2", (ib
[1] >> 20) & 0x1, 1);
309 print_named_value(f
, "ADDRESS_LO", ib
[2], 32);
310 print_named_value(f
, "ADDRESS_HI", ib
[3], 16);
313 case PKT3_DRAW_INDEX_AUTO
:
314 si_dump_reg(f
, R_030930_VGT_NUM_INDICES
, ib
[1], ~0);
315 si_dump_reg(f
, R_0287F0_VGT_DRAW_INITIATOR
, ib
[2], ~0);
317 case PKT3_DRAW_INDEX_2
:
318 si_dump_reg(f
, R_028A78_VGT_DMA_MAX_SIZE
, ib
[1], ~0);
319 si_dump_reg(f
, R_0287E8_VGT_DMA_BASE
, ib
[2], ~0);
320 si_dump_reg(f
, R_0287E4_VGT_DMA_BASE_HI
, ib
[3], ~0);
321 si_dump_reg(f
, R_030930_VGT_NUM_INDICES
, ib
[4], ~0);
322 si_dump_reg(f
, R_0287F0_VGT_DRAW_INITIATOR
, ib
[5], ~0);
324 case PKT3_INDEX_TYPE
:
325 si_dump_reg(f
, R_028A7C_VGT_DMA_INDEX_TYPE
, ib
[1], ~0);
327 case PKT3_NUM_INSTANCES
:
328 si_dump_reg(f
, R_030934_VGT_NUM_INSTANCES
, ib
[1], ~0);
330 case PKT3_WRITE_DATA
:
331 si_dump_reg(f
, R_370_CONTROL
, ib
[1], ~0);
332 si_dump_reg(f
, R_371_DST_ADDR_LO
, ib
[2], ~0);
333 si_dump_reg(f
, R_372_DST_ADDR_HI
, ib
[3], ~0);
334 for (i
= 2; i
< count
; i
++) {
335 print_spaces(f
, INDENT_PKT
);
336 fprintf(f
, "0x%08x\n", ib
[2+i
]);
340 si_dump_reg(f
, R_410_CP_DMA_WORD0
, ib
[1], ~0);
341 si_dump_reg(f
, R_411_CP_DMA_WORD1
, ib
[2], ~0);
342 si_dump_reg(f
, R_412_CP_DMA_WORD2
, ib
[3], ~0);
343 si_dump_reg(f
, R_413_CP_DMA_WORD3
, ib
[4], ~0);
344 si_dump_reg(f
, R_414_COMMAND
, ib
[5], ~0);
347 si_dump_reg(f
, R_500_DMA_DATA_WORD0
, ib
[1], ~0);
348 si_dump_reg(f
, R_501_SRC_ADDR_LO
, ib
[2], ~0);
349 si_dump_reg(f
, R_502_SRC_ADDR_HI
, ib
[3], ~0);
350 si_dump_reg(f
, R_503_DST_ADDR_LO
, ib
[4], ~0);
351 si_dump_reg(f
, R_504_DST_ADDR_HI
, ib
[5], ~0);
352 si_dump_reg(f
, R_414_COMMAND
, ib
[6], ~0);
354 case PKT3_INDIRECT_BUFFER_SI
:
355 case PKT3_INDIRECT_BUFFER_CONST
:
356 case PKT3_INDIRECT_BUFFER_CIK
:
357 si_dump_reg(f
, R_3F0_IB_BASE_LO
, ib
[1], ~0);
358 si_dump_reg(f
, R_3F1_IB_BASE_HI
, ib
[2], ~0);
359 si_dump_reg(f
, R_3F2_CONTROL
, ib
[3], ~0);
362 if (ib
[0] == 0xffff1000) {
363 count
= -1; /* One dword NOP. */
365 } else if (count
== 0 && SI_IS_TRACE_POINT(ib
[1])) {
366 unsigned packet_id
= SI_GET_TRACE_POINT_ID(ib
[1]);
368 print_spaces(f
, INDENT_PKT
);
369 fprintf(f
, COLOR_RED
"Trace point ID: %u\n", packet_id
);
372 break; /* tracing was disabled */
374 print_spaces(f
, INDENT_PKT
);
375 if (packet_id
< trace_id
)
377 "This trace point was reached by the CP."
379 else if (packet_id
== trace_id
)
381 "!!!!! This is the last trace point that "
382 "was reached by the CP !!!!!"
384 else if (packet_id
+1 == trace_id
)
386 "!!!!! This is the first trace point that "
387 "was NOT been reached by the CP !!!!!"
391 "!!!!! This trace point was NOT reached "
396 /* fall through, print all dwords */
398 for (i
= 0; i
< count
+1; i
++) {
399 print_spaces(f
, INDENT_PKT
);
400 fprintf(f
, "0x%08x\n", ib
[1+i
]);
405 *num_dw
-= count
+ 2;
410 * Parse and print an IB into a file.
414 * \param num_dw size of the IB
415 * \param chip_class chip class
416 * \param trace_id the last trace ID that is known to have been reached
417 * and executed by the CP, typically read from a buffer
419 static void si_parse_ib(FILE *f
, uint32_t *ib
, int num_dw
, int trace_id
,
422 fprintf(f
, "------------------ %s begin ------------------\n", name
);
425 unsigned type
= PKT_TYPE_G(ib
[0]);
429 ib
= si_parse_packet3(f
, ib
, &num_dw
, trace_id
);
433 if (ib
[0] == 0x80000000) {
434 fprintf(f
, COLOR_GREEN
"NOP (type 2)" COLOR_RESET
"\n");
440 fprintf(f
, "Unknown packet type %i\n", type
);
445 fprintf(f
, "------------------- %s end -------------------\n", name
);
447 printf("Packet ends after the end of IB.\n");
453 static void si_dump_mmapped_reg(struct si_context
*sctx
, FILE *f
,
456 struct radeon_winsys
*ws
= sctx
->b
.ws
;
459 if (ws
->read_registers(ws
, offset
, 1, &value
))
460 si_dump_reg(f
, offset
, value
, ~0);
463 static void si_dump_debug_registers(struct si_context
*sctx
, FILE *f
)
465 if (sctx
->screen
->b
.info
.drm_major
== 2 &&
466 sctx
->screen
->b
.info
.drm_minor
< 42)
467 return; /* no radeon support */
469 fprintf(f
, "Memory-mapped registers:\n");
470 si_dump_mmapped_reg(sctx
, f
, R_008010_GRBM_STATUS
);
472 /* No other registers can be read on DRM < 3.1.0. */
473 if (sctx
->screen
->b
.info
.drm_major
< 3 ||
474 sctx
->screen
->b
.info
.drm_minor
< 1) {
479 si_dump_mmapped_reg(sctx
, f
, R_008008_GRBM_STATUS2
);
480 si_dump_mmapped_reg(sctx
, f
, R_008014_GRBM_STATUS_SE0
);
481 si_dump_mmapped_reg(sctx
, f
, R_008018_GRBM_STATUS_SE1
);
482 si_dump_mmapped_reg(sctx
, f
, R_008038_GRBM_STATUS_SE2
);
483 si_dump_mmapped_reg(sctx
, f
, R_00803C_GRBM_STATUS_SE3
);
484 si_dump_mmapped_reg(sctx
, f
, R_00D034_SDMA0_STATUS_REG
);
485 si_dump_mmapped_reg(sctx
, f
, R_00D834_SDMA1_STATUS_REG
);
486 si_dump_mmapped_reg(sctx
, f
, R_000E50_SRBM_STATUS
);
487 si_dump_mmapped_reg(sctx
, f
, R_000E4C_SRBM_STATUS2
);
488 si_dump_mmapped_reg(sctx
, f
, R_000E54_SRBM_STATUS3
);
489 si_dump_mmapped_reg(sctx
, f
, R_008680_CP_STAT
);
490 si_dump_mmapped_reg(sctx
, f
, R_008674_CP_STALLED_STAT1
);
491 si_dump_mmapped_reg(sctx
, f
, R_008678_CP_STALLED_STAT2
);
492 si_dump_mmapped_reg(sctx
, f
, R_008670_CP_STALLED_STAT3
);
493 si_dump_mmapped_reg(sctx
, f
, R_008210_CP_CPC_STATUS
);
494 si_dump_mmapped_reg(sctx
, f
, R_008214_CP_CPC_BUSY_STAT
);
495 si_dump_mmapped_reg(sctx
, f
, R_008218_CP_CPC_STALLED_STAT1
);
496 si_dump_mmapped_reg(sctx
, f
, R_00821C_CP_CPF_STATUS
);
497 si_dump_mmapped_reg(sctx
, f
, R_008220_CP_CPF_BUSY_STAT
);
498 si_dump_mmapped_reg(sctx
, f
, R_008224_CP_CPF_STALLED_STAT1
);
502 static void si_dump_last_ib(struct si_context
*sctx
, FILE *f
)
504 int last_trace_id
= -1;
506 if (!sctx
->last_gfx
.ib
)
509 if (sctx
->last_trace_buf
) {
510 /* We are expecting that the ddebug pipe has already
511 * waited for the context, so this buffer should be idle.
512 * If the GPU is hung, there is no point in waiting for it.
514 uint32_t *map
= sctx
->b
.ws
->buffer_map(sctx
->last_trace_buf
->buf
,
516 PIPE_TRANSFER_UNSYNCHRONIZED
|
519 last_trace_id
= *map
;
522 if (sctx
->init_config
)
523 si_parse_ib(f
, sctx
->init_config
->pm4
, sctx
->init_config
->ndw
,
524 -1, "IB2: Init config");
526 if (sctx
->init_config_gs_rings
)
527 si_parse_ib(f
, sctx
->init_config_gs_rings
->pm4
,
528 sctx
->init_config_gs_rings
->ndw
,
529 -1, "IB2: Init GS rings");
531 si_parse_ib(f
, sctx
->last_gfx
.ib
, sctx
->last_gfx
.num_dw
,
532 last_trace_id
, "IB");
535 static const char *priority_to_string(enum radeon_bo_priority priority
)
537 #define ITEM(x) [RADEON_PRIO_##x] = #x
538 static const char *table
[64] = {
541 ITEM(SO_FILLED_SIZE
),
553 ITEM(INTERNAL_SHADER
),
557 ITEM(SAMPLER_BUFFER
),
559 ITEM(SHADER_RW_BUFFER
),
560 ITEM(RINGS_STREAMOUT
),
561 ITEM(SCRATCH_BUFFER
),
562 ITEM(COMPUTE_GLOBAL
),
563 ITEM(SAMPLER_TEXTURE
),
564 ITEM(SHADER_RW_IMAGE
),
565 ITEM(SAMPLER_TEXTURE_MSAA
),
568 ITEM(COLOR_BUFFER_MSAA
),
569 ITEM(DEPTH_BUFFER_MSAA
),
576 assert(priority
< ARRAY_SIZE(table
));
577 return table
[priority
];
580 static int bo_list_compare_va(const struct radeon_bo_list_item
*a
,
581 const struct radeon_bo_list_item
*b
)
583 return a
->vm_address
< b
->vm_address
? -1 :
584 a
->vm_address
> b
->vm_address
? 1 : 0;
587 static void si_dump_bo_list(struct si_context
*sctx
,
588 const struct radeon_saved_cs
*saved
, FILE *f
)
595 /* Sort the list according to VM adddresses first. */
596 qsort(saved
->bo_list
, saved
->bo_count
,
597 sizeof(saved
->bo_list
[0]), (void*)bo_list_compare_va
);
599 fprintf(f
, "Buffer list (in units of pages = 4kB):\n"
600 COLOR_YELLOW
" Size VM start page "
601 "VM end page Usage" COLOR_RESET
"\n");
603 for (i
= 0; i
< saved
->bo_count
; i
++) {
604 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
605 const unsigned page_size
= sctx
->b
.screen
->info
.gart_page_size
;
606 uint64_t va
= saved
->bo_list
[i
].vm_address
;
607 uint64_t size
= saved
->bo_list
[i
].bo_size
;
610 /* If there's unused virtual memory between 2 buffers, print it. */
612 uint64_t previous_va_end
= saved
->bo_list
[i
-1].vm_address
+
613 saved
->bo_list
[i
-1].bo_size
;
615 if (va
> previous_va_end
) {
616 fprintf(f
, " %10"PRIu64
" -- hole --\n",
617 (va
- previous_va_end
) / page_size
);
621 /* Print the buffer. */
622 fprintf(f
, " %10"PRIu64
" 0x%013"PRIx64
" 0x%013"PRIx64
" ",
623 size
/ page_size
, va
/ page_size
, (va
+ size
) / page_size
);
625 /* Print the usage. */
626 for (j
= 0; j
< 64; j
++) {
627 if (!(saved
->bo_list
[i
].priority_usage
& (1llu << j
)))
630 fprintf(f
, "%s%s", !hit
? "" : ", ", priority_to_string(j
));
635 fprintf(f
, "\nNote: The holes represent memory not used by the IB.\n"
636 " Other buffers can still be allocated there.\n\n");
639 static void si_dump_framebuffer(struct si_context
*sctx
, FILE *f
)
641 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
642 struct r600_texture
*rtex
;
645 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
646 if (!state
->cbufs
[i
])
649 rtex
= (struct r600_texture
*)state
->cbufs
[i
]->texture
;
650 fprintf(f
, COLOR_YELLOW
"Color buffer %i:" COLOR_RESET
"\n", i
);
651 r600_print_texture_info(rtex
, f
);
656 rtex
= (struct r600_texture
*)state
->zsbuf
->texture
;
657 fprintf(f
, COLOR_YELLOW
"Depth-stencil buffer:" COLOR_RESET
"\n");
658 r600_print_texture_info(rtex
, f
);
663 static void si_dump_debug_state(struct pipe_context
*ctx
, FILE *f
,
666 struct si_context
*sctx
= (struct si_context
*)ctx
;
668 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
)
669 si_dump_debug_registers(sctx
, f
);
671 if (flags
& PIPE_DUMP_CURRENT_STATES
)
672 si_dump_framebuffer(sctx
, f
);
674 if (flags
& PIPE_DUMP_CURRENT_SHADERS
) {
675 si_dump_shader(sctx
->screen
, &sctx
->vs_shader
, f
);
676 si_dump_shader(sctx
->screen
, &sctx
->tcs_shader
, f
);
677 si_dump_shader(sctx
->screen
, &sctx
->tes_shader
, f
);
678 si_dump_shader(sctx
->screen
, &sctx
->gs_shader
, f
);
679 si_dump_shader(sctx
->screen
, &sctx
->ps_shader
, f
);
682 if (flags
& PIPE_DUMP_LAST_COMMAND_BUFFER
) {
683 si_dump_bo_list(sctx
, &sctx
->last_gfx
, f
);
684 si_dump_last_ib(sctx
, f
);
686 fprintf(f
, "Done.\n");
689 radeon_clear_saved_cs(&sctx
->last_gfx
);
690 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
694 static void si_dump_dma(struct si_context
*sctx
,
695 struct radeon_saved_cs
*saved
, FILE *f
)
697 static const char ib_name
[] = "sDMA IB";
700 si_dump_bo_list(sctx
, saved
, f
);
702 fprintf(f
, "------------------ %s begin ------------------\n", ib_name
);
704 for (i
= 0; i
< saved
->num_dw
; ++i
) {
705 fprintf(f
, " %08x\n", saved
->ib
[i
]);
708 fprintf(f
, "------------------- %s end -------------------\n", ib_name
);
711 fprintf(f
, "SDMA Dump Done.\n");
714 static bool si_vm_fault_occured(struct si_context
*sctx
, uint32_t *out_addr
)
719 uint64_t timestamp
= 0;
722 FILE *p
= popen("dmesg", "r");
726 while (fgets(line
, sizeof(line
), p
)) {
729 if (!line
[0] || line
[0] == '\n')
732 /* Get the timestamp. */
733 if (sscanf(line
, "[%u.%u]", &sec
, &usec
) != 2) {
734 static bool hit
= false;
736 fprintf(stderr
, "%s: failed to parse line '%s'\n",
742 timestamp
= sec
* 1000000llu + usec
;
744 /* If just updating the timestamp. */
748 /* Process messages only if the timestamp is newer. */
749 if (timestamp
<= sctx
->dmesg_timestamp
)
752 /* Only process the first VM fault. */
756 /* Remove trailing \n */
758 if (len
&& line
[len
-1] == '\n')
761 /* Get the message part. */
762 msg
= strchr(line
, ']');
771 if (strstr(msg
, "GPU fault detected:"))
775 msg
= strstr(msg
, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
777 msg
= strstr(msg
, "0x");
780 if (sscanf(msg
, "%X", out_addr
) == 1)
792 if (timestamp
> sctx
->dmesg_timestamp
)
793 sctx
->dmesg_timestamp
= timestamp
;
797 void si_check_vm_faults(struct r600_common_context
*ctx
,
798 struct radeon_saved_cs
*saved
, enum ring_type ring
)
800 struct si_context
*sctx
= (struct si_context
*)ctx
;
801 struct pipe_screen
*screen
= sctx
->b
.b
.screen
;
805 if (!si_vm_fault_occured(sctx
, &addr
))
808 f
= dd_get_debug_file(false);
812 fprintf(f
, "VM fault report.\n\n");
813 fprintf(f
, "Driver vendor: %s\n", screen
->get_vendor(screen
));
814 fprintf(f
, "Device vendor: %s\n", screen
->get_device_vendor(screen
));
815 fprintf(f
, "Device name: %s\n\n", screen
->get_name(screen
));
816 fprintf(f
, "Failing VM page: 0x%08x\n\n", addr
);
818 if (sctx
->apitrace_call_number
)
819 fprintf(f
, "Last apitrace call: %u\n\n",
820 sctx
->apitrace_call_number
);
824 si_dump_debug_state(&sctx
->b
.b
, f
, 0);
828 si_dump_dma(sctx
, saved
, f
);
837 fprintf(stderr
, "Detected a VM fault, exiting...\n");
841 void si_init_debug_functions(struct si_context
*sctx
)
843 sctx
->b
.b
.dump_debug_state
= si_dump_debug_state
;
844 sctx
->b
.check_vm_faults
= si_check_vm_faults
;
846 /* Set the initial dmesg timestamp for this context, so that
847 * only new messages will be checked for VM faults.
849 if (sctx
->screen
->b
.debug_flags
& DBG_CHECK_VM
)
850 si_vm_fault_occured(sctx
, NULL
);