radeonsi: simplify si_llvm_emit_ddxy
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <maraeo@gmail.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "sid_tables.h"
30 #include "radeon/radeon_elf_util.h"
31 #include "ddebug/dd_util.h"
32 #include "util/u_memory.h"
33
34 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
35
36 static void si_dump_shader(struct si_screen *sscreen,
37 struct si_shader_ctx_state *state, FILE *f)
38 {
39 struct si_shader *current = state->current;
40
41 if (!state->cso || !current)
42 return;
43
44 if (current->shader_log)
45 fwrite(current->shader_log, current->shader_log_size, 1, f);
46 else
47 si_shader_dump(sscreen, state->current, NULL,
48 state->cso->info.processor, f);
49 }
50
51 /**
52 * Shader compiles can be overridden with arbitrary ELF objects by setting
53 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
54 */
55 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary)
56 {
57 const char *p = debug_get_option_replace_shaders();
58 const char *semicolon;
59 char *copy = NULL;
60 FILE *f;
61 long filesize, nread;
62 char *buf = NULL;
63 bool replaced = false;
64
65 if (!p)
66 return false;
67
68 while (*p) {
69 unsigned long i;
70 char *endp;
71 i = strtoul(p, &endp, 0);
72
73 p = endp;
74 if (*p != ':') {
75 fprintf(stderr, "RADEON_REPLACE_SHADERS formatted badly.\n");
76 exit(1);
77 }
78 ++p;
79
80 if (i == num)
81 break;
82
83 p = strchr(p, ';');
84 if (!p)
85 return false;
86 ++p;
87 }
88 if (!*p)
89 return false;
90
91 semicolon = strchr(p, ';');
92 if (semicolon) {
93 p = copy = strndup(p, semicolon - p);
94 if (!copy) {
95 fprintf(stderr, "out of memory\n");
96 return false;
97 }
98 }
99
100 fprintf(stderr, "radeonsi: replace shader %u by %s\n", num, p);
101
102 f = fopen(p, "r");
103 if (!f) {
104 perror("radeonsi: failed to open file");
105 goto out_free;
106 }
107
108 if (fseek(f, 0, SEEK_END) != 0)
109 goto file_error;
110
111 filesize = ftell(f);
112 if (filesize < 0)
113 goto file_error;
114
115 if (fseek(f, 0, SEEK_SET) != 0)
116 goto file_error;
117
118 buf = MALLOC(filesize);
119 if (!buf) {
120 fprintf(stderr, "out of memory\n");
121 goto out_close;
122 }
123
124 nread = fread(buf, 1, filesize, f);
125 if (nread != filesize)
126 goto file_error;
127
128 radeon_elf_read(buf, filesize, binary);
129 replaced = true;
130
131 out_close:
132 fclose(f);
133 out_free:
134 FREE(buf);
135 free(copy);
136 return replaced;
137
138 file_error:
139 perror("radeonsi: reading shader");
140 goto out_close;
141 }
142
143 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
144 * read them, or use "aha -b -f file" to convert them to html.
145 */
146 #define COLOR_RESET "\033[0m"
147 #define COLOR_RED "\033[31m"
148 #define COLOR_GREEN "\033[1;32m"
149 #define COLOR_YELLOW "\033[1;33m"
150 #define COLOR_CYAN "\033[1;36m"
151
152 #define INDENT_PKT 8
153
154 static void print_spaces(FILE *f, unsigned num)
155 {
156 fprintf(f, "%*s", num, "");
157 }
158
159 static void print_value(FILE *file, uint32_t value, int bits)
160 {
161 /* Guess if it's int or float */
162 if (value <= (1 << 15)) {
163 if (value <= 9)
164 fprintf(file, "%u\n", value);
165 else
166 fprintf(file, "%u (0x%0*x)\n", value, bits / 4, value);
167 } else {
168 float f = uif(value);
169
170 if (fabs(f) < 100000 && f*10 == floor(f*10))
171 fprintf(file, "%.1ff (0x%0*x)\n", f, bits / 4, value);
172 else
173 /* Don't print more leading zeros than there are bits. */
174 fprintf(file, "0x%0*x\n", bits / 4, value);
175 }
176 }
177
178 static void print_named_value(FILE *file, const char *name, uint32_t value,
179 int bits)
180 {
181 print_spaces(file, INDENT_PKT);
182 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", name);
183 print_value(file, value, bits);
184 }
185
186 static void si_dump_reg(FILE *file, unsigned offset, uint32_t value,
187 uint32_t field_mask)
188 {
189 int r, f;
190
191 for (r = 0; r < ARRAY_SIZE(sid_reg_table); r++) {
192 const struct si_reg *reg = &sid_reg_table[r];
193 const char *reg_name = sid_strings + reg->name_offset;
194
195 if (reg->offset == offset) {
196 bool first_field = true;
197
198 print_spaces(file, INDENT_PKT);
199 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ",
200 reg_name);
201
202 if (!reg->num_fields) {
203 print_value(file, value, 32);
204 return;
205 }
206
207 for (f = 0; f < reg->num_fields; f++) {
208 const struct si_field *field = sid_fields_table + reg->fields_offset + f;
209 const int *values_offsets = sid_strings_offsets + field->values_offset;
210 uint32_t val = (value & field->mask) >>
211 (ffs(field->mask) - 1);
212
213 if (!(field->mask & field_mask))
214 continue;
215
216 /* Indent the field. */
217 if (!first_field)
218 print_spaces(file,
219 INDENT_PKT + strlen(reg_name) + 4);
220
221 /* Print the field. */
222 fprintf(file, "%s = ", sid_strings + field->name_offset);
223
224 if (val < field->num_values && values_offsets[val] >= 0)
225 fprintf(file, "%s\n", sid_strings + values_offsets[val]);
226 else
227 print_value(file, val,
228 util_bitcount(field->mask));
229
230 first_field = false;
231 }
232 return;
233 }
234 }
235
236 fprintf(file, COLOR_YELLOW "0x%05x" COLOR_RESET " = 0x%08x", offset, value);
237 }
238
239 static void si_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count,
240 unsigned reg_offset)
241 {
242 unsigned reg = (ib[1] << 2) + reg_offset;
243 int i;
244
245 for (i = 0; i < count; i++)
246 si_dump_reg(f, reg + i*4, ib[2+i], ~0);
247 }
248
249 static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
250 int trace_id, enum chip_class chip_class)
251 {
252 unsigned count = PKT_COUNT_G(ib[0]);
253 unsigned op = PKT3_IT_OPCODE_G(ib[0]);
254 const char *predicate = PKT3_PREDICATE(ib[0]) ? "(predicate)" : "";
255 int i;
256
257 /* Print the name first. */
258 for (i = 0; i < ARRAY_SIZE(packet3_table); i++)
259 if (packet3_table[i].op == op)
260 break;
261
262 if (i < ARRAY_SIZE(packet3_table)) {
263 const char *name = sid_strings + packet3_table[i].name_offset;
264
265 if (op == PKT3_SET_CONTEXT_REG ||
266 op == PKT3_SET_CONFIG_REG ||
267 op == PKT3_SET_UCONFIG_REG ||
268 op == PKT3_SET_SH_REG)
269 fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
270 name, predicate);
271 else
272 fprintf(f, COLOR_GREEN "%s%s" COLOR_RESET ":\n",
273 name, predicate);
274 } else
275 fprintf(f, COLOR_RED "PKT3_UNKNOWN 0x%x%s" COLOR_RESET ":\n",
276 op, predicate);
277
278 /* Print the contents. */
279 switch (op) {
280 case PKT3_SET_CONTEXT_REG:
281 si_parse_set_reg_packet(f, ib, count, SI_CONTEXT_REG_OFFSET);
282 break;
283 case PKT3_SET_CONFIG_REG:
284 si_parse_set_reg_packet(f, ib, count, SI_CONFIG_REG_OFFSET);
285 break;
286 case PKT3_SET_UCONFIG_REG:
287 si_parse_set_reg_packet(f, ib, count, CIK_UCONFIG_REG_OFFSET);
288 break;
289 case PKT3_SET_SH_REG:
290 si_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET);
291 break;
292 case PKT3_ACQUIRE_MEM:
293 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
294 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
295 si_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ib[3], ~0);
296 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[4], ~0);
297 si_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ib[5], ~0);
298 print_named_value(f, "POLL_INTERVAL", ib[6], 16);
299 break;
300 case PKT3_SURFACE_SYNC:
301 if (chip_class >= CIK) {
302 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
303 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
304 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[3], ~0);
305 } else {
306 si_dump_reg(f, R_0085F0_CP_COHER_CNTL, ib[1], ~0);
307 si_dump_reg(f, R_0085F4_CP_COHER_SIZE, ib[2], ~0);
308 si_dump_reg(f, R_0085F8_CP_COHER_BASE, ib[3], ~0);
309 }
310 print_named_value(f, "POLL_INTERVAL", ib[4], 16);
311 break;
312 case PKT3_EVENT_WRITE:
313 si_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
314 S_028A90_EVENT_TYPE(~0));
315 print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
316 print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
317 if (count > 0) {
318 print_named_value(f, "ADDRESS_LO", ib[2], 32);
319 print_named_value(f, "ADDRESS_HI", ib[3], 16);
320 }
321 break;
322 case PKT3_DRAW_INDEX_AUTO:
323 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
324 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
325 break;
326 case PKT3_DRAW_INDEX_2:
327 si_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
328 si_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
329 si_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
330 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
331 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
332 break;
333 case PKT3_INDEX_TYPE:
334 si_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ib[1], ~0);
335 break;
336 case PKT3_NUM_INSTANCES:
337 si_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ib[1], ~0);
338 break;
339 case PKT3_WRITE_DATA:
340 si_dump_reg(f, R_370_CONTROL, ib[1], ~0);
341 si_dump_reg(f, R_371_DST_ADDR_LO, ib[2], ~0);
342 si_dump_reg(f, R_372_DST_ADDR_HI, ib[3], ~0);
343 for (i = 2; i < count; i++) {
344 print_spaces(f, INDENT_PKT);
345 fprintf(f, "0x%08x\n", ib[2+i]);
346 }
347 break;
348 case PKT3_CP_DMA:
349 si_dump_reg(f, R_410_CP_DMA_WORD0, ib[1], ~0);
350 si_dump_reg(f, R_411_CP_DMA_WORD1, ib[2], ~0);
351 si_dump_reg(f, R_412_CP_DMA_WORD2, ib[3], ~0);
352 si_dump_reg(f, R_413_CP_DMA_WORD3, ib[4], ~0);
353 si_dump_reg(f, R_414_COMMAND, ib[5], ~0);
354 break;
355 case PKT3_DMA_DATA:
356 si_dump_reg(f, R_500_DMA_DATA_WORD0, ib[1], ~0);
357 si_dump_reg(f, R_501_SRC_ADDR_LO, ib[2], ~0);
358 si_dump_reg(f, R_502_SRC_ADDR_HI, ib[3], ~0);
359 si_dump_reg(f, R_503_DST_ADDR_LO, ib[4], ~0);
360 si_dump_reg(f, R_504_DST_ADDR_HI, ib[5], ~0);
361 si_dump_reg(f, R_414_COMMAND, ib[6], ~0);
362 break;
363 case PKT3_INDIRECT_BUFFER_SI:
364 case PKT3_INDIRECT_BUFFER_CONST:
365 case PKT3_INDIRECT_BUFFER_CIK:
366 si_dump_reg(f, R_3F0_IB_BASE_LO, ib[1], ~0);
367 si_dump_reg(f, R_3F1_IB_BASE_HI, ib[2], ~0);
368 si_dump_reg(f, R_3F2_CONTROL, ib[3], ~0);
369 break;
370 case PKT3_NOP:
371 if (ib[0] == 0xffff1000) {
372 count = -1; /* One dword NOP. */
373 break;
374 } else if (count == 0 && SI_IS_TRACE_POINT(ib[1])) {
375 unsigned packet_id = SI_GET_TRACE_POINT_ID(ib[1]);
376
377 print_spaces(f, INDENT_PKT);
378 fprintf(f, COLOR_RED "Trace point ID: %u\n", packet_id);
379
380 if (trace_id == -1)
381 break; /* tracing was disabled */
382
383 print_spaces(f, INDENT_PKT);
384 if (packet_id < trace_id)
385 fprintf(f, COLOR_RED
386 "This trace point was reached by the CP."
387 COLOR_RESET "\n");
388 else if (packet_id == trace_id)
389 fprintf(f, COLOR_RED
390 "!!!!! This is the last trace point that "
391 "was reached by the CP !!!!!"
392 COLOR_RESET "\n");
393 else if (packet_id+1 == trace_id)
394 fprintf(f, COLOR_RED
395 "!!!!! This is the first trace point that "
396 "was NOT been reached by the CP !!!!!"
397 COLOR_RESET "\n");
398 else
399 fprintf(f, COLOR_RED
400 "!!!!! This trace point was NOT reached "
401 "by the CP !!!!!"
402 COLOR_RESET "\n");
403 break;
404 }
405 /* fall through, print all dwords */
406 default:
407 for (i = 0; i < count+1; i++) {
408 print_spaces(f, INDENT_PKT);
409 fprintf(f, "0x%08x\n", ib[1+i]);
410 }
411 }
412
413 ib += count + 2;
414 *num_dw -= count + 2;
415 return ib;
416 }
417
418 /**
419 * Parse and print an IB into a file.
420 *
421 * \param f file
422 * \param ib IB
423 * \param num_dw size of the IB
424 * \param chip_class chip class
425 * \param trace_id the last trace ID that is known to have been reached
426 * and executed by the CP, typically read from a buffer
427 */
428 static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id,
429 const char *name, enum chip_class chip_class)
430 {
431 fprintf(f, "------------------ %s begin ------------------\n", name);
432
433 while (num_dw > 0) {
434 unsigned type = PKT_TYPE_G(ib[0]);
435
436 switch (type) {
437 case 3:
438 ib = si_parse_packet3(f, ib, &num_dw, trace_id,
439 chip_class);
440 break;
441 case 2:
442 /* type-2 nop */
443 if (ib[0] == 0x80000000) {
444 fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
445 ib++;
446 break;
447 }
448 /* fall through */
449 default:
450 fprintf(f, "Unknown packet type %i\n", type);
451 return;
452 }
453 }
454
455 fprintf(f, "------------------- %s end -------------------\n", name);
456 if (num_dw < 0) {
457 printf("Packet ends after the end of IB.\n");
458 exit(0);
459 }
460 fprintf(f, "\n");
461 }
462
463 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
464 unsigned offset)
465 {
466 struct radeon_winsys *ws = sctx->b.ws;
467 uint32_t value;
468
469 if (ws->read_registers(ws, offset, 1, &value))
470 si_dump_reg(f, offset, value, ~0);
471 }
472
473 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
474 {
475 if (sctx->screen->b.info.drm_major == 2 &&
476 sctx->screen->b.info.drm_minor < 42)
477 return; /* no radeon support */
478
479 fprintf(f, "Memory-mapped registers:\n");
480 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
481
482 /* No other registers can be read on DRM < 3.1.0. */
483 if (sctx->screen->b.info.drm_major < 3 ||
484 sctx->screen->b.info.drm_minor < 1) {
485 fprintf(f, "\n");
486 return;
487 }
488
489 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
490 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
491 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
492 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
493 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
494 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
495 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
496 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
497 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
498 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
499 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
500 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
501 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
502 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
503 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
504 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
505 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
506 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
507 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
508 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
509 fprintf(f, "\n");
510 }
511
512 static void si_dump_last_ib(struct si_context *sctx, FILE *f)
513 {
514 int last_trace_id = -1;
515
516 if (!sctx->last_gfx.ib)
517 return;
518
519 if (sctx->last_trace_buf) {
520 /* We are expecting that the ddebug pipe has already
521 * waited for the context, so this buffer should be idle.
522 * If the GPU is hung, there is no point in waiting for it.
523 */
524 uint32_t *map = sctx->b.ws->buffer_map(sctx->last_trace_buf->buf,
525 NULL,
526 PIPE_TRANSFER_UNSYNCHRONIZED |
527 PIPE_TRANSFER_READ);
528 if (map)
529 last_trace_id = *map;
530 }
531
532 if (sctx->init_config)
533 si_parse_ib(f, sctx->init_config->pm4, sctx->init_config->ndw,
534 -1, "IB2: Init config", sctx->b.chip_class);
535
536 if (sctx->init_config_gs_rings)
537 si_parse_ib(f, sctx->init_config_gs_rings->pm4,
538 sctx->init_config_gs_rings->ndw,
539 -1, "IB2: Init GS rings", sctx->b.chip_class);
540
541 si_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw,
542 last_trace_id, "IB", sctx->b.chip_class);
543 }
544
545 static const char *priority_to_string(enum radeon_bo_priority priority)
546 {
547 #define ITEM(x) [RADEON_PRIO_##x] = #x
548 static const char *table[64] = {
549 ITEM(FENCE),
550 ITEM(TRACE),
551 ITEM(SO_FILLED_SIZE),
552 ITEM(QUERY),
553 ITEM(IB1),
554 ITEM(IB2),
555 ITEM(DRAW_INDIRECT),
556 ITEM(INDEX_BUFFER),
557 ITEM(VCE),
558 ITEM(UVD),
559 ITEM(SDMA_BUFFER),
560 ITEM(SDMA_TEXTURE),
561 ITEM(CP_DMA),
562 ITEM(CONST_BUFFER),
563 ITEM(DESCRIPTORS),
564 ITEM(BORDER_COLORS),
565 ITEM(SAMPLER_BUFFER),
566 ITEM(VERTEX_BUFFER),
567 ITEM(SHADER_RW_BUFFER),
568 ITEM(COMPUTE_GLOBAL),
569 ITEM(SAMPLER_TEXTURE),
570 ITEM(SHADER_RW_IMAGE),
571 ITEM(SAMPLER_TEXTURE_MSAA),
572 ITEM(COLOR_BUFFER),
573 ITEM(DEPTH_BUFFER),
574 ITEM(COLOR_BUFFER_MSAA),
575 ITEM(DEPTH_BUFFER_MSAA),
576 ITEM(CMASK),
577 ITEM(DCC),
578 ITEM(HTILE),
579 ITEM(SHADER_BINARY),
580 ITEM(SHADER_RINGS),
581 ITEM(SCRATCH_BUFFER),
582 };
583 #undef ITEM
584
585 assert(priority < ARRAY_SIZE(table));
586 return table[priority];
587 }
588
589 static int bo_list_compare_va(const struct radeon_bo_list_item *a,
590 const struct radeon_bo_list_item *b)
591 {
592 return a->vm_address < b->vm_address ? -1 :
593 a->vm_address > b->vm_address ? 1 : 0;
594 }
595
596 static void si_dump_bo_list(struct si_context *sctx,
597 const struct radeon_saved_cs *saved, FILE *f)
598 {
599 unsigned i,j;
600
601 if (!saved->bo_list)
602 return;
603
604 /* Sort the list according to VM adddresses first. */
605 qsort(saved->bo_list, saved->bo_count,
606 sizeof(saved->bo_list[0]), (void*)bo_list_compare_va);
607
608 fprintf(f, "Buffer list (in units of pages = 4kB):\n"
609 COLOR_YELLOW " Size VM start page "
610 "VM end page Usage" COLOR_RESET "\n");
611
612 for (i = 0; i < saved->bo_count; i++) {
613 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
614 const unsigned page_size = sctx->b.screen->info.gart_page_size;
615 uint64_t va = saved->bo_list[i].vm_address;
616 uint64_t size = saved->bo_list[i].bo_size;
617 bool hit = false;
618
619 /* If there's unused virtual memory between 2 buffers, print it. */
620 if (i) {
621 uint64_t previous_va_end = saved->bo_list[i-1].vm_address +
622 saved->bo_list[i-1].bo_size;
623
624 if (va > previous_va_end) {
625 fprintf(f, " %10"PRIu64" -- hole --\n",
626 (va - previous_va_end) / page_size);
627 }
628 }
629
630 /* Print the buffer. */
631 fprintf(f, " %10"PRIu64" 0x%013"PRIx64" 0x%013"PRIx64" ",
632 size / page_size, va / page_size, (va + size) / page_size);
633
634 /* Print the usage. */
635 for (j = 0; j < 64; j++) {
636 if (!(saved->bo_list[i].priority_usage & (1llu << j)))
637 continue;
638
639 fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
640 hit = true;
641 }
642 fprintf(f, "\n");
643 }
644 fprintf(f, "\nNote: The holes represent memory not used by the IB.\n"
645 " Other buffers can still be allocated there.\n\n");
646 }
647
648 static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
649 {
650 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
651 struct r600_texture *rtex;
652 int i;
653
654 for (i = 0; i < state->nr_cbufs; i++) {
655 if (!state->cbufs[i])
656 continue;
657
658 rtex = (struct r600_texture*)state->cbufs[i]->texture;
659 fprintf(f, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
660 r600_print_texture_info(rtex, f);
661 fprintf(f, "\n");
662 }
663
664 if (state->zsbuf) {
665 rtex = (struct r600_texture*)state->zsbuf->texture;
666 fprintf(f, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
667 r600_print_texture_info(rtex, f);
668 fprintf(f, "\n");
669 }
670 }
671
672 static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
673 unsigned flags)
674 {
675 struct si_context *sctx = (struct si_context*)ctx;
676
677 if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS)
678 si_dump_debug_registers(sctx, f);
679
680 if (flags & PIPE_DUMP_CURRENT_STATES)
681 si_dump_framebuffer(sctx, f);
682
683 if (flags & PIPE_DUMP_CURRENT_SHADERS) {
684 si_dump_shader(sctx->screen, &sctx->vs_shader, f);
685 si_dump_shader(sctx->screen, &sctx->tcs_shader, f);
686 si_dump_shader(sctx->screen, &sctx->tes_shader, f);
687 si_dump_shader(sctx->screen, &sctx->gs_shader, f);
688 si_dump_shader(sctx->screen, &sctx->ps_shader, f);
689 }
690
691 if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
692 si_dump_bo_list(sctx, &sctx->last_gfx, f);
693 si_dump_last_ib(sctx, f);
694
695 fprintf(f, "Done.\n");
696
697 /* dump only once */
698 radeon_clear_saved_cs(&sctx->last_gfx);
699 r600_resource_reference(&sctx->last_trace_buf, NULL);
700 }
701 }
702
703 static void si_dump_dma(struct si_context *sctx,
704 struct radeon_saved_cs *saved, FILE *f)
705 {
706 static const char ib_name[] = "sDMA IB";
707 unsigned i;
708
709 si_dump_bo_list(sctx, saved, f);
710
711 fprintf(f, "------------------ %s begin ------------------\n", ib_name);
712
713 for (i = 0; i < saved->num_dw; ++i) {
714 fprintf(f, " %08x\n", saved->ib[i]);
715 }
716
717 fprintf(f, "------------------- %s end -------------------\n", ib_name);
718 fprintf(f, "\n");
719
720 fprintf(f, "SDMA Dump Done.\n");
721 }
722
723 static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
724 {
725 char line[2000];
726 unsigned sec, usec;
727 int progress = 0;
728 uint64_t timestamp = 0;
729 bool fault = false;
730
731 FILE *p = popen("dmesg", "r");
732 if (!p)
733 return false;
734
735 while (fgets(line, sizeof(line), p)) {
736 char *msg, len;
737
738 if (!line[0] || line[0] == '\n')
739 continue;
740
741 /* Get the timestamp. */
742 if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
743 static bool hit = false;
744 if (!hit) {
745 fprintf(stderr, "%s: failed to parse line '%s'\n",
746 __func__, line);
747 hit = true;
748 }
749 continue;
750 }
751 timestamp = sec * 1000000llu + usec;
752
753 /* If just updating the timestamp. */
754 if (!out_addr)
755 continue;
756
757 /* Process messages only if the timestamp is newer. */
758 if (timestamp <= sctx->dmesg_timestamp)
759 continue;
760
761 /* Only process the first VM fault. */
762 if (fault)
763 continue;
764
765 /* Remove trailing \n */
766 len = strlen(line);
767 if (len && line[len-1] == '\n')
768 line[len-1] = 0;
769
770 /* Get the message part. */
771 msg = strchr(line, ']');
772 if (!msg) {
773 assert(0);
774 continue;
775 }
776 msg++;
777
778 switch (progress) {
779 case 0:
780 if (strstr(msg, "GPU fault detected:"))
781 progress = 1;
782 break;
783 case 1:
784 msg = strstr(msg, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
785 if (msg) {
786 msg = strstr(msg, "0x");
787 if (msg) {
788 msg += 2;
789 if (sscanf(msg, "%X", out_addr) == 1)
790 fault = true;
791 }
792 }
793 progress = 0;
794 break;
795 default:
796 progress = 0;
797 }
798 }
799 pclose(p);
800
801 if (timestamp > sctx->dmesg_timestamp)
802 sctx->dmesg_timestamp = timestamp;
803 return fault;
804 }
805
806 void si_check_vm_faults(struct r600_common_context *ctx,
807 struct radeon_saved_cs *saved, enum ring_type ring)
808 {
809 struct si_context *sctx = (struct si_context *)ctx;
810 struct pipe_screen *screen = sctx->b.b.screen;
811 FILE *f;
812 uint32_t addr;
813 char cmd_line[4096];
814
815 if (!si_vm_fault_occured(sctx, &addr))
816 return;
817
818 f = dd_get_debug_file(false);
819 if (!f)
820 return;
821
822 fprintf(f, "VM fault report.\n\n");
823 if (os_get_command_line(cmd_line, sizeof(cmd_line)))
824 fprintf(f, "Command: %s\n", cmd_line);
825 fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen));
826 fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen));
827 fprintf(f, "Device name: %s\n\n", screen->get_name(screen));
828 fprintf(f, "Failing VM page: 0x%08x\n\n", addr);
829
830 if (sctx->apitrace_call_number)
831 fprintf(f, "Last apitrace call: %u\n\n",
832 sctx->apitrace_call_number);
833
834 switch (ring) {
835 case RING_GFX:
836 si_dump_debug_state(&sctx->b.b, f,
837 PIPE_DUMP_CURRENT_STATES |
838 PIPE_DUMP_CURRENT_SHADERS |
839 PIPE_DUMP_LAST_COMMAND_BUFFER);
840 break;
841
842 case RING_DMA:
843 si_dump_dma(sctx, saved, f);
844 break;
845
846 default:
847 break;
848 }
849
850 fclose(f);
851
852 fprintf(stderr, "Detected a VM fault, exiting...\n");
853 exit(0);
854 }
855
856 void si_init_debug_functions(struct si_context *sctx)
857 {
858 sctx->b.b.dump_debug_state = si_dump_debug_state;
859 sctx->b.check_vm_faults = si_check_vm_faults;
860
861 /* Set the initial dmesg timestamp for this context, so that
862 * only new messages will be checked for VM faults.
863 */
864 if (sctx->screen->b.debug_flags & DBG_CHECK_VM)
865 si_vm_fault_occured(sctx, NULL);
866 }