2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <maraeo@gmail.com>
29 #include "sid_tables.h"
30 #include "radeon/radeon_elf_util.h"
31 #include "ddebug/dd_util.h"
32 #include "util/u_memory.h"
34 DEBUG_GET_ONCE_OPTION(replace_shaders
, "RADEON_REPLACE_SHADERS", NULL
)
36 static void si_dump_shader(struct si_screen
*sscreen
,
37 struct si_shader_ctx_state
*state
, FILE *f
)
39 struct si_shader
*current
= state
->current
;
41 if (!state
->cso
|| !current
)
44 if (current
->shader_log
)
45 fwrite(current
->shader_log
, current
->shader_log_size
, 1, f
);
47 si_shader_dump(sscreen
, state
->current
, NULL
,
48 state
->cso
->info
.processor
, f
, false);
52 * Shader compiles can be overridden with arbitrary ELF objects by setting
53 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
55 bool si_replace_shader(unsigned num
, struct radeon_shader_binary
*binary
)
57 const char *p
= debug_get_option_replace_shaders();
58 const char *semicolon
;
63 bool replaced
= false;
71 i
= strtoul(p
, &endp
, 0);
75 fprintf(stderr
, "RADEON_REPLACE_SHADERS formatted badly.\n");
91 semicolon
= strchr(p
, ';');
93 p
= copy
= strndup(p
, semicolon
- p
);
95 fprintf(stderr
, "out of memory\n");
100 fprintf(stderr
, "radeonsi: replace shader %u by %s\n", num
, p
);
104 perror("radeonsi: failed to open file");
108 if (fseek(f
, 0, SEEK_END
) != 0)
115 if (fseek(f
, 0, SEEK_SET
) != 0)
118 buf
= MALLOC(filesize
);
120 fprintf(stderr
, "out of memory\n");
124 nread
= fread(buf
, 1, filesize
, f
);
125 if (nread
!= filesize
)
128 radeon_elf_read(buf
, filesize
, binary
);
139 perror("radeonsi: reading shader");
143 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
144 * read them, or use "aha -b -f file" to convert them to html.
146 #define COLOR_RESET "\033[0m"
147 #define COLOR_RED "\033[31m"
148 #define COLOR_GREEN "\033[1;32m"
149 #define COLOR_YELLOW "\033[1;33m"
150 #define COLOR_CYAN "\033[1;36m"
154 static void print_spaces(FILE *f
, unsigned num
)
156 fprintf(f
, "%*s", num
, "");
159 static void print_value(FILE *file
, uint32_t value
, int bits
)
161 /* Guess if it's int or float */
162 if (value
<= (1 << 15)) {
164 fprintf(file
, "%u\n", value
);
166 fprintf(file
, "%u (0x%0*x)\n", value
, bits
/ 4, value
);
168 float f
= uif(value
);
170 if (fabs(f
) < 100000 && f
*10 == floor(f
*10))
171 fprintf(file
, "%.1ff (0x%0*x)\n", f
, bits
/ 4, value
);
173 /* Don't print more leading zeros than there are bits. */
174 fprintf(file
, "0x%0*x\n", bits
/ 4, value
);
178 static void print_named_value(FILE *file
, const char *name
, uint32_t value
,
181 print_spaces(file
, INDENT_PKT
);
182 fprintf(file
, COLOR_YELLOW
"%s" COLOR_RESET
" <- ", name
);
183 print_value(file
, value
, bits
);
186 static void si_dump_reg(FILE *file
, unsigned offset
, uint32_t value
,
191 for (r
= 0; r
< ARRAY_SIZE(sid_reg_table
); r
++) {
192 const struct si_reg
*reg
= &sid_reg_table
[r
];
193 const char *reg_name
= sid_strings
+ reg
->name_offset
;
195 if (reg
->offset
== offset
) {
196 bool first_field
= true;
198 print_spaces(file
, INDENT_PKT
);
199 fprintf(file
, COLOR_YELLOW
"%s" COLOR_RESET
" <- ",
202 if (!reg
->num_fields
) {
203 print_value(file
, value
, 32);
207 for (f
= 0; f
< reg
->num_fields
; f
++) {
208 const struct si_field
*field
= sid_fields_table
+ reg
->fields_offset
+ f
;
209 const int *values_offsets
= sid_strings_offsets
+ field
->values_offset
;
210 uint32_t val
= (value
& field
->mask
) >>
211 (ffs(field
->mask
) - 1);
213 if (!(field
->mask
& field_mask
))
216 /* Indent the field. */
219 INDENT_PKT
+ strlen(reg_name
) + 4);
221 /* Print the field. */
222 fprintf(file
, "%s = ", sid_strings
+ field
->name_offset
);
224 if (val
< field
->num_values
&& values_offsets
[val
] >= 0)
225 fprintf(file
, "%s\n", sid_strings
+ values_offsets
[val
]);
227 print_value(file
, val
,
228 util_bitcount(field
->mask
));
236 print_spaces(file
, INDENT_PKT
);
237 fprintf(file
, COLOR_YELLOW
"0x%05x" COLOR_RESET
" <- 0x%08x\n", offset
, value
);
240 static void si_parse_set_reg_packet(FILE *f
, uint32_t *ib
, unsigned count
,
243 unsigned reg
= (ib
[1] << 2) + reg_offset
;
246 for (i
= 0; i
< count
; i
++)
247 si_dump_reg(f
, reg
+ i
*4, ib
[2+i
], ~0);
250 static uint32_t *si_parse_packet3(FILE *f
, uint32_t *ib
, int *num_dw
,
251 int trace_id
, enum chip_class chip_class
)
253 unsigned count
= PKT_COUNT_G(ib
[0]);
254 unsigned op
= PKT3_IT_OPCODE_G(ib
[0]);
255 const char *predicate
= PKT3_PREDICATE(ib
[0]) ? "(predicate)" : "";
258 /* Print the name first. */
259 for (i
= 0; i
< ARRAY_SIZE(packet3_table
); i
++)
260 if (packet3_table
[i
].op
== op
)
263 if (i
< ARRAY_SIZE(packet3_table
)) {
264 const char *name
= sid_strings
+ packet3_table
[i
].name_offset
;
266 if (op
== PKT3_SET_CONTEXT_REG
||
267 op
== PKT3_SET_CONFIG_REG
||
268 op
== PKT3_SET_UCONFIG_REG
||
269 op
== PKT3_SET_SH_REG
)
270 fprintf(f
, COLOR_CYAN
"%s%s" COLOR_CYAN
":\n",
273 fprintf(f
, COLOR_GREEN
"%s%s" COLOR_RESET
":\n",
276 fprintf(f
, COLOR_RED
"PKT3_UNKNOWN 0x%x%s" COLOR_RESET
":\n",
279 /* Print the contents. */
281 case PKT3_SET_CONTEXT_REG
:
282 si_parse_set_reg_packet(f
, ib
, count
, SI_CONTEXT_REG_OFFSET
);
284 case PKT3_SET_CONFIG_REG
:
285 si_parse_set_reg_packet(f
, ib
, count
, SI_CONFIG_REG_OFFSET
);
287 case PKT3_SET_UCONFIG_REG
:
288 si_parse_set_reg_packet(f
, ib
, count
, CIK_UCONFIG_REG_OFFSET
);
290 case PKT3_SET_SH_REG
:
291 si_parse_set_reg_packet(f
, ib
, count
, SI_SH_REG_OFFSET
);
293 case PKT3_ACQUIRE_MEM
:
294 si_dump_reg(f
, R_0301F0_CP_COHER_CNTL
, ib
[1], ~0);
295 si_dump_reg(f
, R_0301F4_CP_COHER_SIZE
, ib
[2], ~0);
296 si_dump_reg(f
, R_030230_CP_COHER_SIZE_HI
, ib
[3], ~0);
297 si_dump_reg(f
, R_0301F8_CP_COHER_BASE
, ib
[4], ~0);
298 si_dump_reg(f
, R_0301E4_CP_COHER_BASE_HI
, ib
[5], ~0);
299 print_named_value(f
, "POLL_INTERVAL", ib
[6], 16);
301 case PKT3_SURFACE_SYNC
:
302 if (chip_class
>= CIK
) {
303 si_dump_reg(f
, R_0301F0_CP_COHER_CNTL
, ib
[1], ~0);
304 si_dump_reg(f
, R_0301F4_CP_COHER_SIZE
, ib
[2], ~0);
305 si_dump_reg(f
, R_0301F8_CP_COHER_BASE
, ib
[3], ~0);
307 si_dump_reg(f
, R_0085F0_CP_COHER_CNTL
, ib
[1], ~0);
308 si_dump_reg(f
, R_0085F4_CP_COHER_SIZE
, ib
[2], ~0);
309 si_dump_reg(f
, R_0085F8_CP_COHER_BASE
, ib
[3], ~0);
311 print_named_value(f
, "POLL_INTERVAL", ib
[4], 16);
313 case PKT3_EVENT_WRITE
:
314 si_dump_reg(f
, R_028A90_VGT_EVENT_INITIATOR
, ib
[1],
315 S_028A90_EVENT_TYPE(~0));
316 print_named_value(f
, "EVENT_INDEX", (ib
[1] >> 8) & 0xf, 4);
317 print_named_value(f
, "INV_L2", (ib
[1] >> 20) & 0x1, 1);
319 print_named_value(f
, "ADDRESS_LO", ib
[2], 32);
320 print_named_value(f
, "ADDRESS_HI", ib
[3], 16);
323 case PKT3_DRAW_INDEX_AUTO
:
324 si_dump_reg(f
, R_030930_VGT_NUM_INDICES
, ib
[1], ~0);
325 si_dump_reg(f
, R_0287F0_VGT_DRAW_INITIATOR
, ib
[2], ~0);
327 case PKT3_DRAW_INDEX_2
:
328 si_dump_reg(f
, R_028A78_VGT_DMA_MAX_SIZE
, ib
[1], ~0);
329 si_dump_reg(f
, R_0287E8_VGT_DMA_BASE
, ib
[2], ~0);
330 si_dump_reg(f
, R_0287E4_VGT_DMA_BASE_HI
, ib
[3], ~0);
331 si_dump_reg(f
, R_030930_VGT_NUM_INDICES
, ib
[4], ~0);
332 si_dump_reg(f
, R_0287F0_VGT_DRAW_INITIATOR
, ib
[5], ~0);
334 case PKT3_INDEX_TYPE
:
335 si_dump_reg(f
, R_028A7C_VGT_DMA_INDEX_TYPE
, ib
[1], ~0);
337 case PKT3_NUM_INSTANCES
:
338 si_dump_reg(f
, R_030934_VGT_NUM_INSTANCES
, ib
[1], ~0);
340 case PKT3_WRITE_DATA
:
341 si_dump_reg(f
, R_370_CONTROL
, ib
[1], ~0);
342 si_dump_reg(f
, R_371_DST_ADDR_LO
, ib
[2], ~0);
343 si_dump_reg(f
, R_372_DST_ADDR_HI
, ib
[3], ~0);
344 for (i
= 2; i
< count
; i
++) {
345 print_spaces(f
, INDENT_PKT
);
346 fprintf(f
, "0x%08x\n", ib
[2+i
]);
350 si_dump_reg(f
, R_410_CP_DMA_WORD0
, ib
[1], ~0);
351 si_dump_reg(f
, R_411_CP_DMA_WORD1
, ib
[2], ~0);
352 si_dump_reg(f
, R_412_CP_DMA_WORD2
, ib
[3], ~0);
353 si_dump_reg(f
, R_413_CP_DMA_WORD3
, ib
[4], ~0);
354 si_dump_reg(f
, R_414_COMMAND
, ib
[5], ~0);
357 si_dump_reg(f
, R_500_DMA_DATA_WORD0
, ib
[1], ~0);
358 si_dump_reg(f
, R_501_SRC_ADDR_LO
, ib
[2], ~0);
359 si_dump_reg(f
, R_502_SRC_ADDR_HI
, ib
[3], ~0);
360 si_dump_reg(f
, R_503_DST_ADDR_LO
, ib
[4], ~0);
361 si_dump_reg(f
, R_504_DST_ADDR_HI
, ib
[5], ~0);
362 si_dump_reg(f
, R_414_COMMAND
, ib
[6], ~0);
364 case PKT3_INDIRECT_BUFFER_SI
:
365 case PKT3_INDIRECT_BUFFER_CONST
:
366 case PKT3_INDIRECT_BUFFER_CIK
:
367 si_dump_reg(f
, R_3F0_IB_BASE_LO
, ib
[1], ~0);
368 si_dump_reg(f
, R_3F1_IB_BASE_HI
, ib
[2], ~0);
369 si_dump_reg(f
, R_3F2_CONTROL
, ib
[3], ~0);
371 case PKT3_CLEAR_STATE
:
372 case PKT3_INCREMENT_DE_COUNTER
:
373 case PKT3_PFP_SYNC_ME
:
376 if (ib
[0] == 0xffff1000) {
377 count
= -1; /* One dword NOP. */
379 } else if (count
== 0 && SI_IS_TRACE_POINT(ib
[1])) {
380 unsigned packet_id
= SI_GET_TRACE_POINT_ID(ib
[1]);
382 print_spaces(f
, INDENT_PKT
);
383 fprintf(f
, COLOR_RED
"Trace point ID: %u\n", packet_id
);
386 break; /* tracing was disabled */
388 print_spaces(f
, INDENT_PKT
);
389 if (packet_id
< trace_id
)
391 "This trace point was reached by the CP."
393 else if (packet_id
== trace_id
)
395 "!!!!! This is the last trace point that "
396 "was reached by the CP !!!!!"
398 else if (packet_id
+1 == trace_id
)
400 "!!!!! This is the first trace point that "
401 "was NOT been reached by the CP !!!!!"
405 "!!!!! This trace point was NOT reached "
410 /* fall through, print all dwords */
412 for (i
= 0; i
< count
+1; i
++) {
413 print_spaces(f
, INDENT_PKT
);
414 fprintf(f
, "0x%08x\n", ib
[1+i
]);
419 *num_dw
-= count
+ 2;
424 * Parse and print an IB into a file.
428 * \param num_dw size of the IB
429 * \param chip_class chip class
430 * \param trace_id the last trace ID that is known to have been reached
431 * and executed by the CP, typically read from a buffer
433 static void si_parse_ib(FILE *f
, uint32_t *ib
, int num_dw
, int trace_id
,
434 const char *name
, enum chip_class chip_class
)
436 fprintf(f
, "------------------ %s begin ------------------\n", name
);
439 unsigned type
= PKT_TYPE_G(ib
[0]);
443 ib
= si_parse_packet3(f
, ib
, &num_dw
, trace_id
,
448 if (ib
[0] == 0x80000000) {
449 fprintf(f
, COLOR_GREEN
"NOP (type 2)" COLOR_RESET
"\n");
455 fprintf(f
, "Unknown packet type %i\n", type
);
460 fprintf(f
, "------------------- %s end -------------------\n", name
);
462 printf("Packet ends after the end of IB.\n");
468 static void si_dump_mmapped_reg(struct si_context
*sctx
, FILE *f
,
471 struct radeon_winsys
*ws
= sctx
->b
.ws
;
474 if (ws
->read_registers(ws
, offset
, 1, &value
))
475 si_dump_reg(f
, offset
, value
, ~0);
478 static void si_dump_debug_registers(struct si_context
*sctx
, FILE *f
)
480 if (sctx
->screen
->b
.info
.drm_major
== 2 &&
481 sctx
->screen
->b
.info
.drm_minor
< 42)
482 return; /* no radeon support */
484 fprintf(f
, "Memory-mapped registers:\n");
485 si_dump_mmapped_reg(sctx
, f
, R_008010_GRBM_STATUS
);
487 /* No other registers can be read on DRM < 3.1.0. */
488 if (sctx
->screen
->b
.info
.drm_major
< 3 ||
489 sctx
->screen
->b
.info
.drm_minor
< 1) {
494 si_dump_mmapped_reg(sctx
, f
, R_008008_GRBM_STATUS2
);
495 si_dump_mmapped_reg(sctx
, f
, R_008014_GRBM_STATUS_SE0
);
496 si_dump_mmapped_reg(sctx
, f
, R_008018_GRBM_STATUS_SE1
);
497 si_dump_mmapped_reg(sctx
, f
, R_008038_GRBM_STATUS_SE2
);
498 si_dump_mmapped_reg(sctx
, f
, R_00803C_GRBM_STATUS_SE3
);
499 si_dump_mmapped_reg(sctx
, f
, R_00D034_SDMA0_STATUS_REG
);
500 si_dump_mmapped_reg(sctx
, f
, R_00D834_SDMA1_STATUS_REG
);
501 si_dump_mmapped_reg(sctx
, f
, R_000E50_SRBM_STATUS
);
502 si_dump_mmapped_reg(sctx
, f
, R_000E4C_SRBM_STATUS2
);
503 si_dump_mmapped_reg(sctx
, f
, R_000E54_SRBM_STATUS3
);
504 si_dump_mmapped_reg(sctx
, f
, R_008680_CP_STAT
);
505 si_dump_mmapped_reg(sctx
, f
, R_008674_CP_STALLED_STAT1
);
506 si_dump_mmapped_reg(sctx
, f
, R_008678_CP_STALLED_STAT2
);
507 si_dump_mmapped_reg(sctx
, f
, R_008670_CP_STALLED_STAT3
);
508 si_dump_mmapped_reg(sctx
, f
, R_008210_CP_CPC_STATUS
);
509 si_dump_mmapped_reg(sctx
, f
, R_008214_CP_CPC_BUSY_STAT
);
510 si_dump_mmapped_reg(sctx
, f
, R_008218_CP_CPC_STALLED_STAT1
);
511 si_dump_mmapped_reg(sctx
, f
, R_00821C_CP_CPF_STATUS
);
512 si_dump_mmapped_reg(sctx
, f
, R_008220_CP_CPF_BUSY_STAT
);
513 si_dump_mmapped_reg(sctx
, f
, R_008224_CP_CPF_STALLED_STAT1
);
517 static void si_dump_last_ib(struct si_context
*sctx
, FILE *f
)
519 int last_trace_id
= -1;
521 if (!sctx
->last_gfx
.ib
)
524 if (sctx
->last_trace_buf
) {
525 /* We are expecting that the ddebug pipe has already
526 * waited for the context, so this buffer should be idle.
527 * If the GPU is hung, there is no point in waiting for it.
529 uint32_t *map
= sctx
->b
.ws
->buffer_map(sctx
->last_trace_buf
->buf
,
531 PIPE_TRANSFER_UNSYNCHRONIZED
|
534 last_trace_id
= *map
;
537 if (sctx
->init_config
)
538 si_parse_ib(f
, sctx
->init_config
->pm4
, sctx
->init_config
->ndw
,
539 -1, "IB2: Init config", sctx
->b
.chip_class
);
541 if (sctx
->init_config_gs_rings
)
542 si_parse_ib(f
, sctx
->init_config_gs_rings
->pm4
,
543 sctx
->init_config_gs_rings
->ndw
,
544 -1, "IB2: Init GS rings", sctx
->b
.chip_class
);
546 si_parse_ib(f
, sctx
->last_gfx
.ib
, sctx
->last_gfx
.num_dw
,
547 last_trace_id
, "IB", sctx
->b
.chip_class
);
550 static const char *priority_to_string(enum radeon_bo_priority priority
)
552 #define ITEM(x) [RADEON_PRIO_##x] = #x
553 static const char *table
[64] = {
556 ITEM(SO_FILLED_SIZE
),
570 ITEM(SAMPLER_BUFFER
),
572 ITEM(SHADER_RW_BUFFER
),
573 ITEM(COMPUTE_GLOBAL
),
574 ITEM(SAMPLER_TEXTURE
),
575 ITEM(SHADER_RW_IMAGE
),
576 ITEM(SAMPLER_TEXTURE_MSAA
),
579 ITEM(COLOR_BUFFER_MSAA
),
580 ITEM(DEPTH_BUFFER_MSAA
),
586 ITEM(SCRATCH_BUFFER
),
590 assert(priority
< ARRAY_SIZE(table
));
591 return table
[priority
];
594 static int bo_list_compare_va(const struct radeon_bo_list_item
*a
,
595 const struct radeon_bo_list_item
*b
)
597 return a
->vm_address
< b
->vm_address
? -1 :
598 a
->vm_address
> b
->vm_address
? 1 : 0;
601 static void si_dump_bo_list(struct si_context
*sctx
,
602 const struct radeon_saved_cs
*saved
, FILE *f
)
609 /* Sort the list according to VM adddresses first. */
610 qsort(saved
->bo_list
, saved
->bo_count
,
611 sizeof(saved
->bo_list
[0]), (void*)bo_list_compare_va
);
613 fprintf(f
, "Buffer list (in units of pages = 4kB):\n"
614 COLOR_YELLOW
" Size VM start page "
615 "VM end page Usage" COLOR_RESET
"\n");
617 for (i
= 0; i
< saved
->bo_count
; i
++) {
618 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
619 const unsigned page_size
= sctx
->b
.screen
->info
.gart_page_size
;
620 uint64_t va
= saved
->bo_list
[i
].vm_address
;
621 uint64_t size
= saved
->bo_list
[i
].bo_size
;
624 /* If there's unused virtual memory between 2 buffers, print it. */
626 uint64_t previous_va_end
= saved
->bo_list
[i
-1].vm_address
+
627 saved
->bo_list
[i
-1].bo_size
;
629 if (va
> previous_va_end
) {
630 fprintf(f
, " %10"PRIu64
" -- hole --\n",
631 (va
- previous_va_end
) / page_size
);
635 /* Print the buffer. */
636 fprintf(f
, " %10"PRIu64
" 0x%013"PRIX64
" 0x%013"PRIX64
" ",
637 size
/ page_size
, va
/ page_size
, (va
+ size
) / page_size
);
639 /* Print the usage. */
640 for (j
= 0; j
< 64; j
++) {
641 if (!(saved
->bo_list
[i
].priority_usage
& (1llu << j
)))
644 fprintf(f
, "%s%s", !hit
? "" : ", ", priority_to_string(j
));
649 fprintf(f
, "\nNote: The holes represent memory not used by the IB.\n"
650 " Other buffers can still be allocated there.\n\n");
653 static void si_dump_framebuffer(struct si_context
*sctx
, FILE *f
)
655 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
656 struct r600_texture
*rtex
;
659 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
660 if (!state
->cbufs
[i
])
663 rtex
= (struct r600_texture
*)state
->cbufs
[i
]->texture
;
664 fprintf(f
, COLOR_YELLOW
"Color buffer %i:" COLOR_RESET
"\n", i
);
665 r600_print_texture_info(rtex
, f
);
670 rtex
= (struct r600_texture
*)state
->zsbuf
->texture
;
671 fprintf(f
, COLOR_YELLOW
"Depth-stencil buffer:" COLOR_RESET
"\n");
672 r600_print_texture_info(rtex
, f
);
677 static void si_dump_descriptor_list(struct si_descriptors
*desc
,
678 const char *shader_name
,
679 const char *elem_name
,
680 unsigned num_elements
,
684 uint32_t *cpu_list
= desc
->list
;
685 uint32_t *gpu_list
= desc
->gpu_list
;
686 const char *list_note
= "GPU list";
690 list_note
= "CPU list";
693 for (i
= 0; i
< num_elements
; i
++) {
694 fprintf(f
, COLOR_GREEN
"%s%s slot %u (%s):" COLOR_RESET
"\n",
695 shader_name
, elem_name
, i
, list_note
);
697 switch (desc
->element_dw_size
) {
699 for (j
= 0; j
< 4; j
++)
700 si_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
701 gpu_list
[j
], 0xffffffff);
704 for (j
= 0; j
< 8; j
++)
705 si_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
706 gpu_list
[j
], 0xffffffff);
708 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
709 for (j
= 0; j
< 4; j
++)
710 si_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
711 gpu_list
[4+j
], 0xffffffff);
714 for (j
= 0; j
< 8; j
++)
715 si_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
716 gpu_list
[j
], 0xffffffff);
718 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
719 for (j
= 0; j
< 4; j
++)
720 si_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
721 gpu_list
[4+j
], 0xffffffff);
723 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
724 for (j
= 0; j
< 8; j
++)
725 si_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
726 gpu_list
[8+j
], 0xffffffff);
728 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
729 for (j
= 0; j
< 4; j
++)
730 si_dump_reg(f
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
*4,
731 gpu_list
[12+j
], 0xffffffff);
735 if (memcmp(gpu_list
, cpu_list
, desc
->element_dw_size
* 4) != 0) {
736 fprintf(f
, COLOR_RED
"!!!!! This slot was corrupted in GPU memory !!!!!"
741 gpu_list
+= desc
->element_dw_size
;
742 cpu_list
+= desc
->element_dw_size
;
746 static void si_dump_descriptors(struct si_context
*sctx
,
747 struct si_shader_ctx_state
*state
,
750 if (!state
->cso
|| !state
->current
)
753 unsigned type
= state
->cso
->type
;
754 const struct tgsi_shader_info
*info
= &state
->cso
->info
;
755 struct si_descriptors
*descs
=
756 &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
+
757 type
* SI_NUM_SHADER_DESCS
];
758 static const char *shader_name
[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
760 static const char *elem_name
[] = {
761 " - Constant buffer",
766 unsigned num_elements
[] = {
767 util_last_bit(info
->const_buffers_declared
),
768 util_last_bit(info
->shader_buffers_declared
),
769 util_last_bit(info
->samplers_declared
),
770 util_last_bit(info
->images_declared
),
773 if (type
== PIPE_SHADER_VERTEX
) {
774 si_dump_descriptor_list(&sctx
->vertex_buffers
, shader_name
[type
],
775 " - Vertex buffer", info
->num_inputs
, f
);
778 for (unsigned i
= 0; i
< SI_NUM_SHADER_DESCS
; ++i
, ++descs
)
779 si_dump_descriptor_list(descs
, shader_name
[type
], elem_name
[i
],
783 static void si_dump_debug_state(struct pipe_context
*ctx
, FILE *f
,
786 struct si_context
*sctx
= (struct si_context
*)ctx
;
788 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
)
789 si_dump_debug_registers(sctx
, f
);
791 if (flags
& PIPE_DUMP_CURRENT_STATES
)
792 si_dump_framebuffer(sctx
, f
);
794 if (flags
& PIPE_DUMP_CURRENT_SHADERS
) {
795 si_dump_shader(sctx
->screen
, &sctx
->vs_shader
, f
);
796 si_dump_shader(sctx
->screen
, &sctx
->tcs_shader
, f
);
797 si_dump_shader(sctx
->screen
, &sctx
->tes_shader
, f
);
798 si_dump_shader(sctx
->screen
, &sctx
->gs_shader
, f
);
799 si_dump_shader(sctx
->screen
, &sctx
->ps_shader
, f
);
801 si_dump_descriptor_list(&sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
802 "", "RW buffers", SI_NUM_RW_BUFFERS
, f
);
803 si_dump_descriptors(sctx
, &sctx
->vs_shader
, f
);
804 si_dump_descriptors(sctx
, &sctx
->tcs_shader
, f
);
805 si_dump_descriptors(sctx
, &sctx
->tes_shader
, f
);
806 si_dump_descriptors(sctx
, &sctx
->gs_shader
, f
);
807 si_dump_descriptors(sctx
, &sctx
->ps_shader
, f
);
810 if (flags
& PIPE_DUMP_LAST_COMMAND_BUFFER
) {
811 si_dump_bo_list(sctx
, &sctx
->last_gfx
, f
);
812 si_dump_last_ib(sctx
, f
);
814 fprintf(f
, "Done.\n");
817 radeon_clear_saved_cs(&sctx
->last_gfx
);
818 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
822 static void si_dump_dma(struct si_context
*sctx
,
823 struct radeon_saved_cs
*saved
, FILE *f
)
825 static const char ib_name
[] = "sDMA IB";
828 si_dump_bo_list(sctx
, saved
, f
);
830 fprintf(f
, "------------------ %s begin ------------------\n", ib_name
);
832 for (i
= 0; i
< saved
->num_dw
; ++i
) {
833 fprintf(f
, " %08x\n", saved
->ib
[i
]);
836 fprintf(f
, "------------------- %s end -------------------\n", ib_name
);
839 fprintf(f
, "SDMA Dump Done.\n");
842 static bool si_vm_fault_occured(struct si_context
*sctx
, uint32_t *out_addr
)
847 uint64_t timestamp
= 0;
850 FILE *p
= popen("dmesg", "r");
854 while (fgets(line
, sizeof(line
), p
)) {
857 if (!line
[0] || line
[0] == '\n')
860 /* Get the timestamp. */
861 if (sscanf(line
, "[%u.%u]", &sec
, &usec
) != 2) {
862 static bool hit
= false;
864 fprintf(stderr
, "%s: failed to parse line '%s'\n",
870 timestamp
= sec
* 1000000llu + usec
;
872 /* If just updating the timestamp. */
876 /* Process messages only if the timestamp is newer. */
877 if (timestamp
<= sctx
->dmesg_timestamp
)
880 /* Only process the first VM fault. */
884 /* Remove trailing \n */
886 if (len
&& line
[len
-1] == '\n')
889 /* Get the message part. */
890 msg
= strchr(line
, ']');
899 if (strstr(msg
, "GPU fault detected:"))
903 msg
= strstr(msg
, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
905 msg
= strstr(msg
, "0x");
908 if (sscanf(msg
, "%X", out_addr
) == 1)
920 if (timestamp
> sctx
->dmesg_timestamp
)
921 sctx
->dmesg_timestamp
= timestamp
;
925 void si_check_vm_faults(struct r600_common_context
*ctx
,
926 struct radeon_saved_cs
*saved
, enum ring_type ring
)
928 struct si_context
*sctx
= (struct si_context
*)ctx
;
929 struct pipe_screen
*screen
= sctx
->b
.b
.screen
;
934 if (!si_vm_fault_occured(sctx
, &addr
))
937 f
= dd_get_debug_file(false);
941 fprintf(f
, "VM fault report.\n\n");
942 if (os_get_command_line(cmd_line
, sizeof(cmd_line
)))
943 fprintf(f
, "Command: %s\n", cmd_line
);
944 fprintf(f
, "Driver vendor: %s\n", screen
->get_vendor(screen
));
945 fprintf(f
, "Device vendor: %s\n", screen
->get_device_vendor(screen
));
946 fprintf(f
, "Device name: %s\n\n", screen
->get_name(screen
));
947 fprintf(f
, "Failing VM page: 0x%08x\n\n", addr
);
949 if (sctx
->apitrace_call_number
)
950 fprintf(f
, "Last apitrace call: %u\n\n",
951 sctx
->apitrace_call_number
);
955 si_dump_debug_state(&sctx
->b
.b
, f
,
956 PIPE_DUMP_CURRENT_STATES
|
957 PIPE_DUMP_CURRENT_SHADERS
|
958 PIPE_DUMP_LAST_COMMAND_BUFFER
);
962 si_dump_dma(sctx
, saved
, f
);
971 fprintf(stderr
, "Detected a VM fault, exiting...\n");
975 void si_init_debug_functions(struct si_context
*sctx
)
977 sctx
->b
.b
.dump_debug_state
= si_dump_debug_state
;
978 sctx
->b
.check_vm_faults
= si_check_vm_faults
;
980 /* Set the initial dmesg timestamp for this context, so that
981 * only new messages will be checked for VM faults.
983 if (sctx
->screen
->b
.debug_flags
& DBG_CHECK_VM
)
984 si_vm_fault_occured(sctx
, NULL
);