gallium: add render_condition_enable param to clear_render_target/depth_stencil
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <maraeo@gmail.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "sid_tables.h"
31 #include "radeon/radeon_elf_util.h"
32 #include "ddebug/dd_util.h"
33 #include "util/u_memory.h"
34
35 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
36
37 static void si_dump_shader(struct si_screen *sscreen,
38 struct si_shader_ctx_state *state, FILE *f)
39 {
40 struct si_shader *current = state->current;
41
42 if (!state->cso || !current)
43 return;
44
45 if (current->shader_log)
46 fwrite(current->shader_log, current->shader_log_size, 1, f);
47 else
48 si_shader_dump(sscreen, state->current, NULL,
49 state->cso->info.processor, f);
50 }
51
52 /**
53 * Shader compiles can be overridden with arbitrary ELF objects by setting
54 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
55 */
56 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary)
57 {
58 const char *p = debug_get_option_replace_shaders();
59 const char *semicolon;
60 char *copy = NULL;
61 FILE *f;
62 long filesize, nread;
63 char *buf = NULL;
64 bool replaced = false;
65
66 if (!p)
67 return false;
68
69 while (*p) {
70 unsigned long i;
71 char *endp;
72 i = strtoul(p, &endp, 0);
73
74 p = endp;
75 if (*p != ':') {
76 fprintf(stderr, "RADEON_REPLACE_SHADERS formatted badly.\n");
77 exit(1);
78 }
79 ++p;
80
81 if (i == num)
82 break;
83
84 p = strchr(p, ';');
85 if (!p)
86 return false;
87 ++p;
88 }
89 if (!*p)
90 return false;
91
92 semicolon = strchr(p, ';');
93 if (semicolon) {
94 p = copy = strndup(p, semicolon - p);
95 if (!copy) {
96 fprintf(stderr, "out of memory\n");
97 return false;
98 }
99 }
100
101 fprintf(stderr, "radeonsi: replace shader %u by %s\n", num, p);
102
103 f = fopen(p, "r");
104 if (!f) {
105 perror("radeonsi: failed to open file");
106 goto out_free;
107 }
108
109 if (fseek(f, 0, SEEK_END) != 0)
110 goto file_error;
111
112 filesize = ftell(f);
113 if (filesize < 0)
114 goto file_error;
115
116 if (fseek(f, 0, SEEK_SET) != 0)
117 goto file_error;
118
119 buf = MALLOC(filesize);
120 if (!buf) {
121 fprintf(stderr, "out of memory\n");
122 goto out_close;
123 }
124
125 nread = fread(buf, 1, filesize, f);
126 if (nread != filesize)
127 goto file_error;
128
129 radeon_elf_read(buf, filesize, binary);
130 replaced = true;
131
132 out_close:
133 fclose(f);
134 out_free:
135 FREE(buf);
136 free(copy);
137 return replaced;
138
139 file_error:
140 perror("radeonsi: reading shader");
141 goto out_close;
142 }
143
144 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
145 * read them, or use "aha -b -f file" to convert them to html.
146 */
147 #define COLOR_RESET "\033[0m"
148 #define COLOR_RED "\033[31m"
149 #define COLOR_GREEN "\033[1;32m"
150 #define COLOR_YELLOW "\033[1;33m"
151 #define COLOR_CYAN "\033[1;36m"
152
153 #define INDENT_PKT 8
154
155 static void print_spaces(FILE *f, unsigned num)
156 {
157 fprintf(f, "%*s", num, "");
158 }
159
160 static void print_value(FILE *file, uint32_t value, int bits)
161 {
162 /* Guess if it's int or float */
163 if (value <= (1 << 15)) {
164 if (value <= 9)
165 fprintf(file, "%u\n", value);
166 else
167 fprintf(file, "%u (0x%0*x)\n", value, bits / 4, value);
168 } else {
169 float f = uif(value);
170
171 if (fabs(f) < 100000 && f*10 == floor(f*10))
172 fprintf(file, "%.1ff (0x%0*x)\n", f, bits / 4, value);
173 else
174 /* Don't print more leading zeros than there are bits. */
175 fprintf(file, "0x%0*x\n", bits / 4, value);
176 }
177 }
178
179 static void print_named_value(FILE *file, const char *name, uint32_t value,
180 int bits)
181 {
182 print_spaces(file, INDENT_PKT);
183 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", name);
184 print_value(file, value, bits);
185 }
186
187 static void si_dump_reg(FILE *file, unsigned offset, uint32_t value,
188 uint32_t field_mask)
189 {
190 int r, f;
191
192 for (r = 0; r < ARRAY_SIZE(sid_reg_table); r++) {
193 const struct si_reg *reg = &sid_reg_table[r];
194 const char *reg_name = sid_strings + reg->name_offset;
195
196 if (reg->offset == offset) {
197 bool first_field = true;
198
199 print_spaces(file, INDENT_PKT);
200 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ",
201 reg_name);
202
203 if (!reg->num_fields) {
204 print_value(file, value, 32);
205 return;
206 }
207
208 for (f = 0; f < reg->num_fields; f++) {
209 const struct si_field *field = sid_fields_table + reg->fields_offset + f;
210 const int *values_offsets = sid_strings_offsets + field->values_offset;
211 uint32_t val = (value & field->mask) >>
212 (ffs(field->mask) - 1);
213
214 if (!(field->mask & field_mask))
215 continue;
216
217 /* Indent the field. */
218 if (!first_field)
219 print_spaces(file,
220 INDENT_PKT + strlen(reg_name) + 4);
221
222 /* Print the field. */
223 fprintf(file, "%s = ", sid_strings + field->name_offset);
224
225 if (val < field->num_values && values_offsets[val] >= 0)
226 fprintf(file, "%s\n", sid_strings + values_offsets[val]);
227 else
228 print_value(file, val,
229 util_bitcount(field->mask));
230
231 first_field = false;
232 }
233 return;
234 }
235 }
236
237 fprintf(file, COLOR_YELLOW "0x%05x" COLOR_RESET " = 0x%08x", offset, value);
238 }
239
240 static void si_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count,
241 unsigned reg_offset)
242 {
243 unsigned reg = (ib[1] << 2) + reg_offset;
244 int i;
245
246 for (i = 0; i < count; i++)
247 si_dump_reg(f, reg + i*4, ib[2+i], ~0);
248 }
249
250 static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
251 int trace_id)
252 {
253 unsigned count = PKT_COUNT_G(ib[0]);
254 unsigned op = PKT3_IT_OPCODE_G(ib[0]);
255 const char *predicate = PKT3_PREDICATE(ib[0]) ? "(predicate)" : "";
256 int i;
257
258 /* Print the name first. */
259 for (i = 0; i < ARRAY_SIZE(packet3_table); i++)
260 if (packet3_table[i].op == op)
261 break;
262
263 if (i < ARRAY_SIZE(packet3_table)) {
264 const char *name = sid_strings + packet3_table[i].name_offset;
265
266 if (op == PKT3_SET_CONTEXT_REG ||
267 op == PKT3_SET_CONFIG_REG ||
268 op == PKT3_SET_UCONFIG_REG ||
269 op == PKT3_SET_SH_REG)
270 fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
271 name, predicate);
272 else
273 fprintf(f, COLOR_GREEN "%s%s" COLOR_RESET ":\n",
274 name, predicate);
275 } else
276 fprintf(f, COLOR_RED "PKT3_UNKNOWN 0x%x%s" COLOR_RESET ":\n",
277 op, predicate);
278
279 /* Print the contents. */
280 switch (op) {
281 case PKT3_SET_CONTEXT_REG:
282 si_parse_set_reg_packet(f, ib, count, SI_CONTEXT_REG_OFFSET);
283 break;
284 case PKT3_SET_CONFIG_REG:
285 si_parse_set_reg_packet(f, ib, count, SI_CONFIG_REG_OFFSET);
286 break;
287 case PKT3_SET_UCONFIG_REG:
288 si_parse_set_reg_packet(f, ib, count, CIK_UCONFIG_REG_OFFSET);
289 break;
290 case PKT3_SET_SH_REG:
291 si_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET);
292 break;
293 case PKT3_ACQUIRE_MEM:
294 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
295 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
296 si_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ib[3], ~0);
297 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[4], ~0);
298 si_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ib[5], ~0);
299 print_named_value(f, "POLL_INTERVAL", ib[6], 16);
300 break;
301 case PKT3_SURFACE_SYNC:
302 si_dump_reg(f, R_0085F0_CP_COHER_CNTL, ib[1], ~0);
303 si_dump_reg(f, R_0085F4_CP_COHER_SIZE, ib[2], ~0);
304 si_dump_reg(f, R_0085F8_CP_COHER_BASE, ib[3], ~0);
305 print_named_value(f, "POLL_INTERVAL", ib[4], 16);
306 break;
307 case PKT3_EVENT_WRITE:
308 si_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
309 S_028A90_EVENT_TYPE(~0));
310 print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
311 print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
312 if (count > 0) {
313 print_named_value(f, "ADDRESS_LO", ib[2], 32);
314 print_named_value(f, "ADDRESS_HI", ib[3], 16);
315 }
316 break;
317 case PKT3_DRAW_INDEX_AUTO:
318 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
319 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
320 break;
321 case PKT3_DRAW_INDEX_2:
322 si_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
323 si_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
324 si_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
325 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
326 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
327 break;
328 case PKT3_INDEX_TYPE:
329 si_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ib[1], ~0);
330 break;
331 case PKT3_NUM_INSTANCES:
332 si_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ib[1], ~0);
333 break;
334 case PKT3_WRITE_DATA:
335 si_dump_reg(f, R_370_CONTROL, ib[1], ~0);
336 si_dump_reg(f, R_371_DST_ADDR_LO, ib[2], ~0);
337 si_dump_reg(f, R_372_DST_ADDR_HI, ib[3], ~0);
338 for (i = 2; i < count; i++) {
339 print_spaces(f, INDENT_PKT);
340 fprintf(f, "0x%08x\n", ib[2+i]);
341 }
342 break;
343 case PKT3_CP_DMA:
344 si_dump_reg(f, R_410_CP_DMA_WORD0, ib[1], ~0);
345 si_dump_reg(f, R_411_CP_DMA_WORD1, ib[2], ~0);
346 si_dump_reg(f, R_412_CP_DMA_WORD2, ib[3], ~0);
347 si_dump_reg(f, R_413_CP_DMA_WORD3, ib[4], ~0);
348 si_dump_reg(f, R_414_COMMAND, ib[5], ~0);
349 break;
350 case PKT3_DMA_DATA:
351 si_dump_reg(f, R_500_DMA_DATA_WORD0, ib[1], ~0);
352 si_dump_reg(f, R_501_SRC_ADDR_LO, ib[2], ~0);
353 si_dump_reg(f, R_502_SRC_ADDR_HI, ib[3], ~0);
354 si_dump_reg(f, R_503_DST_ADDR_LO, ib[4], ~0);
355 si_dump_reg(f, R_504_DST_ADDR_HI, ib[5], ~0);
356 si_dump_reg(f, R_414_COMMAND, ib[6], ~0);
357 break;
358 case PKT3_INDIRECT_BUFFER_SI:
359 case PKT3_INDIRECT_BUFFER_CONST:
360 case PKT3_INDIRECT_BUFFER_CIK:
361 si_dump_reg(f, R_3F0_IB_BASE_LO, ib[1], ~0);
362 si_dump_reg(f, R_3F1_IB_BASE_HI, ib[2], ~0);
363 si_dump_reg(f, R_3F2_CONTROL, ib[3], ~0);
364 break;
365 case PKT3_NOP:
366 if (ib[0] == 0xffff1000) {
367 count = -1; /* One dword NOP. */
368 break;
369 } else if (count == 0 && SI_IS_TRACE_POINT(ib[1])) {
370 unsigned packet_id = SI_GET_TRACE_POINT_ID(ib[1]);
371
372 print_spaces(f, INDENT_PKT);
373 fprintf(f, COLOR_RED "Trace point ID: %u\n", packet_id);
374
375 if (trace_id == -1)
376 break; /* tracing was disabled */
377
378 print_spaces(f, INDENT_PKT);
379 if (packet_id < trace_id)
380 fprintf(f, COLOR_RED
381 "This trace point was reached by the CP."
382 COLOR_RESET "\n");
383 else if (packet_id == trace_id)
384 fprintf(f, COLOR_RED
385 "!!!!! This is the last trace point that "
386 "was reached by the CP !!!!!"
387 COLOR_RESET "\n");
388 else if (packet_id+1 == trace_id)
389 fprintf(f, COLOR_RED
390 "!!!!! This is the first trace point that "
391 "was NOT been reached by the CP !!!!!"
392 COLOR_RESET "\n");
393 else
394 fprintf(f, COLOR_RED
395 "!!!!! This trace point was NOT reached "
396 "by the CP !!!!!"
397 COLOR_RESET "\n");
398 break;
399 }
400 /* fall through, print all dwords */
401 default:
402 for (i = 0; i < count+1; i++) {
403 print_spaces(f, INDENT_PKT);
404 fprintf(f, "0x%08x\n", ib[1+i]);
405 }
406 }
407
408 ib += count + 2;
409 *num_dw -= count + 2;
410 return ib;
411 }
412
413 /**
414 * Parse and print an IB into a file.
415 *
416 * \param f file
417 * \param ib IB
418 * \param num_dw size of the IB
419 * \param chip_class chip class
420 * \param trace_id the last trace ID that is known to have been reached
421 * and executed by the CP, typically read from a buffer
422 */
423 static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id,
424 const char *name)
425 {
426 fprintf(f, "------------------ %s begin ------------------\n", name);
427
428 while (num_dw > 0) {
429 unsigned type = PKT_TYPE_G(ib[0]);
430
431 switch (type) {
432 case 3:
433 ib = si_parse_packet3(f, ib, &num_dw, trace_id);
434 break;
435 case 2:
436 /* type-2 nop */
437 if (ib[0] == 0x80000000) {
438 fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
439 ib++;
440 break;
441 }
442 /* fall through */
443 default:
444 fprintf(f, "Unknown packet type %i\n", type);
445 return;
446 }
447 }
448
449 fprintf(f, "------------------- %s end -------------------\n", name);
450 if (num_dw < 0) {
451 printf("Packet ends after the end of IB.\n");
452 exit(0);
453 }
454 fprintf(f, "\n");
455 }
456
457 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
458 unsigned offset)
459 {
460 struct radeon_winsys *ws = sctx->b.ws;
461 uint32_t value;
462
463 if (ws->read_registers(ws, offset, 1, &value))
464 si_dump_reg(f, offset, value, ~0);
465 }
466
467 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
468 {
469 if (sctx->screen->b.info.drm_major == 2 &&
470 sctx->screen->b.info.drm_minor < 42)
471 return; /* no radeon support */
472
473 fprintf(f, "Memory-mapped registers:\n");
474 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
475
476 /* No other registers can be read on DRM < 3.1.0. */
477 if (sctx->screen->b.info.drm_major < 3 ||
478 sctx->screen->b.info.drm_minor < 1) {
479 fprintf(f, "\n");
480 return;
481 }
482
483 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
484 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
485 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
486 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
487 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
488 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
489 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
490 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
491 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
492 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
493 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
494 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
495 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
496 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
497 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
498 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
499 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
500 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
501 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
502 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
503 fprintf(f, "\n");
504 }
505
506 static void si_dump_last_ib(struct si_context *sctx, FILE *f)
507 {
508 int last_trace_id = -1;
509
510 if (!sctx->last_gfx.ib)
511 return;
512
513 if (sctx->last_trace_buf) {
514 /* We are expecting that the ddebug pipe has already
515 * waited for the context, so this buffer should be idle.
516 * If the GPU is hung, there is no point in waiting for it.
517 */
518 uint32_t *map = sctx->b.ws->buffer_map(sctx->last_trace_buf->buf,
519 NULL,
520 PIPE_TRANSFER_UNSYNCHRONIZED |
521 PIPE_TRANSFER_READ);
522 if (map)
523 last_trace_id = *map;
524 }
525
526 if (sctx->init_config)
527 si_parse_ib(f, sctx->init_config->pm4, sctx->init_config->ndw,
528 -1, "IB2: Init config");
529
530 if (sctx->init_config_gs_rings)
531 si_parse_ib(f, sctx->init_config_gs_rings->pm4,
532 sctx->init_config_gs_rings->ndw,
533 -1, "IB2: Init GS rings");
534
535 si_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw,
536 last_trace_id, "IB");
537 }
538
539 static const char *priority_to_string(enum radeon_bo_priority priority)
540 {
541 #define ITEM(x) [RADEON_PRIO_##x] = #x
542 static const char *table[64] = {
543 ITEM(FENCE),
544 ITEM(TRACE),
545 ITEM(SO_FILLED_SIZE),
546 ITEM(QUERY),
547 ITEM(IB1),
548 ITEM(IB2),
549 ITEM(DRAW_INDIRECT),
550 ITEM(INDEX_BUFFER),
551 ITEM(CP_DMA),
552 ITEM(VCE),
553 ITEM(UVD),
554 ITEM(SDMA_BUFFER),
555 ITEM(SDMA_TEXTURE),
556 ITEM(USER_SHADER),
557 ITEM(INTERNAL_SHADER),
558 ITEM(CONST_BUFFER),
559 ITEM(DESCRIPTORS),
560 ITEM(BORDER_COLORS),
561 ITEM(SAMPLER_BUFFER),
562 ITEM(VERTEX_BUFFER),
563 ITEM(SHADER_RW_BUFFER),
564 ITEM(RINGS_STREAMOUT),
565 ITEM(SCRATCH_BUFFER),
566 ITEM(COMPUTE_GLOBAL),
567 ITEM(SAMPLER_TEXTURE),
568 ITEM(SHADER_RW_IMAGE),
569 ITEM(SAMPLER_TEXTURE_MSAA),
570 ITEM(COLOR_BUFFER),
571 ITEM(DEPTH_BUFFER),
572 ITEM(COLOR_BUFFER_MSAA),
573 ITEM(DEPTH_BUFFER_MSAA),
574 ITEM(CMASK),
575 ITEM(DCC),
576 ITEM(HTILE),
577 };
578 #undef ITEM
579
580 assert(priority < ARRAY_SIZE(table));
581 return table[priority];
582 }
583
584 static int bo_list_compare_va(const struct radeon_bo_list_item *a,
585 const struct radeon_bo_list_item *b)
586 {
587 return a->vm_address < b->vm_address ? -1 :
588 a->vm_address > b->vm_address ? 1 : 0;
589 }
590
591 static void si_dump_bo_list(struct si_context *sctx,
592 const struct radeon_saved_cs *saved, FILE *f)
593 {
594 unsigned i,j;
595
596 if (!saved->bo_list)
597 return;
598
599 /* Sort the list according to VM adddresses first. */
600 qsort(saved->bo_list, saved->bo_count,
601 sizeof(saved->bo_list[0]), (void*)bo_list_compare_va);
602
603 fprintf(f, "Buffer list (in units of pages = 4kB):\n"
604 COLOR_YELLOW " Size VM start page "
605 "VM end page Usage" COLOR_RESET "\n");
606
607 for (i = 0; i < saved->bo_count; i++) {
608 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
609 const unsigned page_size = sctx->b.screen->info.gart_page_size;
610 uint64_t va = saved->bo_list[i].vm_address;
611 uint64_t size = saved->bo_list[i].bo_size;
612 bool hit = false;
613
614 /* If there's unused virtual memory between 2 buffers, print it. */
615 if (i) {
616 uint64_t previous_va_end = saved->bo_list[i-1].vm_address +
617 saved->bo_list[i-1].bo_size;
618
619 if (va > previous_va_end) {
620 fprintf(f, " %10"PRIu64" -- hole --\n",
621 (va - previous_va_end) / page_size);
622 }
623 }
624
625 /* Print the buffer. */
626 fprintf(f, " %10"PRIu64" 0x%013"PRIx64" 0x%013"PRIx64" ",
627 size / page_size, va / page_size, (va + size) / page_size);
628
629 /* Print the usage. */
630 for (j = 0; j < 64; j++) {
631 if (!(saved->bo_list[i].priority_usage & (1llu << j)))
632 continue;
633
634 fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
635 hit = true;
636 }
637 fprintf(f, "\n");
638 }
639 fprintf(f, "\nNote: The holes represent memory not used by the IB.\n"
640 " Other buffers can still be allocated there.\n\n");
641 }
642
643 static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
644 {
645 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
646 struct r600_texture *rtex;
647 int i;
648
649 for (i = 0; i < state->nr_cbufs; i++) {
650 if (!state->cbufs[i])
651 continue;
652
653 rtex = (struct r600_texture*)state->cbufs[i]->texture;
654 fprintf(f, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
655 r600_print_texture_info(rtex, f);
656 fprintf(f, "\n");
657 }
658
659 if (state->zsbuf) {
660 rtex = (struct r600_texture*)state->zsbuf->texture;
661 fprintf(f, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
662 r600_print_texture_info(rtex, f);
663 fprintf(f, "\n");
664 }
665 }
666
667 static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
668 unsigned flags)
669 {
670 struct si_context *sctx = (struct si_context*)ctx;
671
672 if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS)
673 si_dump_debug_registers(sctx, f);
674
675 if (flags & PIPE_DUMP_CURRENT_STATES)
676 si_dump_framebuffer(sctx, f);
677
678 if (flags & PIPE_DUMP_CURRENT_SHADERS) {
679 si_dump_shader(sctx->screen, &sctx->vs_shader, f);
680 si_dump_shader(sctx->screen, &sctx->tcs_shader, f);
681 si_dump_shader(sctx->screen, &sctx->tes_shader, f);
682 si_dump_shader(sctx->screen, &sctx->gs_shader, f);
683 si_dump_shader(sctx->screen, &sctx->ps_shader, f);
684 }
685
686 if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
687 si_dump_bo_list(sctx, &sctx->last_gfx, f);
688 si_dump_last_ib(sctx, f);
689
690 fprintf(f, "Done.\n");
691
692 /* dump only once */
693 radeon_clear_saved_cs(&sctx->last_gfx);
694 r600_resource_reference(&sctx->last_trace_buf, NULL);
695 }
696 }
697
698 static void si_dump_dma(struct si_context *sctx,
699 struct radeon_saved_cs *saved, FILE *f)
700 {
701 static const char ib_name[] = "sDMA IB";
702 unsigned i;
703
704 si_dump_bo_list(sctx, saved, f);
705
706 fprintf(f, "------------------ %s begin ------------------\n", ib_name);
707
708 for (i = 0; i < saved->num_dw; ++i) {
709 fprintf(f, " %08x\n", saved->ib[i]);
710 }
711
712 fprintf(f, "------------------- %s end -------------------\n", ib_name);
713 fprintf(f, "\n");
714
715 fprintf(f, "SDMA Dump Done.\n");
716 }
717
718 static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
719 {
720 char line[2000];
721 unsigned sec, usec;
722 int progress = 0;
723 uint64_t timestamp = 0;
724 bool fault = false;
725
726 FILE *p = popen("dmesg", "r");
727 if (!p)
728 return false;
729
730 while (fgets(line, sizeof(line), p)) {
731 char *msg, len;
732
733 if (!line[0] || line[0] == '\n')
734 continue;
735
736 /* Get the timestamp. */
737 if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
738 static bool hit = false;
739 if (!hit) {
740 fprintf(stderr, "%s: failed to parse line '%s'\n",
741 __func__, line);
742 hit = true;
743 }
744 continue;
745 }
746 timestamp = sec * 1000000llu + usec;
747
748 /* If just updating the timestamp. */
749 if (!out_addr)
750 continue;
751
752 /* Process messages only if the timestamp is newer. */
753 if (timestamp <= sctx->dmesg_timestamp)
754 continue;
755
756 /* Only process the first VM fault. */
757 if (fault)
758 continue;
759
760 /* Remove trailing \n */
761 len = strlen(line);
762 if (len && line[len-1] == '\n')
763 line[len-1] = 0;
764
765 /* Get the message part. */
766 msg = strchr(line, ']');
767 if (!msg) {
768 assert(0);
769 continue;
770 }
771 msg++;
772
773 switch (progress) {
774 case 0:
775 if (strstr(msg, "GPU fault detected:"))
776 progress = 1;
777 break;
778 case 1:
779 msg = strstr(msg, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
780 if (msg) {
781 msg = strstr(msg, "0x");
782 if (msg) {
783 msg += 2;
784 if (sscanf(msg, "%X", out_addr) == 1)
785 fault = true;
786 }
787 }
788 progress = 0;
789 break;
790 default:
791 progress = 0;
792 }
793 }
794 pclose(p);
795
796 if (timestamp > sctx->dmesg_timestamp)
797 sctx->dmesg_timestamp = timestamp;
798 return fault;
799 }
800
801 void si_check_vm_faults(struct r600_common_context *ctx,
802 struct radeon_saved_cs *saved, enum ring_type ring)
803 {
804 struct si_context *sctx = (struct si_context *)ctx;
805 struct pipe_screen *screen = sctx->b.b.screen;
806 FILE *f;
807 uint32_t addr;
808 char cmd_line[4096];
809
810 if (!si_vm_fault_occured(sctx, &addr))
811 return;
812
813 f = dd_get_debug_file(false);
814 if (!f)
815 return;
816
817 fprintf(f, "VM fault report.\n\n");
818 if (os_get_command_line(cmd_line, sizeof(cmd_line)))
819 fprintf(f, "Command: %s\n", cmd_line);
820 fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen));
821 fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen));
822 fprintf(f, "Device name: %s\n\n", screen->get_name(screen));
823 fprintf(f, "Failing VM page: 0x%08x\n\n", addr);
824
825 if (sctx->apitrace_call_number)
826 fprintf(f, "Last apitrace call: %u\n\n",
827 sctx->apitrace_call_number);
828
829 switch (ring) {
830 case RING_GFX:
831 si_dump_debug_state(&sctx->b.b, f, 0);
832 break;
833
834 case RING_DMA:
835 si_dump_dma(sctx, saved, f);
836 break;
837
838 default:
839 break;
840 }
841
842 fclose(f);
843
844 fprintf(stderr, "Detected a VM fault, exiting...\n");
845 exit(0);
846 }
847
848 void si_init_debug_functions(struct si_context *sctx)
849 {
850 sctx->b.b.dump_debug_state = si_dump_debug_state;
851 sctx->b.check_vm_faults = si_check_vm_faults;
852
853 /* Set the initial dmesg timestamp for this context, so that
854 * only new messages will be checked for VM faults.
855 */
856 if (sctx->screen->b.debug_flags & DBG_CHECK_VM)
857 si_vm_fault_occured(sctx, NULL);
858 }