2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <maraeo@gmail.com>
29 #include "sid_tables.h"
30 #include "ddebug/dd_util.h"
31 #include "util/u_memory.h"
34 DEBUG_GET_ONCE_OPTION(replace_shaders
, "RADEON_REPLACE_SHADERS", NULL
)
36 static void si_dump_shader(struct si_screen
*sscreen
,
37 struct si_shader_ctx_state
*state
, FILE *f
)
39 struct si_shader
*current
= state
->current
;
41 if (!state
->cso
|| !current
)
44 if (current
->shader_log
)
45 fwrite(current
->shader_log
, current
->shader_log_size
, 1, f
);
47 si_shader_dump(sscreen
, state
->current
, NULL
,
48 state
->cso
->info
.processor
, f
, false);
52 * Shader compiles can be overridden with arbitrary ELF objects by setting
53 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
55 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
)
57 const char *p
= debug_get_option_replace_shaders();
58 const char *semicolon
;
63 bool replaced
= false;
71 i
= strtoul(p
, &endp
, 0);
75 fprintf(stderr
, "RADEON_REPLACE_SHADERS formatted badly.\n");
91 semicolon
= strchr(p
, ';');
93 p
= copy
= strndup(p
, semicolon
- p
);
95 fprintf(stderr
, "out of memory\n");
100 fprintf(stderr
, "radeonsi: replace shader %u by %s\n", num
, p
);
104 perror("radeonsi: failed to open file");
108 if (fseek(f
, 0, SEEK_END
) != 0)
115 if (fseek(f
, 0, SEEK_SET
) != 0)
118 buf
= MALLOC(filesize
);
120 fprintf(stderr
, "out of memory\n");
124 nread
= fread(buf
, 1, filesize
, f
);
125 if (nread
!= filesize
)
128 ac_elf_read(buf
, filesize
, binary
);
139 perror("radeonsi: reading shader");
143 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
144 * read them, or use "aha -b -f file" to convert them to html.
146 #define COLOR_RESET "\033[0m"
147 #define COLOR_RED "\033[31m"
148 #define COLOR_GREEN "\033[1;32m"
149 #define COLOR_YELLOW "\033[1;33m"
150 #define COLOR_CYAN "\033[1;36m"
152 static void si_dump_mmapped_reg(struct si_context
*sctx
, FILE *f
,
155 struct radeon_winsys
*ws
= sctx
->b
.ws
;
158 if (ws
->read_registers(ws
, offset
, 1, &value
))
159 ac_dump_reg(f
, offset
, value
, ~0);
162 static void si_dump_debug_registers(struct si_context
*sctx
, FILE *f
)
164 if (sctx
->screen
->b
.info
.drm_major
== 2 &&
165 sctx
->screen
->b
.info
.drm_minor
< 42)
166 return; /* no radeon support */
168 fprintf(f
, "Memory-mapped registers:\n");
169 si_dump_mmapped_reg(sctx
, f
, R_008010_GRBM_STATUS
);
171 /* No other registers can be read on DRM < 3.1.0. */
172 if (sctx
->screen
->b
.info
.drm_major
< 3 ||
173 sctx
->screen
->b
.info
.drm_minor
< 1) {
178 si_dump_mmapped_reg(sctx
, f
, R_008008_GRBM_STATUS2
);
179 si_dump_mmapped_reg(sctx
, f
, R_008014_GRBM_STATUS_SE0
);
180 si_dump_mmapped_reg(sctx
, f
, R_008018_GRBM_STATUS_SE1
);
181 si_dump_mmapped_reg(sctx
, f
, R_008038_GRBM_STATUS_SE2
);
182 si_dump_mmapped_reg(sctx
, f
, R_00803C_GRBM_STATUS_SE3
);
183 si_dump_mmapped_reg(sctx
, f
, R_00D034_SDMA0_STATUS_REG
);
184 si_dump_mmapped_reg(sctx
, f
, R_00D834_SDMA1_STATUS_REG
);
185 si_dump_mmapped_reg(sctx
, f
, R_000E50_SRBM_STATUS
);
186 si_dump_mmapped_reg(sctx
, f
, R_000E4C_SRBM_STATUS2
);
187 si_dump_mmapped_reg(sctx
, f
, R_000E54_SRBM_STATUS3
);
188 si_dump_mmapped_reg(sctx
, f
, R_008680_CP_STAT
);
189 si_dump_mmapped_reg(sctx
, f
, R_008674_CP_STALLED_STAT1
);
190 si_dump_mmapped_reg(sctx
, f
, R_008678_CP_STALLED_STAT2
);
191 si_dump_mmapped_reg(sctx
, f
, R_008670_CP_STALLED_STAT3
);
192 si_dump_mmapped_reg(sctx
, f
, R_008210_CP_CPC_STATUS
);
193 si_dump_mmapped_reg(sctx
, f
, R_008214_CP_CPC_BUSY_STAT
);
194 si_dump_mmapped_reg(sctx
, f
, R_008218_CP_CPC_STALLED_STAT1
);
195 si_dump_mmapped_reg(sctx
, f
, R_00821C_CP_CPF_STATUS
);
196 si_dump_mmapped_reg(sctx
, f
, R_008220_CP_CPF_BUSY_STAT
);
197 si_dump_mmapped_reg(sctx
, f
, R_008224_CP_CPF_STALLED_STAT1
);
201 static void si_dump_last_ib(struct si_context
*sctx
, FILE *f
)
203 int last_trace_id
= -1;
205 if (!sctx
->last_gfx
.ib
)
208 if (sctx
->last_trace_buf
) {
209 /* We are expecting that the ddebug pipe has already
210 * waited for the context, so this buffer should be idle.
211 * If the GPU is hung, there is no point in waiting for it.
213 uint32_t *map
= sctx
->b
.ws
->buffer_map(sctx
->last_trace_buf
->buf
,
215 PIPE_TRANSFER_UNSYNCHRONIZED
|
218 last_trace_id
= *map
;
221 if (sctx
->init_config
)
222 ac_parse_ib(f
, sctx
->init_config
->pm4
, sctx
->init_config
->ndw
,
223 -1, "IB2: Init config", sctx
->b
.chip_class
,
226 if (sctx
->init_config_gs_rings
)
227 ac_parse_ib(f
, sctx
->init_config_gs_rings
->pm4
,
228 sctx
->init_config_gs_rings
->ndw
,
229 -1, "IB2: Init GS rings", sctx
->b
.chip_class
,
232 ac_parse_ib(f
, sctx
->last_gfx
.ib
, sctx
->last_gfx
.num_dw
,
233 last_trace_id
, "IB", sctx
->b
.chip_class
,
237 static const char *priority_to_string(enum radeon_bo_priority priority
)
239 #define ITEM(x) [RADEON_PRIO_##x] = #x
240 static const char *table
[64] = {
243 ITEM(SO_FILLED_SIZE
),
257 ITEM(SAMPLER_BUFFER
),
259 ITEM(SHADER_RW_BUFFER
),
260 ITEM(COMPUTE_GLOBAL
),
261 ITEM(SAMPLER_TEXTURE
),
262 ITEM(SHADER_RW_IMAGE
),
263 ITEM(SAMPLER_TEXTURE_MSAA
),
266 ITEM(COLOR_BUFFER_MSAA
),
267 ITEM(DEPTH_BUFFER_MSAA
),
273 ITEM(SCRATCH_BUFFER
),
277 assert(priority
< ARRAY_SIZE(table
));
278 return table
[priority
];
281 static int bo_list_compare_va(const struct radeon_bo_list_item
*a
,
282 const struct radeon_bo_list_item
*b
)
284 return a
->vm_address
< b
->vm_address
? -1 :
285 a
->vm_address
> b
->vm_address
? 1 : 0;
288 static void si_dump_bo_list(struct si_context
*sctx
,
289 const struct radeon_saved_cs
*saved
, FILE *f
)
296 /* Sort the list according to VM adddresses first. */
297 qsort(saved
->bo_list
, saved
->bo_count
,
298 sizeof(saved
->bo_list
[0]), (void*)bo_list_compare_va
);
300 fprintf(f
, "Buffer list (in units of pages = 4kB):\n"
301 COLOR_YELLOW
" Size VM start page "
302 "VM end page Usage" COLOR_RESET
"\n");
304 for (i
= 0; i
< saved
->bo_count
; i
++) {
305 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
306 const unsigned page_size
= sctx
->b
.screen
->info
.gart_page_size
;
307 uint64_t va
= saved
->bo_list
[i
].vm_address
;
308 uint64_t size
= saved
->bo_list
[i
].bo_size
;
311 /* If there's unused virtual memory between 2 buffers, print it. */
313 uint64_t previous_va_end
= saved
->bo_list
[i
-1].vm_address
+
314 saved
->bo_list
[i
-1].bo_size
;
316 if (va
> previous_va_end
) {
317 fprintf(f
, " %10"PRIu64
" -- hole --\n",
318 (va
- previous_va_end
) / page_size
);
322 /* Print the buffer. */
323 fprintf(f
, " %10"PRIu64
" 0x%013"PRIX64
" 0x%013"PRIX64
" ",
324 size
/ page_size
, va
/ page_size
, (va
+ size
) / page_size
);
326 /* Print the usage. */
327 for (j
= 0; j
< 64; j
++) {
328 if (!(saved
->bo_list
[i
].priority_usage
& (1llu << j
)))
331 fprintf(f
, "%s%s", !hit
? "" : ", ", priority_to_string(j
));
336 fprintf(f
, "\nNote: The holes represent memory not used by the IB.\n"
337 " Other buffers can still be allocated there.\n\n");
340 static void si_dump_framebuffer(struct si_context
*sctx
, FILE *f
)
342 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
343 struct r600_texture
*rtex
;
346 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
347 if (!state
->cbufs
[i
])
350 rtex
= (struct r600_texture
*)state
->cbufs
[i
]->texture
;
351 fprintf(f
, COLOR_YELLOW
"Color buffer %i:" COLOR_RESET
"\n", i
);
352 r600_print_texture_info(rtex
, f
);
357 rtex
= (struct r600_texture
*)state
->zsbuf
->texture
;
358 fprintf(f
, COLOR_YELLOW
"Depth-stencil buffer:" COLOR_RESET
"\n");
359 r600_print_texture_info(rtex
, f
);
364 static void si_dump_descriptor_list(struct si_descriptors
*desc
,
365 const char *shader_name
,
366 const char *elem_name
,
367 unsigned num_elements
,
371 uint32_t *cpu_list
= desc
->list
;
372 uint32_t *gpu_list
= desc
->gpu_list
;
373 const char *list_note
= "GPU list";
377 list_note
= "CPU list";
380 for (i
= 0; i
< num_elements
; i
++) {
381 fprintf(f
, COLOR_GREEN
"%s%s slot %u (%s):" COLOR_RESET
"\n",
382 shader_name
, elem_name
, i
, list_note
);
384 switch (desc
->element_dw_size
) {
386 for (j
= 0; j
< 4; j
++)
387 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
388 gpu_list
[j
], 0xffffffff);
391 for (j
= 0; j
< 8; j
++)
392 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
393 gpu_list
[j
], 0xffffffff);
395 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
396 for (j
= 0; j
< 4; j
++)
397 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
398 gpu_list
[4+j
], 0xffffffff);
401 for (j
= 0; j
< 8; j
++)
402 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
403 gpu_list
[j
], 0xffffffff);
405 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
406 for (j
= 0; j
< 4; j
++)
407 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
408 gpu_list
[4+j
], 0xffffffff);
410 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
411 for (j
= 0; j
< 8; j
++)
412 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
413 gpu_list
[8+j
], 0xffffffff);
415 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
416 for (j
= 0; j
< 4; j
++)
417 ac_dump_reg(f
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
*4,
418 gpu_list
[12+j
], 0xffffffff);
422 if (memcmp(gpu_list
, cpu_list
, desc
->element_dw_size
* 4) != 0) {
423 fprintf(f
, COLOR_RED
"!!!!! This slot was corrupted in GPU memory !!!!!"
428 gpu_list
+= desc
->element_dw_size
;
429 cpu_list
+= desc
->element_dw_size
;
433 static void si_dump_descriptors(struct si_context
*sctx
,
434 struct si_shader_ctx_state
*state
,
437 if (!state
->cso
|| !state
->current
)
440 unsigned type
= state
->cso
->type
;
441 const struct tgsi_shader_info
*info
= &state
->cso
->info
;
442 struct si_descriptors
*descs
=
443 &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
+
444 type
* SI_NUM_SHADER_DESCS
];
445 static const char *shader_name
[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
447 static const char *elem_name
[] = {
448 " - Constant buffer",
453 unsigned num_elements
[] = {
454 util_last_bit(info
->const_buffers_declared
),
455 util_last_bit(info
->shader_buffers_declared
),
456 util_last_bit(info
->samplers_declared
),
457 util_last_bit(info
->images_declared
),
460 if (type
== PIPE_SHADER_VERTEX
) {
461 si_dump_descriptor_list(&sctx
->vertex_buffers
, shader_name
[type
],
462 " - Vertex buffer", info
->num_inputs
, f
);
465 for (unsigned i
= 0; i
< SI_NUM_SHADER_DESCS
; ++i
, ++descs
)
466 si_dump_descriptor_list(descs
, shader_name
[type
], elem_name
[i
],
470 struct si_shader_inst
{
471 char text
[160]; /* one disasm line */
472 unsigned offset
; /* instruction offset */
473 unsigned size
; /* instruction size = 4 or 8 */
476 /* Split a disassembly string into lines and add them to the array pointed
477 * to by "instructions". */
478 static void si_add_split_disasm(const char *disasm
,
481 struct si_shader_inst
*instructions
)
483 struct si_shader_inst
*last_inst
= *num
? &instructions
[*num
- 1] : NULL
;
486 while ((next
= strchr(disasm
, '\n'))) {
487 struct si_shader_inst
*inst
= &instructions
[*num
];
488 unsigned len
= next
- disasm
;
490 assert(len
< ARRAY_SIZE(inst
->text
));
491 memcpy(inst
->text
, disasm
, len
);
493 inst
->offset
= last_inst
? last_inst
->offset
+ last_inst
->size
: 0;
495 const char *semicolon
= strchr(disasm
, ';');
497 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
498 inst
->size
= next
- semicolon
> 16 ? 8 : 4;
500 snprintf(inst
->text
+ len
, ARRAY_SIZE(inst
->text
) - len
,
501 " [PC=0x%"PRIx64
", off=%u, size=%u]",
502 start_addr
+ inst
->offset
, inst
->offset
, inst
->size
);
510 #define MAX_WAVES_PER_CHIP (64 * 40)
512 struct si_wave_info
{
513 unsigned se
; /* shader engine */
514 unsigned sh
; /* shader array */
515 unsigned cu
; /* compute unit */
519 uint64_t pc
; /* program counter */
523 bool matched
; /* whether the wave is used by a currently-bound shader */
526 static int compare_wave(const void *p1
, const void *p2
)
528 struct si_wave_info
*w1
= (struct si_wave_info
*)p1
;
529 struct si_wave_info
*w2
= (struct si_wave_info
*)p2
;
531 /* Sort waves according to PC and then SE, SH, CU, etc. */
548 if (w1
->simd
< w2
->simd
)
550 if (w1
->simd
> w2
->simd
)
552 if (w1
->wave
< w2
->wave
)
554 if (w1
->wave
> w2
->wave
)
560 /* Return wave information. "waves" should be a large enough array. */
561 static unsigned si_get_wave_info(struct si_wave_info waves
[MAX_WAVES_PER_CHIP
])
564 unsigned num_waves
= 0;
566 FILE *p
= popen("umr -wa", "r");
570 if (!fgets(line
, sizeof(line
), p
) ||
571 strncmp(line
, "SE", 2) != 0) {
576 while (fgets(line
, sizeof(line
), p
)) {
577 struct si_wave_info
*w
;
578 uint32_t pc_hi
, pc_lo
, exec_hi
, exec_lo
;
580 assert(num_waves
< MAX_WAVES_PER_CHIP
);
581 w
= &waves
[num_waves
];
583 if (sscanf(line
, "%u %u %u %u %u %x %x %x %x %x %x %x",
584 &w
->se
, &w
->sh
, &w
->cu
, &w
->simd
, &w
->wave
,
585 &w
->status
, &pc_hi
, &pc_lo
, &w
->inst_dw0
,
586 &w
->inst_dw1
, &exec_hi
, &exec_lo
) == 12) {
587 w
->pc
= ((uint64_t)pc_hi
<< 32) | pc_lo
;
588 w
->exec
= ((uint64_t)exec_hi
<< 32) | exec_lo
;
594 qsort(waves
, num_waves
, sizeof(struct si_wave_info
), compare_wave
);
600 /* If the shader is being executed, print its asm instructions, and annotate
601 * those that are being executed right now with information about waves that
602 * execute them. This is most useful during a GPU hang.
604 static void si_print_annotated_shader(struct si_shader
*shader
,
605 struct si_wave_info
*waves
,
609 if (!shader
|| !shader
->binary
.disasm_string
)
612 uint64_t start_addr
= shader
->bo
->gpu_address
;
613 uint64_t end_addr
= start_addr
+ shader
->bo
->b
.b
.width0
;
616 /* See if any wave executes the shader. */
617 for (i
= 0; i
< num_waves
; i
++) {
618 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
622 return; /* the shader is not being executed */
624 /* Remember the first found wave. The waves are sorted according to PC. */
628 /* Get the list of instructions.
629 * Buffer size / 4 is the upper bound of the instruction count.
631 unsigned num_inst
= 0;
632 struct si_shader_inst
*instructions
=
633 calloc(shader
->bo
->b
.b
.width0
/ 4, sizeof(struct si_shader_inst
));
635 if (shader
->prolog
) {
636 si_add_split_disasm(shader
->prolog
->binary
.disasm_string
,
637 start_addr
, &num_inst
, instructions
);
639 si_add_split_disasm(shader
->binary
.disasm_string
,
640 start_addr
, &num_inst
, instructions
);
641 if (shader
->epilog
) {
642 si_add_split_disasm(shader
->epilog
->binary
.disasm_string
,
643 start_addr
, &num_inst
, instructions
);
646 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
647 si_get_shader_name(shader
, shader
->selector
->type
));
649 /* Print instructions with annotations. */
650 for (i
= 0; i
< num_inst
; i
++) {
651 struct si_shader_inst
*inst
= &instructions
[i
];
653 fprintf(f
, "%s\n", inst
->text
);
655 /* Print which waves execute the instruction right now. */
656 while (num_waves
&& start_addr
+ inst
->offset
== waves
->pc
) {
658 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
659 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
660 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
661 waves
->wave
, waves
->exec
);
663 if (inst
->size
== 4) {
664 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
667 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
668 waves
->inst_dw0
, waves
->inst_dw1
);
671 waves
->matched
= true;
681 static void si_dump_annotated_shaders(struct si_context
*sctx
, FILE *f
)
683 struct si_wave_info waves
[MAX_WAVES_PER_CHIP
];
684 unsigned num_waves
= si_get_wave_info(waves
);
686 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
689 si_print_annotated_shader(sctx
->vs_shader
.current
, waves
, num_waves
, f
);
690 si_print_annotated_shader(sctx
->tcs_shader
.current
, waves
, num_waves
, f
);
691 si_print_annotated_shader(sctx
->tes_shader
.current
, waves
, num_waves
, f
);
692 si_print_annotated_shader(sctx
->gs_shader
.current
, waves
, num_waves
, f
);
693 si_print_annotated_shader(sctx
->ps_shader
.current
, waves
, num_waves
, f
);
695 /* Print waves executing shaders that are not currently bound. */
698 for (i
= 0; i
< num_waves
; i
++) {
699 if (waves
[i
].matched
)
703 fprintf(f
, COLOR_CYAN
704 "Waves not executing currently-bound shaders:"
708 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
709 " INST=%08X %08X PC=%"PRIx64
"\n",
710 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
711 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
712 waves
[i
].inst_dw1
, waves
[i
].pc
);
718 static void si_dump_command(const char *title
, const char *command
, FILE *f
)
722 FILE *p
= popen(command
, "r");
726 fprintf(f
, COLOR_YELLOW
"%s: " COLOR_RESET
"\n", title
);
727 while (fgets(line
, sizeof(line
), p
))
733 static void si_dump_debug_state(struct pipe_context
*ctx
, FILE *f
,
736 struct si_context
*sctx
= (struct si_context
*)ctx
;
738 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
)
739 si_dump_debug_registers(sctx
, f
);
741 if (flags
& PIPE_DUMP_CURRENT_STATES
)
742 si_dump_framebuffer(sctx
, f
);
744 if (flags
& PIPE_DUMP_CURRENT_SHADERS
) {
745 si_dump_shader(sctx
->screen
, &sctx
->vs_shader
, f
);
746 si_dump_shader(sctx
->screen
, &sctx
->tcs_shader
, f
);
747 si_dump_shader(sctx
->screen
, &sctx
->tes_shader
, f
);
748 si_dump_shader(sctx
->screen
, &sctx
->gs_shader
, f
);
749 si_dump_shader(sctx
->screen
, &sctx
->ps_shader
, f
);
751 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
) {
752 si_dump_annotated_shaders(sctx
, f
);
753 si_dump_command("Active waves (raw data)", "umr -wa | column -t", f
);
754 si_dump_command("Wave information", "umr -O bits -wa", f
);
757 si_dump_descriptor_list(&sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
758 "", "RW buffers", SI_NUM_RW_BUFFERS
, f
);
759 si_dump_descriptors(sctx
, &sctx
->vs_shader
, f
);
760 si_dump_descriptors(sctx
, &sctx
->tcs_shader
, f
);
761 si_dump_descriptors(sctx
, &sctx
->tes_shader
, f
);
762 si_dump_descriptors(sctx
, &sctx
->gs_shader
, f
);
763 si_dump_descriptors(sctx
, &sctx
->ps_shader
, f
);
766 if (flags
& PIPE_DUMP_LAST_COMMAND_BUFFER
) {
767 si_dump_bo_list(sctx
, &sctx
->last_gfx
, f
);
768 si_dump_last_ib(sctx
, f
);
770 fprintf(f
, "Done.\n");
773 radeon_clear_saved_cs(&sctx
->last_gfx
);
774 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
778 static void si_dump_dma(struct si_context
*sctx
,
779 struct radeon_saved_cs
*saved
, FILE *f
)
781 static const char ib_name
[] = "sDMA IB";
784 si_dump_bo_list(sctx
, saved
, f
);
786 fprintf(f
, "------------------ %s begin ------------------\n", ib_name
);
788 for (i
= 0; i
< saved
->num_dw
; ++i
) {
789 fprintf(f
, " %08x\n", saved
->ib
[i
]);
792 fprintf(f
, "------------------- %s end -------------------\n", ib_name
);
795 fprintf(f
, "SDMA Dump Done.\n");
798 static bool si_vm_fault_occured(struct si_context
*sctx
, uint32_t *out_addr
)
803 uint64_t timestamp
= 0;
806 FILE *p
= popen("dmesg", "r");
810 while (fgets(line
, sizeof(line
), p
)) {
813 if (!line
[0] || line
[0] == '\n')
816 /* Get the timestamp. */
817 if (sscanf(line
, "[%u.%u]", &sec
, &usec
) != 2) {
818 static bool hit
= false;
820 fprintf(stderr
, "%s: failed to parse line '%s'\n",
826 timestamp
= sec
* 1000000llu + usec
;
828 /* If just updating the timestamp. */
832 /* Process messages only if the timestamp is newer. */
833 if (timestamp
<= sctx
->dmesg_timestamp
)
836 /* Only process the first VM fault. */
840 /* Remove trailing \n */
842 if (len
&& line
[len
-1] == '\n')
845 /* Get the message part. */
846 msg
= strchr(line
, ']');
855 if (strstr(msg
, "GPU fault detected:"))
859 msg
= strstr(msg
, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
861 msg
= strstr(msg
, "0x");
864 if (sscanf(msg
, "%X", out_addr
) == 1)
876 if (timestamp
> sctx
->dmesg_timestamp
)
877 sctx
->dmesg_timestamp
= timestamp
;
881 void si_check_vm_faults(struct r600_common_context
*ctx
,
882 struct radeon_saved_cs
*saved
, enum ring_type ring
)
884 struct si_context
*sctx
= (struct si_context
*)ctx
;
885 struct pipe_screen
*screen
= sctx
->b
.b
.screen
;
890 if (!si_vm_fault_occured(sctx
, &addr
))
893 f
= dd_get_debug_file(false);
897 fprintf(f
, "VM fault report.\n\n");
898 if (os_get_command_line(cmd_line
, sizeof(cmd_line
)))
899 fprintf(f
, "Command: %s\n", cmd_line
);
900 fprintf(f
, "Driver vendor: %s\n", screen
->get_vendor(screen
));
901 fprintf(f
, "Device vendor: %s\n", screen
->get_device_vendor(screen
));
902 fprintf(f
, "Device name: %s\n\n", screen
->get_name(screen
));
903 fprintf(f
, "Failing VM page: 0x%08x\n\n", addr
);
905 if (sctx
->apitrace_call_number
)
906 fprintf(f
, "Last apitrace call: %u\n\n",
907 sctx
->apitrace_call_number
);
911 si_dump_debug_state(&sctx
->b
.b
, f
,
912 PIPE_DUMP_CURRENT_STATES
|
913 PIPE_DUMP_CURRENT_SHADERS
|
914 PIPE_DUMP_LAST_COMMAND_BUFFER
);
918 si_dump_dma(sctx
, saved
, f
);
927 fprintf(stderr
, "Detected a VM fault, exiting...\n");
931 void si_init_debug_functions(struct si_context
*sctx
)
933 sctx
->b
.b
.dump_debug_state
= si_dump_debug_state
;
934 sctx
->b
.check_vm_faults
= si_check_vm_faults
;
936 /* Set the initial dmesg timestamp for this context, so that
937 * only new messages will be checked for VM faults.
939 if (sctx
->screen
->b
.debug_flags
& DBG_CHECK_VM
)
940 si_vm_fault_occured(sctx
, NULL
);