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[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 r600_resource_reference(&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
241 &desc->buffer_offset,
242 (struct pipe_resource**)&desc->buffer, &ptr);
243 if (!desc->buffer)
244 return false; /* skip the draw call */
245
246 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
247
248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
249 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
250 }
251 desc->pointer_dirty = true;
252 desc->dirty_mask = 0;
253
254 if (atom)
255 si_mark_atom_dirty(sctx, atom);
256
257 return true;
258 }
259
260 static void
261 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
262 {
263 desc->ce_ram_dirty = true;
264
265 if (!desc->buffer)
266 return;
267
268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
269 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
270 }
271
272 /* SAMPLER VIEWS */
273
274 static unsigned
275 si_sampler_descriptors_idx(unsigned shader)
276 {
277 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
278 SI_SHADER_DESCS_SAMPLERS;
279 }
280
281 static struct si_descriptors *
282 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
283 {
284 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
285 }
286
287 static void si_release_sampler_views(struct si_sampler_views *views)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
292 pipe_sampler_view_reference(&views->views[i], NULL);
293 }
294 }
295
296 static void si_sampler_view_add_buffer(struct si_context *sctx,
297 struct pipe_resource *resource,
298 enum radeon_bo_usage usage,
299 bool is_stencil_sampler,
300 bool check_mem)
301 {
302 struct r600_resource *rres;
303 struct r600_texture *rtex;
304 enum radeon_bo_priority priority;
305
306 if (!resource)
307 return;
308
309 if (resource->target != PIPE_BUFFER) {
310 struct r600_texture *tex = (struct r600_texture*)resource;
311
312 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
313 resource = &tex->flushed_depth_texture->resource.b.b;
314 }
315
316 rres = (struct r600_resource*)resource;
317 priority = r600_get_sampler_view_priority(rres);
318
319 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
320 rres, usage, priority,
321 check_mem);
322
323 if (resource->target == PIPE_BUFFER)
324 return;
325
326 /* Now add separate DCC if it's present. */
327 rtex = (struct r600_texture*)resource;
328 if (!rtex->dcc_separate_buffer)
329 return;
330
331 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
332 rtex->dcc_separate_buffer, usage,
333 RADEON_PRIO_DCC, check_mem);
334 }
335
336 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
337 struct si_sampler_views *views)
338 {
339 unsigned mask = views->enabled_mask;
340
341 /* Add buffers to the CS. */
342 while (mask) {
343 int i = u_bit_scan(&mask);
344 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
345
346 si_sampler_view_add_buffer(sctx, sview->base.texture,
347 RADEON_USAGE_READ,
348 sview->is_stencil_sampler, false);
349 }
350 }
351
352 /* Set texture descriptor fields that can be changed by reallocations.
353 *
354 * \param tex texture
355 * \param base_level_info information of the level of BASE_ADDRESS
356 * \param base_level the level of BASE_ADDRESS
357 * \param first_level pipe_sampler_view.u.tex.first_level
358 * \param block_width util_format_get_blockwidth()
359 * \param is_stencil select between separate Z & Stencil
360 * \param state descriptor to update
361 */
362 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
363 const struct radeon_surf_level *base_level_info,
364 unsigned base_level, unsigned first_level,
365 unsigned block_width, bool is_stencil,
366 uint32_t *state)
367 {
368 uint64_t va;
369 unsigned pitch = base_level_info->nblk_x * block_width;
370
371 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
372 tex = tex->flushed_depth_texture;
373 is_stencil = false;
374 }
375
376 va = tex->resource.gpu_address + base_level_info->offset;
377
378 state[1] &= C_008F14_BASE_ADDRESS_HI;
379 state[3] &= C_008F1C_TILING_INDEX;
380 state[4] &= C_008F20_PITCH;
381 state[6] &= C_008F28_COMPRESSION_EN;
382
383 state[0] = va >> 8;
384 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
385 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
386 is_stencil));
387 state[4] |= S_008F20_PITCH(pitch - 1);
388
389 if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
390 state[6] |= S_008F28_COMPRESSION_EN(1);
391 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
392 tex->dcc_offset +
393 base_level_info->dcc_offset) >> 8;
394 }
395 }
396
397 static void si_set_sampler_view(struct si_context *sctx,
398 unsigned shader,
399 unsigned slot, struct pipe_sampler_view *view,
400 bool disallow_early_out)
401 {
402 struct si_sampler_views *views = &sctx->samplers[shader].views;
403 struct si_sampler_view *rview = (struct si_sampler_view*)view;
404 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
405
406 if (views->views[slot] == view && !disallow_early_out)
407 return;
408
409 if (view) {
410 struct r600_texture *rtex = (struct r600_texture *)view->texture;
411 uint32_t *desc = descs->list + slot * 16;
412
413 assert(rtex); /* views with texture == NULL aren't supported */
414 pipe_sampler_view_reference(&views->views[slot], view);
415 memcpy(desc, rview->state, 8*4);
416
417 if (rtex->resource.b.b.target == PIPE_BUFFER) {
418 rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
419 } else {
420 bool is_separate_stencil =
421 rtex->db_compatible &&
422 rview->is_stencil_sampler;
423
424 si_set_mutable_tex_desc_fields(rtex,
425 rview->base_level_info,
426 rview->base_level,
427 rview->base.u.tex.first_level,
428 rview->block_width,
429 is_separate_stencil,
430 desc);
431 }
432
433 if (rtex->resource.b.b.target != PIPE_BUFFER &&
434 rtex->fmask.size) {
435 memcpy(desc + 8,
436 rview->fmask_state, 8*4);
437 } else {
438 /* Disable FMASK and bind sampler state in [12:15]. */
439 memcpy(desc + 8,
440 null_texture_descriptor, 4*4);
441
442 if (views->sampler_states[slot])
443 memcpy(desc + 12,
444 views->sampler_states[slot], 4*4);
445 }
446
447 views->enabled_mask |= 1u << slot;
448
449 /* Since this can flush, it must be done after enabled_mask is
450 * updated. */
451 si_sampler_view_add_buffer(sctx, view->texture,
452 RADEON_USAGE_READ,
453 rview->is_stencil_sampler, true);
454 } else {
455 pipe_sampler_view_reference(&views->views[slot], NULL);
456 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
457 /* Only clear the lower dwords of FMASK. */
458 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
459 views->enabled_mask &= ~(1u << slot);
460 }
461
462 descs->dirty_mask |= 1u << slot;
463 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
464 }
465
466 static bool is_compressed_colortex(struct r600_texture *rtex)
467 {
468 return rtex->cmask.size || rtex->fmask.size ||
469 (rtex->dcc_offset && rtex->dirty_level_mask);
470 }
471
472 static void si_set_sampler_views(struct pipe_context *ctx,
473 enum pipe_shader_type shader, unsigned start,
474 unsigned count,
475 struct pipe_sampler_view **views)
476 {
477 struct si_context *sctx = (struct si_context *)ctx;
478 struct si_textures_info *samplers = &sctx->samplers[shader];
479 int i;
480
481 if (!count || shader >= SI_NUM_SHADERS)
482 return;
483
484 for (i = 0; i < count; i++) {
485 unsigned slot = start + i;
486
487 if (!views || !views[i]) {
488 samplers->depth_texture_mask &= ~(1u << slot);
489 samplers->compressed_colortex_mask &= ~(1u << slot);
490 si_set_sampler_view(sctx, shader, slot, NULL, false);
491 continue;
492 }
493
494 si_set_sampler_view(sctx, shader, slot, views[i], false);
495
496 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
497 struct r600_texture *rtex =
498 (struct r600_texture*)views[i]->texture;
499
500 if (rtex->db_compatible) {
501 samplers->depth_texture_mask |= 1u << slot;
502 } else {
503 samplers->depth_texture_mask &= ~(1u << slot);
504 }
505 if (is_compressed_colortex(rtex)) {
506 samplers->compressed_colortex_mask |= 1u << slot;
507 } else {
508 samplers->compressed_colortex_mask &= ~(1u << slot);
509 }
510
511 if (rtex->dcc_offset &&
512 p_atomic_read(&rtex->framebuffers_bound))
513 sctx->need_check_render_feedback = true;
514 } else {
515 samplers->depth_texture_mask &= ~(1u << slot);
516 samplers->compressed_colortex_mask &= ~(1u << slot);
517 }
518 }
519 }
520
521 static void
522 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
523 {
524 unsigned mask = samplers->views.enabled_mask;
525
526 while (mask) {
527 int i = u_bit_scan(&mask);
528 struct pipe_resource *res = samplers->views.views[i]->texture;
529
530 if (res && res->target != PIPE_BUFFER) {
531 struct r600_texture *rtex = (struct r600_texture *)res;
532
533 if (is_compressed_colortex(rtex)) {
534 samplers->compressed_colortex_mask |= 1u << i;
535 } else {
536 samplers->compressed_colortex_mask &= ~(1u << i);
537 }
538 }
539 }
540 }
541
542 /* IMAGE VIEWS */
543
544 static unsigned
545 si_image_descriptors_idx(unsigned shader)
546 {
547 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
548 SI_SHADER_DESCS_IMAGES;
549 }
550
551 static struct si_descriptors*
552 si_image_descriptors(struct si_context *sctx, unsigned shader)
553 {
554 return &sctx->descriptors[si_image_descriptors_idx(shader)];
555 }
556
557 static void
558 si_release_image_views(struct si_images_info *images)
559 {
560 unsigned i;
561
562 for (i = 0; i < SI_NUM_IMAGES; ++i) {
563 struct pipe_image_view *view = &images->views[i];
564
565 pipe_resource_reference(&view->resource, NULL);
566 }
567 }
568
569 static void
570 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
571 {
572 uint mask = images->enabled_mask;
573
574 /* Add buffers to the CS. */
575 while (mask) {
576 int i = u_bit_scan(&mask);
577 struct pipe_image_view *view = &images->views[i];
578
579 assert(view->resource);
580
581 si_sampler_view_add_buffer(sctx, view->resource,
582 RADEON_USAGE_READWRITE, false, false);
583 }
584 }
585
586 static void
587 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
588 {
589 struct si_images_info *images = &ctx->images[shader];
590
591 if (images->enabled_mask & (1u << slot)) {
592 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
593
594 pipe_resource_reference(&images->views[slot].resource, NULL);
595 images->compressed_colortex_mask &= ~(1 << slot);
596
597 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
598 images->enabled_mask &= ~(1u << slot);
599 descs->dirty_mask |= 1u << slot;
600 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
601 }
602 }
603
604 static void
605 si_mark_image_range_valid(const struct pipe_image_view *view)
606 {
607 struct r600_resource *res = (struct r600_resource *)view->resource;
608
609 assert(res && res->b.b.target == PIPE_BUFFER);
610
611 util_range_add(&res->valid_buffer_range,
612 view->u.buf.offset,
613 view->u.buf.offset + view->u.buf.size);
614 }
615
616 static void si_set_shader_image(struct si_context *ctx,
617 unsigned shader,
618 unsigned slot, const struct pipe_image_view *view)
619 {
620 struct si_screen *screen = ctx->screen;
621 struct si_images_info *images = &ctx->images[shader];
622 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
623 struct r600_resource *res;
624
625 if (!view || !view->resource) {
626 si_disable_shader_image(ctx, shader, slot);
627 return;
628 }
629
630 res = (struct r600_resource *)view->resource;
631
632 if (&images->views[slot] != view)
633 util_copy_image_view(&images->views[slot], view);
634
635 if (res->b.b.target == PIPE_BUFFER) {
636 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
637 si_mark_image_range_valid(view);
638
639 si_make_buffer_descriptor(screen, res,
640 view->format,
641 view->u.buf.offset,
642 view->u.buf.size,
643 descs->list + slot * 8);
644 images->compressed_colortex_mask &= ~(1 << slot);
645 res->bind_history |= PIPE_BIND_SHADER_IMAGE;
646 } else {
647 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
648 struct r600_texture *tex = (struct r600_texture *)res;
649 unsigned level = view->u.tex.level;
650 unsigned width, height, depth;
651 uint32_t *desc = descs->list + slot * 8;
652 bool uses_dcc = tex->dcc_offset &&
653 tex->surface.level[level].dcc_enabled;
654
655 assert(!tex->is_depth);
656 assert(tex->fmask.size == 0);
657
658 if (uses_dcc &&
659 (view->access & PIPE_IMAGE_ACCESS_WRITE ||
660 !vi_dcc_formats_compatible(res->b.b.format, view->format))) {
661 /* If DCC can't be disabled, at least decompress it.
662 * The decompression is relatively cheap if the surface
663 * has been decompressed already.
664 */
665 if (r600_texture_disable_dcc(&ctx->b, tex))
666 uses_dcc = false;
667 else
668 ctx->b.decompress_dcc(&ctx->b.b, tex);
669 }
670
671 if (is_compressed_colortex(tex)) {
672 images->compressed_colortex_mask |= 1 << slot;
673 } else {
674 images->compressed_colortex_mask &= ~(1 << slot);
675 }
676
677 if (uses_dcc &&
678 p_atomic_read(&tex->framebuffers_bound))
679 ctx->need_check_render_feedback = true;
680
681 /* Always force the base level to the selected level.
682 *
683 * This is required for 3D textures, where otherwise
684 * selecting a single slice for non-layered bindings
685 * fails. It doesn't hurt the other targets.
686 */
687 width = u_minify(res->b.b.width0, level);
688 height = u_minify(res->b.b.height0, level);
689 depth = u_minify(res->b.b.depth0, level);
690
691 si_make_texture_descriptor(screen, tex,
692 false, res->b.b.target,
693 view->format, swizzle,
694 0, 0,
695 view->u.tex.first_layer,
696 view->u.tex.last_layer,
697 width, height, depth,
698 desc, NULL);
699 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
700 level, level,
701 util_format_get_blockwidth(view->format),
702 false, desc);
703 }
704
705 images->enabled_mask |= 1u << slot;
706 descs->dirty_mask |= 1u << slot;
707 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
708
709 /* Since this can flush, it must be done after enabled_mask is updated. */
710 si_sampler_view_add_buffer(ctx, &res->b.b,
711 RADEON_USAGE_READWRITE, false, true);
712 }
713
714 static void
715 si_set_shader_images(struct pipe_context *pipe,
716 enum pipe_shader_type shader,
717 unsigned start_slot, unsigned count,
718 const struct pipe_image_view *views)
719 {
720 struct si_context *ctx = (struct si_context *)pipe;
721 unsigned i, slot;
722
723 assert(shader < SI_NUM_SHADERS);
724
725 if (!count)
726 return;
727
728 assert(start_slot + count <= SI_NUM_IMAGES);
729
730 if (views) {
731 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
732 si_set_shader_image(ctx, shader, slot, &views[i]);
733 } else {
734 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
735 si_set_shader_image(ctx, shader, slot, NULL);
736 }
737 }
738
739 static void
740 si_images_update_compressed_colortex_mask(struct si_images_info *images)
741 {
742 unsigned mask = images->enabled_mask;
743
744 while (mask) {
745 int i = u_bit_scan(&mask);
746 struct pipe_resource *res = images->views[i].resource;
747
748 if (res && res->target != PIPE_BUFFER) {
749 struct r600_texture *rtex = (struct r600_texture *)res;
750
751 if (is_compressed_colortex(rtex)) {
752 images->compressed_colortex_mask |= 1 << i;
753 } else {
754 images->compressed_colortex_mask &= ~(1 << i);
755 }
756 }
757 }
758 }
759
760 /* SAMPLER STATES */
761
762 static void si_bind_sampler_states(struct pipe_context *ctx,
763 enum pipe_shader_type shader,
764 unsigned start, unsigned count, void **states)
765 {
766 struct si_context *sctx = (struct si_context *)ctx;
767 struct si_textures_info *samplers = &sctx->samplers[shader];
768 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
769 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
770 int i;
771
772 if (!count || shader >= SI_NUM_SHADERS)
773 return;
774
775 for (i = 0; i < count; i++) {
776 unsigned slot = start + i;
777
778 if (!sstates[i] ||
779 sstates[i] == samplers->views.sampler_states[slot])
780 continue;
781
782 samplers->views.sampler_states[slot] = sstates[i];
783
784 /* If FMASK is bound, don't overwrite it.
785 * The sampler state will be set after FMASK is unbound.
786 */
787 if (samplers->views.views[i] &&
788 samplers->views.views[i]->texture &&
789 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
790 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
791 continue;
792
793 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
794 desc->dirty_mask |= 1u << slot;
795 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
796 }
797 }
798
799 /* BUFFER RESOURCES */
800
801 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
802 struct si_descriptors *descs,
803 unsigned num_buffers,
804 unsigned shader_userdata_index,
805 enum radeon_bo_usage shader_usage,
806 enum radeon_bo_priority priority,
807 unsigned *ce_offset)
808 {
809 buffers->shader_usage = shader_usage;
810 buffers->priority = priority;
811 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
812
813 si_init_descriptors(descs, shader_userdata_index, 4,
814 num_buffers, NULL, ce_offset);
815 }
816
817 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
818 struct si_descriptors *descs)
819 {
820 int i;
821
822 for (i = 0; i < descs->num_elements; i++) {
823 pipe_resource_reference(&buffers->buffers[i], NULL);
824 }
825
826 FREE(buffers->buffers);
827 }
828
829 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
830 struct si_buffer_resources *buffers)
831 {
832 unsigned mask = buffers->enabled_mask;
833
834 /* Add buffers to the CS. */
835 while (mask) {
836 int i = u_bit_scan(&mask);
837
838 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
839 (struct r600_resource*)buffers->buffers[i],
840 buffers->shader_usage, buffers->priority);
841 }
842 }
843
844 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
845 struct si_descriptors *descs,
846 unsigned idx, struct pipe_resource **buf,
847 unsigned *offset, unsigned *size)
848 {
849 pipe_resource_reference(buf, buffers->buffers[idx]);
850 if (*buf) {
851 struct r600_resource *res = r600_resource(*buf);
852 const uint32_t *desc = descs->list + idx * 4;
853 uint64_t va;
854
855 *size = desc[2];
856
857 assert(G_008F04_STRIDE(desc[1]) == 0);
858 va = ((uint64_t)desc[1] << 32) | desc[0];
859
860 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
861 *offset = va - res->gpu_address;
862 }
863 }
864
865 /* VERTEX BUFFERS */
866
867 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
868 {
869 struct si_descriptors *desc = &sctx->vertex_buffers;
870 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
871 int i;
872
873 for (i = 0; i < count; i++) {
874 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
875
876 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
877 continue;
878 if (!sctx->vertex_buffer[vb].buffer)
879 continue;
880
881 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
882 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
883 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
884 }
885
886 if (!desc->buffer)
887 return;
888 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
889 desc->buffer, RADEON_USAGE_READ,
890 RADEON_PRIO_DESCRIPTORS);
891 }
892
893 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
894 {
895 struct si_descriptors *desc = &sctx->vertex_buffers;
896 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
897 unsigned i, count = sctx->vertex_elements->count;
898 uint64_t va;
899 uint32_t *ptr;
900
901 if (!sctx->vertex_buffers_dirty)
902 return true;
903 if (!count || !sctx->vertex_elements)
904 return true;
905
906 /* Vertex buffer descriptors are the only ones which are uploaded
907 * directly through a staging buffer and don't go through
908 * the fine-grained upload path.
909 */
910 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
911 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
912 if (!desc->buffer)
913 return false;
914
915 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
916 desc->buffer, RADEON_USAGE_READ,
917 RADEON_PRIO_DESCRIPTORS);
918
919 assert(count <= SI_NUM_VERTEX_BUFFERS);
920
921 for (i = 0; i < count; i++) {
922 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
923 struct pipe_vertex_buffer *vb;
924 struct r600_resource *rbuffer;
925 unsigned offset;
926 uint32_t *desc = &ptr[i*4];
927
928 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
929 memset(desc, 0, 16);
930 continue;
931 }
932
933 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
934 rbuffer = (struct r600_resource*)vb->buffer;
935 if (!rbuffer) {
936 memset(desc, 0, 16);
937 continue;
938 }
939
940 offset = vb->buffer_offset + ve->src_offset;
941 va = rbuffer->gpu_address + offset;
942
943 /* Fill in T# buffer resource description */
944 desc[0] = va;
945 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
946 S_008F04_STRIDE(vb->stride);
947
948 if (sctx->b.chip_class <= CIK && vb->stride)
949 /* Round up by rounding down and adding 1 */
950 desc[2] = (vb->buffer->width0 - offset -
951 sctx->vertex_elements->format_size[i]) /
952 vb->stride + 1;
953 else
954 desc[2] = vb->buffer->width0 - offset;
955
956 desc[3] = sctx->vertex_elements->rsrc_word3[i];
957
958 if (!bound[ve->vertex_buffer_index]) {
959 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
960 (struct r600_resource*)vb->buffer,
961 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
962 bound[ve->vertex_buffer_index] = true;
963 }
964 }
965
966 /* Don't flush the const cache. It would have a very negative effect
967 * on performance (confirmed by testing). New descriptors are always
968 * uploaded to a fresh new buffer, so I don't think flushing the const
969 * cache is needed. */
970 desc->pointer_dirty = true;
971 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
972 sctx->vertex_buffers_dirty = false;
973 return true;
974 }
975
976
977 /* CONSTANT BUFFERS */
978
979 static unsigned
980 si_const_buffer_descriptors_idx(unsigned shader)
981 {
982 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
983 SI_SHADER_DESCS_CONST_BUFFERS;
984 }
985
986 static struct si_descriptors *
987 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
988 {
989 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
990 }
991
992 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
993 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
994 {
995 void *tmp;
996
997 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
998 (struct pipe_resource**)rbuffer, &tmp);
999 if (*rbuffer)
1000 util_memcpy_cpu_to_le32(tmp, ptr, size);
1001 }
1002
1003 static void si_set_constant_buffer(struct si_context *sctx,
1004 struct si_buffer_resources *buffers,
1005 unsigned descriptors_idx,
1006 uint slot, const struct pipe_constant_buffer *input)
1007 {
1008 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1009 assert(slot < descs->num_elements);
1010 pipe_resource_reference(&buffers->buffers[slot], NULL);
1011
1012 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1013 * with a NULL buffer). We need to use a dummy buffer instead. */
1014 if (sctx->b.chip_class == CIK &&
1015 (!input || (!input->buffer && !input->user_buffer)))
1016 input = &sctx->null_const_buf;
1017
1018 if (input && (input->buffer || input->user_buffer)) {
1019 struct pipe_resource *buffer = NULL;
1020 uint64_t va;
1021
1022 /* Upload the user buffer if needed. */
1023 if (input->user_buffer) {
1024 unsigned buffer_offset;
1025
1026 si_upload_const_buffer(sctx,
1027 (struct r600_resource**)&buffer, input->user_buffer,
1028 input->buffer_size, &buffer_offset);
1029 if (!buffer) {
1030 /* Just unbind on failure. */
1031 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1032 return;
1033 }
1034 va = r600_resource(buffer)->gpu_address + buffer_offset;
1035 } else {
1036 pipe_resource_reference(&buffer, input->buffer);
1037 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1038 /* Only track usage for non-user buffers. */
1039 r600_resource(buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
1040 }
1041
1042 /* Set the descriptor. */
1043 uint32_t *desc = descs->list + slot*4;
1044 desc[0] = va;
1045 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1046 S_008F04_STRIDE(0);
1047 desc[2] = input->buffer_size;
1048 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1049 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1050 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1051 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1052 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1053 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1054
1055 buffers->buffers[slot] = buffer;
1056 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1057 (struct r600_resource*)buffer,
1058 buffers->shader_usage,
1059 buffers->priority, true);
1060 buffers->enabled_mask |= 1u << slot;
1061 } else {
1062 /* Clear the descriptor. */
1063 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1064 buffers->enabled_mask &= ~(1u << slot);
1065 }
1066
1067 descs->dirty_mask |= 1u << slot;
1068 sctx->descriptors_dirty |= 1u << descriptors_idx;
1069 }
1070
1071 void si_set_rw_buffer(struct si_context *sctx,
1072 uint slot, const struct pipe_constant_buffer *input)
1073 {
1074 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1075 SI_DESCS_RW_BUFFERS, slot, input);
1076 }
1077
1078 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1079 uint shader, uint slot,
1080 const struct pipe_constant_buffer *input)
1081 {
1082 struct si_context *sctx = (struct si_context *)ctx;
1083
1084 if (shader >= SI_NUM_SHADERS)
1085 return;
1086
1087 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1088 si_const_buffer_descriptors_idx(shader),
1089 slot, input);
1090 }
1091
1092 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
1093 uint slot, struct pipe_constant_buffer *cbuf)
1094 {
1095 cbuf->user_buffer = NULL;
1096 si_get_buffer_from_descriptors(
1097 &sctx->const_buffers[shader],
1098 si_const_buffer_descriptors(sctx, shader),
1099 slot, &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1100 }
1101
1102 /* SHADER BUFFERS */
1103
1104 static unsigned
1105 si_shader_buffer_descriptors_idx(enum pipe_shader_type shader)
1106 {
1107 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1108 SI_SHADER_DESCS_SHADER_BUFFERS;
1109 }
1110
1111 static struct si_descriptors *
1112 si_shader_buffer_descriptors(struct si_context *sctx,
1113 enum pipe_shader_type shader)
1114 {
1115 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1116 }
1117
1118 static void si_set_shader_buffers(struct pipe_context *ctx,
1119 enum pipe_shader_type shader,
1120 unsigned start_slot, unsigned count,
1121 const struct pipe_shader_buffer *sbuffers)
1122 {
1123 struct si_context *sctx = (struct si_context *)ctx;
1124 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1125 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1126 unsigned i;
1127
1128 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1129
1130 for (i = 0; i < count; ++i) {
1131 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1132 struct r600_resource *buf;
1133 unsigned slot = start_slot + i;
1134 uint32_t *desc = descs->list + slot * 4;
1135 uint64_t va;
1136
1137 if (!sbuffer || !sbuffer->buffer) {
1138 pipe_resource_reference(&buffers->buffers[slot], NULL);
1139 memset(desc, 0, sizeof(uint32_t) * 4);
1140 buffers->enabled_mask &= ~(1u << slot);
1141 descs->dirty_mask |= 1u << slot;
1142 sctx->descriptors_dirty |=
1143 1u << si_shader_buffer_descriptors_idx(shader);
1144 continue;
1145 }
1146
1147 buf = (struct r600_resource *)sbuffer->buffer;
1148 va = buf->gpu_address + sbuffer->buffer_offset;
1149
1150 desc[0] = va;
1151 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1152 S_008F04_STRIDE(0);
1153 desc[2] = sbuffer->buffer_size;
1154 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1155 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1156 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1157 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1158 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1159 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1160
1161 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1162 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
1163 buffers->shader_usage,
1164 buffers->priority, true);
1165 buf->bind_history |= PIPE_BIND_SHADER_BUFFER;
1166
1167 buffers->enabled_mask |= 1u << slot;
1168 descs->dirty_mask |= 1u << slot;
1169 sctx->descriptors_dirty |=
1170 1u << si_shader_buffer_descriptors_idx(shader);
1171 }
1172 }
1173
1174 void si_get_shader_buffers(struct si_context *sctx, uint shader,
1175 uint start_slot, uint count,
1176 struct pipe_shader_buffer *sbuf)
1177 {
1178 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1179 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1180
1181 for (unsigned i = 0; i < count; ++i) {
1182 si_get_buffer_from_descriptors(
1183 buffers, descs, start_slot + i,
1184 &sbuf[i].buffer, &sbuf[i].buffer_offset,
1185 &sbuf[i].buffer_size);
1186 }
1187 }
1188
1189 /* RING BUFFERS */
1190
1191 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1192 struct pipe_resource *buffer,
1193 unsigned stride, unsigned num_records,
1194 bool add_tid, bool swizzle,
1195 unsigned element_size, unsigned index_stride, uint64_t offset)
1196 {
1197 struct si_context *sctx = (struct si_context *)ctx;
1198 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1199 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1200
1201 /* The stride field in the resource descriptor has 14 bits */
1202 assert(stride < (1 << 14));
1203
1204 assert(slot < descs->num_elements);
1205 pipe_resource_reference(&buffers->buffers[slot], NULL);
1206
1207 if (buffer) {
1208 uint64_t va;
1209
1210 va = r600_resource(buffer)->gpu_address + offset;
1211
1212 switch (element_size) {
1213 default:
1214 assert(!"Unsupported ring buffer element size");
1215 case 0:
1216 case 2:
1217 element_size = 0;
1218 break;
1219 case 4:
1220 element_size = 1;
1221 break;
1222 case 8:
1223 element_size = 2;
1224 break;
1225 case 16:
1226 element_size = 3;
1227 break;
1228 }
1229
1230 switch (index_stride) {
1231 default:
1232 assert(!"Unsupported ring buffer index stride");
1233 case 0:
1234 case 8:
1235 index_stride = 0;
1236 break;
1237 case 16:
1238 index_stride = 1;
1239 break;
1240 case 32:
1241 index_stride = 2;
1242 break;
1243 case 64:
1244 index_stride = 3;
1245 break;
1246 }
1247
1248 if (sctx->b.chip_class >= VI && stride)
1249 num_records *= stride;
1250
1251 /* Set the descriptor. */
1252 uint32_t *desc = descs->list + slot*4;
1253 desc[0] = va;
1254 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1255 S_008F04_STRIDE(stride) |
1256 S_008F04_SWIZZLE_ENABLE(swizzle);
1257 desc[2] = num_records;
1258 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1259 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1260 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1261 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1262 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1263 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1264 S_008F0C_ELEMENT_SIZE(element_size) |
1265 S_008F0C_INDEX_STRIDE(index_stride) |
1266 S_008F0C_ADD_TID_ENABLE(add_tid);
1267
1268 pipe_resource_reference(&buffers->buffers[slot], buffer);
1269 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1270 (struct r600_resource*)buffer,
1271 buffers->shader_usage, buffers->priority);
1272 buffers->enabled_mask |= 1u << slot;
1273 } else {
1274 /* Clear the descriptor. */
1275 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1276 buffers->enabled_mask &= ~(1u << slot);
1277 }
1278
1279 descs->dirty_mask |= 1u << slot;
1280 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1281 }
1282
1283 /* STREAMOUT BUFFERS */
1284
1285 static void si_set_streamout_targets(struct pipe_context *ctx,
1286 unsigned num_targets,
1287 struct pipe_stream_output_target **targets,
1288 const unsigned *offsets)
1289 {
1290 struct si_context *sctx = (struct si_context *)ctx;
1291 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1292 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1293 unsigned old_num_targets = sctx->b.streamout.num_targets;
1294 unsigned i, bufidx;
1295
1296 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1297 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1298 /* Since streamout uses vector writes which go through TC L2
1299 * and most other clients can use TC L2 as well, we don't need
1300 * to flush it.
1301 *
1302 * The only cases which requires flushing it is VGT DMA index
1303 * fetching (on <= CIK) and indirect draw data, which are rare
1304 * cases. Thus, flag the TC L2 dirtiness in the resource and
1305 * handle it at draw call time.
1306 */
1307 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1308 if (sctx->b.streamout.targets[i])
1309 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1310
1311 /* Invalidate the scalar cache in case a streamout buffer is
1312 * going to be used as a constant buffer.
1313 *
1314 * Invalidate TC L1, because streamout bypasses it (done by
1315 * setting GLC=1 in the store instruction), but it can contain
1316 * outdated data of streamout buffers.
1317 *
1318 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1319 * used as an input immediately.
1320 */
1321 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1322 SI_CONTEXT_INV_VMEM_L1 |
1323 SI_CONTEXT_VS_PARTIAL_FLUSH;
1324 }
1325
1326 /* All readers of the streamout targets need to be finished before we can
1327 * start writing to the targets.
1328 */
1329 if (num_targets)
1330 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1331 SI_CONTEXT_CS_PARTIAL_FLUSH;
1332
1333 /* Streamout buffers must be bound in 2 places:
1334 * 1) in VGT by setting the VGT_STRMOUT registers
1335 * 2) as shader resources
1336 */
1337
1338 /* Set the VGT regs. */
1339 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1340
1341 /* Set the shader resources.*/
1342 for (i = 0; i < num_targets; i++) {
1343 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1344
1345 if (targets[i]) {
1346 struct pipe_resource *buffer = targets[i]->buffer;
1347 uint64_t va = r600_resource(buffer)->gpu_address;
1348
1349 /* Set the descriptor.
1350 *
1351 * On VI, the format must be non-INVALID, otherwise
1352 * the buffer will be considered not bound and store
1353 * instructions will be no-ops.
1354 */
1355 uint32_t *desc = descs->list + bufidx*4;
1356 desc[0] = va;
1357 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1358 desc[2] = 0xffffffff;
1359 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1360 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1361 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1362 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1363 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1364
1365 /* Set the resource. */
1366 pipe_resource_reference(&buffers->buffers[bufidx],
1367 buffer);
1368 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1369 (struct r600_resource*)buffer,
1370 buffers->shader_usage,
1371 RADEON_PRIO_SHADER_RW_BUFFER,
1372 true);
1373 r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
1374
1375 buffers->enabled_mask |= 1u << bufidx;
1376 } else {
1377 /* Clear the descriptor and unset the resource. */
1378 memset(descs->list + bufidx*4, 0,
1379 sizeof(uint32_t) * 4);
1380 pipe_resource_reference(&buffers->buffers[bufidx],
1381 NULL);
1382 buffers->enabled_mask &= ~(1u << bufidx);
1383 }
1384 descs->dirty_mask |= 1u << bufidx;
1385 }
1386 for (; i < old_num_targets; i++) {
1387 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1388 /* Clear the descriptor and unset the resource. */
1389 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1390 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1391 buffers->enabled_mask &= ~(1u << bufidx);
1392 descs->dirty_mask |= 1u << bufidx;
1393 }
1394
1395 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1396 }
1397
1398 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1399 uint32_t *desc, uint64_t old_buf_va,
1400 struct pipe_resource *new_buf)
1401 {
1402 /* Retrieve the buffer offset from the descriptor. */
1403 uint64_t old_desc_va =
1404 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1405
1406 assert(old_buf_va <= old_desc_va);
1407 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1408
1409 /* Update the descriptor. */
1410 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1411
1412 desc[0] = va;
1413 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1414 S_008F04_BASE_ADDRESS_HI(va >> 32);
1415 }
1416
1417 /* INTERNAL CONST BUFFERS */
1418
1419 static void si_set_polygon_stipple(struct pipe_context *ctx,
1420 const struct pipe_poly_stipple *state)
1421 {
1422 struct si_context *sctx = (struct si_context *)ctx;
1423 struct pipe_constant_buffer cb = {};
1424 unsigned stipple[32];
1425 int i;
1426
1427 for (i = 0; i < 32; i++)
1428 stipple[i] = util_bitreverse(state->stipple[i]);
1429
1430 cb.user_buffer = stipple;
1431 cb.buffer_size = sizeof(stipple);
1432
1433 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1434 }
1435
1436 /* TEXTURE METADATA ENABLE/DISABLE */
1437
1438 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1439 * while the texture is bound, possibly by a different context. In that case,
1440 * call this function to update compressed_colortex_masks.
1441 */
1442 void si_update_compressed_colortex_masks(struct si_context *sctx)
1443 {
1444 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1445 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1446 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1447 }
1448 }
1449
1450 /* BUFFER DISCARD/INVALIDATION */
1451
1452 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1453 static void si_reset_buffer_resources(struct si_context *sctx,
1454 struct si_buffer_resources *buffers,
1455 unsigned descriptors_idx,
1456 struct pipe_resource *buf,
1457 uint64_t old_va)
1458 {
1459 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1460 unsigned mask = buffers->enabled_mask;
1461
1462 while (mask) {
1463 unsigned i = u_bit_scan(&mask);
1464 if (buffers->buffers[i] == buf) {
1465 si_desc_reset_buffer_offset(&sctx->b.b,
1466 descs->list + i*4,
1467 old_va, buf);
1468 descs->dirty_mask |= 1u << i;
1469 sctx->descriptors_dirty |= 1u << descriptors_idx;
1470
1471 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1472 (struct r600_resource *)buf,
1473 buffers->shader_usage,
1474 buffers->priority, true);
1475 }
1476 }
1477 }
1478
1479 /* Reallocate a buffer a update all resource bindings where the buffer is
1480 * bound.
1481 *
1482 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1483 * idle by discarding its contents. Apps usually tell us when to do this using
1484 * map_buffer flags, for example.
1485 */
1486 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1487 {
1488 struct si_context *sctx = (struct si_context*)ctx;
1489 struct r600_resource *rbuffer = r600_resource(buf);
1490 unsigned i, shader;
1491 uint64_t old_va = rbuffer->gpu_address;
1492 unsigned num_elems = sctx->vertex_elements ?
1493 sctx->vertex_elements->count : 0;
1494 struct si_sampler_view *view;
1495
1496 /* Reallocate the buffer in the same pipe_resource. */
1497 r600_alloc_resource(&sctx->screen->b, rbuffer);
1498
1499 /* We changed the buffer, now we need to bind it where the old one
1500 * was bound. This consists of 2 things:
1501 * 1) Updating the resource descriptor and dirtying it.
1502 * 2) Adding a relocation to the CS, so that it's usable.
1503 */
1504
1505 /* Vertex buffers. */
1506 if (rbuffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
1507 for (i = 0; i < num_elems; i++) {
1508 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1509
1510 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1511 continue;
1512 if (!sctx->vertex_buffer[vb].buffer)
1513 continue;
1514
1515 if (sctx->vertex_buffer[vb].buffer == buf) {
1516 sctx->vertex_buffers_dirty = true;
1517 break;
1518 }
1519 }
1520 }
1521
1522 /* Streamout buffers. (other internal buffers can't be invalidated) */
1523 if (rbuffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
1524 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1525 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1526 struct si_descriptors *descs =
1527 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1528
1529 if (buffers->buffers[i] != buf)
1530 continue;
1531
1532 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1533 old_va, buf);
1534 descs->dirty_mask |= 1u << i;
1535 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1536
1537 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1538 rbuffer, buffers->shader_usage,
1539 RADEON_PRIO_SHADER_RW_BUFFER,
1540 true);
1541
1542 /* Update the streamout state. */
1543 if (sctx->b.streamout.begin_emitted)
1544 r600_emit_streamout_end(&sctx->b);
1545 sctx->b.streamout.append_bitmask =
1546 sctx->b.streamout.enabled_mask;
1547 r600_streamout_buffers_dirty(&sctx->b);
1548 }
1549 }
1550
1551 /* Constant and shader buffers. */
1552 if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1553 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1554 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1555 si_const_buffer_descriptors_idx(shader),
1556 buf, old_va);
1557 }
1558
1559 if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
1560 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1561 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1562 si_shader_buffer_descriptors_idx(shader),
1563 buf, old_va);
1564 }
1565
1566 if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
1567 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1568 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1569 if (view->base.texture == buf) {
1570 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1571 }
1572 }
1573 /* Texture buffers - update bindings. */
1574 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1575 struct si_sampler_views *views = &sctx->samplers[shader].views;
1576 struct si_descriptors *descs =
1577 si_sampler_descriptors(sctx, shader);
1578 unsigned mask = views->enabled_mask;
1579
1580 while (mask) {
1581 unsigned i = u_bit_scan(&mask);
1582 if (views->views[i]->texture == buf) {
1583 si_desc_reset_buffer_offset(ctx,
1584 descs->list +
1585 i * 16 + 4,
1586 old_va, buf);
1587 descs->dirty_mask |= 1u << i;
1588 sctx->descriptors_dirty |=
1589 1u << si_sampler_descriptors_idx(shader);
1590
1591 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1592 rbuffer, RADEON_USAGE_READ,
1593 RADEON_PRIO_SAMPLER_BUFFER,
1594 true);
1595 }
1596 }
1597 }
1598 }
1599
1600 /* Shader images */
1601 if (rbuffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
1602 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1603 struct si_images_info *images = &sctx->images[shader];
1604 struct si_descriptors *descs =
1605 si_image_descriptors(sctx, shader);
1606 unsigned mask = images->enabled_mask;
1607
1608 while (mask) {
1609 unsigned i = u_bit_scan(&mask);
1610
1611 if (images->views[i].resource == buf) {
1612 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1613 si_mark_image_range_valid(&images->views[i]);
1614
1615 si_desc_reset_buffer_offset(
1616 ctx, descs->list + i * 8 + 4,
1617 old_va, buf);
1618 descs->dirty_mask |= 1u << i;
1619 sctx->descriptors_dirty |=
1620 1u << si_image_descriptors_idx(shader);
1621
1622 radeon_add_to_buffer_list_check_mem(
1623 &sctx->b, &sctx->b.gfx, rbuffer,
1624 RADEON_USAGE_READWRITE,
1625 RADEON_PRIO_SAMPLER_BUFFER, true);
1626 }
1627 }
1628 }
1629 }
1630 }
1631
1632 /* Update mutable image descriptor fields of all bound textures. */
1633 void si_update_all_texture_descriptors(struct si_context *sctx)
1634 {
1635 unsigned shader;
1636
1637 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1638 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1639 struct si_images_info *images = &sctx->images[shader];
1640 unsigned mask;
1641
1642 /* Images. */
1643 mask = images->enabled_mask;
1644 while (mask) {
1645 unsigned i = u_bit_scan(&mask);
1646 struct pipe_image_view *view = &images->views[i];
1647
1648 if (!view->resource ||
1649 view->resource->target == PIPE_BUFFER)
1650 continue;
1651
1652 si_set_shader_image(sctx, shader, i, view);
1653 }
1654
1655 /* Sampler views. */
1656 mask = samplers->enabled_mask;
1657 while (mask) {
1658 unsigned i = u_bit_scan(&mask);
1659 struct pipe_sampler_view *view = samplers->views[i];
1660
1661 if (!view ||
1662 !view->texture ||
1663 view->texture->target == PIPE_BUFFER)
1664 continue;
1665
1666 si_set_sampler_view(sctx, shader, i,
1667 samplers->views[i], true);
1668 }
1669 }
1670 }
1671
1672 /* SHADER USER DATA */
1673
1674 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1675 unsigned shader)
1676 {
1677 struct si_descriptors *descs =
1678 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1679
1680 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1681 descs->pointer_dirty = true;
1682
1683 if (shader == PIPE_SHADER_VERTEX)
1684 sctx->vertex_buffers.pointer_dirty = true;
1685
1686 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1687 }
1688
1689 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1690 {
1691 int i;
1692
1693 for (i = 0; i < SI_NUM_SHADERS; i++) {
1694 si_mark_shader_pointers_dirty(sctx, i);
1695 }
1696 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1697 }
1698
1699 /* Set a base register address for user data constants in the given shader.
1700 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1701 */
1702 static void si_set_user_data_base(struct si_context *sctx,
1703 unsigned shader, uint32_t new_base)
1704 {
1705 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1706
1707 if (*base != new_base) {
1708 *base = new_base;
1709
1710 if (new_base)
1711 si_mark_shader_pointers_dirty(sctx, shader);
1712 }
1713 }
1714
1715 /* This must be called when these shaders are changed from non-NULL to NULL
1716 * and vice versa:
1717 * - geometry shader
1718 * - tessellation control shader
1719 * - tessellation evaluation shader
1720 */
1721 void si_shader_change_notify(struct si_context *sctx)
1722 {
1723 /* VS can be bound as VS, ES, or LS. */
1724 if (sctx->tes_shader.cso)
1725 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1726 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1727 else if (sctx->gs_shader.cso)
1728 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1729 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1730 else
1731 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1732 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1733
1734 /* TES can be bound as ES, VS, or not bound. */
1735 if (sctx->tes_shader.cso) {
1736 if (sctx->gs_shader.cso)
1737 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1738 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1739 else
1740 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1741 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1742 } else {
1743 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1744 }
1745 }
1746
1747 static void si_emit_shader_pointer(struct si_context *sctx,
1748 struct si_descriptors *desc,
1749 unsigned sh_base, bool keep_dirty)
1750 {
1751 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1752 uint64_t va;
1753
1754 if (!desc->pointer_dirty || !desc->buffer)
1755 return;
1756
1757 va = desc->buffer->gpu_address +
1758 desc->buffer_offset;
1759
1760 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1761 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1762 radeon_emit(cs, va);
1763 radeon_emit(cs, va >> 32);
1764
1765 desc->pointer_dirty = keep_dirty;
1766 }
1767
1768 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1769 struct r600_atom *atom)
1770 {
1771 unsigned shader;
1772 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1773 struct si_descriptors *descs;
1774
1775 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1776
1777 if (descs->pointer_dirty) {
1778 si_emit_shader_pointer(sctx, descs,
1779 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1780 si_emit_shader_pointer(sctx, descs,
1781 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1782 si_emit_shader_pointer(sctx, descs,
1783 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1784 si_emit_shader_pointer(sctx, descs,
1785 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1786 si_emit_shader_pointer(sctx, descs,
1787 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1788 descs->pointer_dirty = false;
1789 }
1790
1791 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1792
1793 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1794 unsigned base = sh_base[shader];
1795 unsigned i;
1796
1797 if (!base)
1798 continue;
1799
1800 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1801 si_emit_shader_pointer(sctx, descs, base, false);
1802 }
1803 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1804 }
1805
1806 void si_emit_compute_shader_userdata(struct si_context *sctx)
1807 {
1808 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1809 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1810
1811 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1812 si_emit_shader_pointer(sctx, descs, base, false);
1813 }
1814
1815 /* INIT/DEINIT/UPLOAD */
1816
1817 void si_init_all_descriptors(struct si_context *sctx)
1818 {
1819 int i;
1820 unsigned ce_offset = 0;
1821
1822 for (i = 0; i < SI_NUM_SHADERS; i++) {
1823 si_init_buffer_resources(&sctx->const_buffers[i],
1824 si_const_buffer_descriptors(sctx, i),
1825 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1826 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1827 &ce_offset);
1828 si_init_buffer_resources(&sctx->shader_buffers[i],
1829 si_shader_buffer_descriptors(sctx, i),
1830 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1831 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1832 &ce_offset);
1833
1834 si_init_descriptors(si_sampler_descriptors(sctx, i),
1835 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1836 null_texture_descriptor, &ce_offset);
1837
1838 si_init_descriptors(si_image_descriptors(sctx, i),
1839 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1840 null_image_descriptor, &ce_offset);
1841 }
1842
1843 si_init_buffer_resources(&sctx->rw_buffers,
1844 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1845 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1846 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
1847 &ce_offset);
1848 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1849 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1850
1851 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1852
1853 assert(ce_offset <= 32768);
1854
1855 /* Set pipe_context functions. */
1856 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1857 sctx->b.b.set_shader_images = si_set_shader_images;
1858 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1859 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1860 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1861 sctx->b.b.set_sampler_views = si_set_sampler_views;
1862 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1863 sctx->b.invalidate_buffer = si_invalidate_buffer;
1864
1865 /* Shader user data. */
1866 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1867 si_emit_graphics_shader_userdata);
1868
1869 /* Set default and immutable mappings. */
1870 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1871 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1872 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1873 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1874 }
1875
1876 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1877 {
1878 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
1879 unsigned dirty = sctx->descriptors_dirty & mask;
1880
1881 while (dirty) {
1882 unsigned i = u_bit_scan(&dirty);
1883
1884 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1885 &sctx->shader_userdata.atom))
1886 return false;
1887 }
1888
1889 sctx->descriptors_dirty &= ~mask;
1890 return true;
1891 }
1892
1893 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1894 {
1895 /* Does not update rw_buffers as that is not needed for compute shaders
1896 * and the input buffer is using the same SGPR's anyway.
1897 */
1898 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
1899 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
1900 unsigned dirty = sctx->descriptors_dirty & mask;
1901
1902 while (dirty) {
1903 unsigned i = u_bit_scan(&dirty);
1904
1905 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1906 return false;
1907 }
1908
1909 sctx->descriptors_dirty &= ~mask;
1910
1911 return true;
1912 }
1913
1914 void si_release_all_descriptors(struct si_context *sctx)
1915 {
1916 int i;
1917
1918 for (i = 0; i < SI_NUM_SHADERS; i++) {
1919 si_release_buffer_resources(&sctx->const_buffers[i],
1920 si_const_buffer_descriptors(sctx, i));
1921 si_release_buffer_resources(&sctx->shader_buffers[i],
1922 si_shader_buffer_descriptors(sctx, i));
1923 si_release_sampler_views(&sctx->samplers[i].views);
1924 si_release_image_views(&sctx->images[i]);
1925 }
1926 si_release_buffer_resources(&sctx->rw_buffers,
1927 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1928
1929 for (i = 0; i < SI_NUM_DESCS; ++i)
1930 si_release_descriptors(&sctx->descriptors[i]);
1931 si_release_descriptors(&sctx->vertex_buffers);
1932 }
1933
1934 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1935 {
1936 int i;
1937
1938 for (i = 0; i < SI_NUM_SHADERS; i++) {
1939 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1940 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1941 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1942 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1943 }
1944 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1945 si_vertex_buffers_begin_new_cs(sctx);
1946
1947 for (i = 0; i < SI_NUM_DESCS; ++i)
1948 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1949
1950 si_shader_userdata_begin_new_cs(sctx);
1951 }