2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/hash_table.h"
64 #include "util/u_idalloc.h"
65 #include "util/u_format.h"
66 #include "util/u_memory.h"
67 #include "util/u_upload_mgr.h"
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
79 * This is the only reason why the buffer descriptor must be in words [4:7].
81 static uint32_t null_texture_descriptor
[8] = {
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
87 /* the rest must contain zeros, which is also used by the buffer
91 static uint32_t null_image_descriptor
[8] = {
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
96 /* the rest must contain zeros, which is also used by the buffer
100 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
102 return desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
105 static void si_init_descriptor_list(uint32_t *desc_list
,
106 unsigned element_dw_size
,
107 unsigned num_elements
,
108 const uint32_t *null_descriptor
)
112 /* Initialize the array to NULL descriptors if the element size is 8. */
113 if (null_descriptor
) {
114 assert(element_dw_size
% 8 == 0);
115 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
116 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
120 static void si_init_descriptors(struct si_descriptors
*desc
,
121 unsigned shader_userdata_index
,
122 unsigned element_dw_size
,
123 unsigned num_elements
)
125 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
126 desc
->element_dw_size
= element_dw_size
;
127 desc
->num_elements
= num_elements
;
128 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
131 static void si_release_descriptors(struct si_descriptors
*desc
)
133 r600_resource_reference(&desc
->buffer
, NULL
);
137 static bool si_upload_descriptors(struct si_context
*sctx
,
138 struct si_descriptors
*desc
)
140 unsigned slot_size
= desc
->element_dw_size
* 4;
141 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
142 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
144 /* Skip the upload if no shader is using the descriptors. dirty_mask
145 * will stay dirty and the descriptors will be uploaded when there is
146 * a shader using them.
153 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
154 si_optimal_tcc_alignment(sctx
, upload_size
),
155 (unsigned*)&buffer_offset
,
156 (struct pipe_resource
**)&desc
->buffer
,
159 desc
->gpu_address
= 0;
160 return false; /* skip the draw call */
163 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
165 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
167 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
168 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
170 /* The shader pointer should point to slot 0. */
171 buffer_offset
-= first_slot_offset
;
172 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
174 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
179 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
184 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
185 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
191 si_sampler_and_image_descriptors_idx(unsigned shader
)
193 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
194 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
197 static struct si_descriptors
*
198 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
200 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
203 static void si_release_sampler_views(struct si_samplers
*samplers
)
207 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
208 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
212 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
213 struct pipe_resource
*resource
,
214 enum radeon_bo_usage usage
,
215 bool is_stencil_sampler
,
218 struct r600_resource
*rres
;
219 struct r600_texture
*rtex
;
220 enum radeon_bo_priority priority
;
225 if (resource
->target
!= PIPE_BUFFER
) {
226 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
228 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
229 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
232 rres
= (struct r600_resource
*)resource
;
233 priority
= r600_get_sampler_view_priority(rres
);
235 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
236 rres
, usage
, priority
,
239 if (resource
->target
== PIPE_BUFFER
)
242 /* Now add separate DCC or HTILE. */
243 rtex
= (struct r600_texture
*)resource
;
244 if (rtex
->dcc_separate_buffer
) {
245 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
246 rtex
->dcc_separate_buffer
, usage
,
247 RADEON_PRIO_DCC
, check_mem
);
251 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
252 struct si_samplers
*samplers
)
254 unsigned mask
= samplers
->enabled_mask
;
256 /* Add buffers to the CS. */
258 int i
= u_bit_scan(&mask
);
259 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
261 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
263 sview
->is_stencil_sampler
, false);
267 /* Set buffer descriptor fields that can be changed by reallocations. */
268 static void si_set_buf_desc_address(struct r600_resource
*buf
,
269 uint64_t offset
, uint32_t *state
)
271 uint64_t va
= buf
->gpu_address
+ offset
;
274 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
275 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
278 /* Set texture descriptor fields that can be changed by reallocations.
281 * \param base_level_info information of the level of BASE_ADDRESS
282 * \param base_level the level of BASE_ADDRESS
283 * \param first_level pipe_sampler_view.u.tex.first_level
284 * \param block_width util_format_get_blockwidth()
285 * \param is_stencil select between separate Z & Stencil
286 * \param state descriptor to update
288 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
289 struct r600_texture
*tex
,
290 const struct legacy_surf_level
*base_level_info
,
291 unsigned base_level
, unsigned first_level
,
292 unsigned block_width
, bool is_stencil
,
295 uint64_t va
, meta_va
= 0;
297 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
298 tex
= tex
->flushed_depth_texture
;
302 va
= tex
->resource
.gpu_address
;
304 if (sscreen
->b
.chip_class
>= GFX9
) {
305 /* Only stencil_offset needs to be added here. */
307 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
309 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
311 va
+= base_level_info
->offset
;
315 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
316 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
318 /* Only macrotiled modes can set tile swizzle.
319 * GFX9 doesn't use (legacy) base_level_info.
321 if (sscreen
->b
.chip_class
>= GFX9
||
322 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
323 state
[0] |= tex
->surface
.tile_swizzle
;
325 if (sscreen
->b
.chip_class
>= VI
) {
326 state
[6] &= C_008F28_COMPRESSION_EN
;
329 if (vi_dcc_enabled(tex
, first_level
)) {
330 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
333 if (sscreen
->b
.chip_class
== VI
) {
334 meta_va
+= base_level_info
->dcc_offset
;
335 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
338 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
339 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
340 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
344 state
[6] |= S_008F28_COMPRESSION_EN(1);
345 state
[7] = meta_va
>> 8;
349 if (sscreen
->b
.chip_class
>= GFX9
) {
350 state
[3] &= C_008F1C_SW_MODE
;
351 state
[4] &= C_008F20_PITCH_GFX9
;
354 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
355 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
357 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
358 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
361 state
[5] &= C_008F24_META_DATA_ADDRESS
&
362 C_008F24_META_PIPE_ALIGNED
&
363 C_008F24_META_RB_ALIGNED
;
365 struct gfx9_surf_meta_flags meta
;
368 meta
= tex
->surface
.u
.gfx9
.dcc
;
370 meta
= tex
->surface
.u
.gfx9
.htile
;
372 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
373 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
374 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
378 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
379 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
381 state
[3] &= C_008F1C_TILING_INDEX
;
382 state
[3] |= S_008F1C_TILING_INDEX(index
);
383 state
[4] &= C_008F20_PITCH_GFX6
;
384 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
388 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
389 struct si_sampler_view
*sview
,
390 struct r600_texture
*tex
,
393 if (sview
&& sview
->is_integer
)
394 memcpy(desc
, sstate
->integer_val
, 4*4);
395 else if (tex
&& tex
->upgraded_depth
&&
396 (!sview
|| !sview
->is_stencil_sampler
))
397 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
399 memcpy(desc
, sstate
->val
, 4*4);
402 static void si_set_sampler_view_desc(struct si_context
*sctx
,
403 struct si_sampler_view
*sview
,
404 struct si_sampler_state
*sstate
,
407 struct pipe_sampler_view
*view
= &sview
->base
;
408 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
409 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
411 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
412 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
413 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
414 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
416 sview
->dcc_incompatible
= false;
419 assert(rtex
); /* views with texture == NULL aren't supported */
420 memcpy(desc
, sview
->state
, 8*4);
423 si_set_buf_desc_address(&rtex
->resource
,
424 sview
->base
.u
.buf
.offset
,
427 bool is_separate_stencil
= rtex
->db_compatible
&&
428 sview
->is_stencil_sampler
;
430 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
431 sview
->base_level_info
,
433 sview
->base
.u
.tex
.first_level
,
439 if (!is_buffer
&& rtex
->fmask
.size
) {
440 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
442 /* Disable FMASK and bind sampler state in [12:15]. */
443 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
446 si_set_sampler_state_desc(sstate
, sview
,
447 is_buffer
? NULL
: rtex
,
452 static bool color_needs_decompression(struct r600_texture
*rtex
)
454 return rtex
->fmask
.size
||
455 (rtex
->dirty_level_mask
&&
456 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
459 static bool depth_needs_decompression(struct r600_texture
*rtex
)
461 /* If the depth/stencil texture is TC-compatible, no decompression
462 * will be done. The decompression function will only flush DB caches
463 * to make it coherent with shaders. That's necessary because the driver
464 * doesn't flush DB caches in any other case.
466 return rtex
->db_compatible
;
469 static void si_set_sampler_view(struct si_context
*sctx
,
471 unsigned slot
, struct pipe_sampler_view
*view
,
472 bool disallow_early_out
)
474 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
475 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
476 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
477 unsigned desc_slot
= si_get_sampler_slot(slot
);
478 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
480 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
484 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
486 si_set_sampler_view_desc(sctx
, rview
,
487 samplers
->sampler_states
[slot
], desc
);
489 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
490 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
491 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
492 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
494 if (depth_needs_decompression(rtex
)) {
495 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
497 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
499 if (color_needs_decompression(rtex
)) {
500 samplers
->needs_color_decompress_mask
|= 1u << slot
;
502 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
505 if (rtex
->dcc_offset
&&
506 p_atomic_read(&rtex
->framebuffers_bound
))
507 sctx
->need_check_render_feedback
= true;
510 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
511 samplers
->enabled_mask
|= 1u << slot
;
513 /* Since this can flush, it must be done after enabled_mask is
515 si_sampler_view_add_buffer(sctx
, view
->texture
,
517 rview
->is_stencil_sampler
, true);
519 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
520 memcpy(desc
, null_texture_descriptor
, 8*4);
521 /* Only clear the lower dwords of FMASK. */
522 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
523 /* Re-set the sampler state if we are transitioning from FMASK. */
524 if (samplers
->sampler_states
[slot
])
525 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
528 samplers
->enabled_mask
&= ~(1u << slot
);
529 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
530 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
533 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
536 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
539 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
540 unsigned shader_bit
= 1 << shader
;
542 if (samplers
->needs_depth_decompress_mask
||
543 samplers
->needs_color_decompress_mask
||
544 sctx
->images
[shader
].needs_color_decompress_mask
)
545 sctx
->shader_needs_decompress_mask
|= shader_bit
;
547 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
550 static void si_set_sampler_views(struct pipe_context
*ctx
,
551 enum pipe_shader_type shader
, unsigned start
,
553 struct pipe_sampler_view
**views
)
555 struct si_context
*sctx
= (struct si_context
*)ctx
;
558 if (!count
|| shader
>= SI_NUM_SHADERS
)
562 for (i
= 0; i
< count
; i
++)
563 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
565 for (i
= 0; i
< count
; i
++)
566 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
569 si_update_shader_needs_decompress_mask(sctx
, shader
);
573 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
575 unsigned mask
= samplers
->enabled_mask
;
578 int i
= u_bit_scan(&mask
);
579 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
581 if (res
&& res
->target
!= PIPE_BUFFER
) {
582 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
584 if (color_needs_decompression(rtex
)) {
585 samplers
->needs_color_decompress_mask
|= 1u << i
;
587 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
596 si_release_image_views(struct si_images
*images
)
600 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
601 struct pipe_image_view
*view
= &images
->views
[i
];
603 pipe_resource_reference(&view
->resource
, NULL
);
608 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
610 uint mask
= images
->enabled_mask
;
612 /* Add buffers to the CS. */
614 int i
= u_bit_scan(&mask
);
615 struct pipe_image_view
*view
= &images
->views
[i
];
617 assert(view
->resource
);
619 si_sampler_view_add_buffer(sctx
, view
->resource
,
620 RADEON_USAGE_READWRITE
, false, false);
625 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
627 struct si_images
*images
= &ctx
->images
[shader
];
629 if (images
->enabled_mask
& (1u << slot
)) {
630 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
631 unsigned desc_slot
= si_get_image_slot(slot
);
633 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
634 images
->needs_color_decompress_mask
&= ~(1 << slot
);
636 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
637 images
->enabled_mask
&= ~(1u << slot
);
638 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
643 si_mark_image_range_valid(const struct pipe_image_view
*view
)
645 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
647 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
649 util_range_add(&res
->valid_buffer_range
,
651 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
654 static void si_set_shader_image_desc(struct si_context
*ctx
,
655 const struct pipe_image_view
*view
,
656 bool skip_decompress
,
659 struct si_screen
*screen
= ctx
->screen
;
660 struct r600_resource
*res
;
662 res
= (struct r600_resource
*)view
->resource
;
664 if (res
->b
.b
.target
== PIPE_BUFFER
) {
665 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
666 si_mark_image_range_valid(view
);
668 si_make_buffer_descriptor(screen
, res
,
671 view
->u
.buf
.size
, desc
);
672 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
674 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
675 struct r600_texture
*tex
= (struct r600_texture
*)res
;
676 unsigned level
= view
->u
.tex
.level
;
677 unsigned width
, height
, depth
, hw_level
;
678 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
680 assert(!tex
->is_depth
);
681 assert(tex
->fmask
.size
== 0);
683 if (uses_dcc
&& !skip_decompress
&&
684 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
685 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
686 /* If DCC can't be disabled, at least decompress it.
687 * The decompression is relatively cheap if the surface
688 * has been decompressed already.
690 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
691 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
694 if (ctx
->b
.chip_class
>= GFX9
) {
695 /* Always set the base address. The swizzle modes don't
696 * allow setting mipmap level offsets as the base.
698 width
= res
->b
.b
.width0
;
699 height
= res
->b
.b
.height0
;
700 depth
= res
->b
.b
.depth0
;
703 /* Always force the base level to the selected level.
705 * This is required for 3D textures, where otherwise
706 * selecting a single slice for non-layered bindings
707 * fails. It doesn't hurt the other targets.
709 width
= u_minify(res
->b
.b
.width0
, level
);
710 height
= u_minify(res
->b
.b
.height0
, level
);
711 depth
= u_minify(res
->b
.b
.depth0
, level
);
715 si_make_texture_descriptor(screen
, tex
,
716 false, res
->b
.b
.target
,
717 view
->format
, swizzle
,
719 view
->u
.tex
.first_layer
,
720 view
->u
.tex
.last_layer
,
721 width
, height
, depth
,
723 si_set_mutable_tex_desc_fields(screen
, tex
,
724 &tex
->surface
.u
.legacy
.level
[level
],
726 util_format_get_blockwidth(view
->format
),
731 static void si_set_shader_image(struct si_context
*ctx
,
733 unsigned slot
, const struct pipe_image_view
*view
,
734 bool skip_decompress
)
736 struct si_images
*images
= &ctx
->images
[shader
];
737 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
738 struct r600_resource
*res
;
739 unsigned desc_slot
= si_get_image_slot(slot
);
740 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
742 if (!view
|| !view
->resource
) {
743 si_disable_shader_image(ctx
, shader
, slot
);
747 res
= (struct r600_resource
*)view
->resource
;
749 if (&images
->views
[slot
] != view
)
750 util_copy_image_view(&images
->views
[slot
], view
);
752 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
754 if (res
->b
.b
.target
== PIPE_BUFFER
) {
755 images
->needs_color_decompress_mask
&= ~(1 << slot
);
756 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
758 struct r600_texture
*tex
= (struct r600_texture
*)res
;
759 unsigned level
= view
->u
.tex
.level
;
761 if (color_needs_decompression(tex
)) {
762 images
->needs_color_decompress_mask
|= 1 << slot
;
764 images
->needs_color_decompress_mask
&= ~(1 << slot
);
767 if (vi_dcc_enabled(tex
, level
) &&
768 p_atomic_read(&tex
->framebuffers_bound
))
769 ctx
->need_check_render_feedback
= true;
772 images
->enabled_mask
|= 1u << slot
;
773 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
775 /* Since this can flush, it must be done after enabled_mask is updated. */
776 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
777 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
778 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
783 si_set_shader_images(struct pipe_context
*pipe
,
784 enum pipe_shader_type shader
,
785 unsigned start_slot
, unsigned count
,
786 const struct pipe_image_view
*views
)
788 struct si_context
*ctx
= (struct si_context
*)pipe
;
791 assert(shader
< SI_NUM_SHADERS
);
796 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
799 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
800 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
802 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
803 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
806 si_update_shader_needs_decompress_mask(ctx
, shader
);
810 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
812 unsigned mask
= images
->enabled_mask
;
815 int i
= u_bit_scan(&mask
);
816 struct pipe_resource
*res
= images
->views
[i
].resource
;
818 if (res
&& res
->target
!= PIPE_BUFFER
) {
819 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
821 if (color_needs_decompression(rtex
)) {
822 images
->needs_color_decompress_mask
|= 1 << i
;
824 images
->needs_color_decompress_mask
&= ~(1 << i
);
832 static void si_bind_sampler_states(struct pipe_context
*ctx
,
833 enum pipe_shader_type shader
,
834 unsigned start
, unsigned count
, void **states
)
836 struct si_context
*sctx
= (struct si_context
*)ctx
;
837 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
838 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
839 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
842 if (!count
|| shader
>= SI_NUM_SHADERS
)
845 for (i
= 0; i
< count
; i
++) {
846 unsigned slot
= start
+ i
;
847 unsigned desc_slot
= si_get_sampler_slot(slot
);
850 sstates
[i
] == samplers
->sampler_states
[slot
])
854 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
856 samplers
->sampler_states
[slot
] = sstates
[i
];
858 /* If FMASK is bound, don't overwrite it.
859 * The sampler state will be set after FMASK is unbound.
861 struct si_sampler_view
*sview
=
862 (struct si_sampler_view
*)samplers
->views
[slot
];
864 struct r600_texture
*tex
= NULL
;
866 if (sview
&& sview
->base
.texture
&&
867 sview
->base
.texture
->target
!= PIPE_BUFFER
)
868 tex
= (struct r600_texture
*)sview
->base
.texture
;
870 if (tex
&& tex
->fmask
.size
)
873 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
874 desc
->list
+ desc_slot
* 16 + 12);
876 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
880 /* BUFFER RESOURCES */
882 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
883 struct si_descriptors
*descs
,
884 unsigned num_buffers
,
885 unsigned shader_userdata_index
,
886 enum radeon_bo_usage shader_usage
,
887 enum radeon_bo_usage shader_usage_constbuf
,
888 enum radeon_bo_priority priority
,
889 enum radeon_bo_priority priority_constbuf
)
891 buffers
->shader_usage
= shader_usage
;
892 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
893 buffers
->priority
= priority
;
894 buffers
->priority_constbuf
= priority_constbuf
;
895 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
897 si_init_descriptors(descs
, shader_userdata_index
, 4, num_buffers
);
900 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
901 struct si_descriptors
*descs
)
905 for (i
= 0; i
< descs
->num_elements
; i
++) {
906 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
909 FREE(buffers
->buffers
);
912 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
913 struct si_buffer_resources
*buffers
)
915 unsigned mask
= buffers
->enabled_mask
;
917 /* Add buffers to the CS. */
919 int i
= u_bit_scan(&mask
);
921 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
922 r600_resource(buffers
->buffers
[i
]),
923 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
924 buffers
->shader_usage_constbuf
,
925 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
926 buffers
->priority_constbuf
);
930 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
931 struct si_descriptors
*descs
,
932 unsigned idx
, struct pipe_resource
**buf
,
933 unsigned *offset
, unsigned *size
)
935 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
937 struct r600_resource
*res
= r600_resource(*buf
);
938 const uint32_t *desc
= descs
->list
+ idx
* 4;
943 assert(G_008F04_STRIDE(desc
[1]) == 0);
944 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
946 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
947 *offset
= va
- res
->gpu_address
;
953 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
955 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
956 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
959 for (i
= 0; i
< count
; i
++) {
960 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
962 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
964 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
967 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
968 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
969 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
974 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
975 desc
->buffer
, RADEON_USAGE_READ
,
976 RADEON_PRIO_DESCRIPTORS
);
979 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
981 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
982 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
984 unsigned desc_list_byte_size
;
985 unsigned first_vb_use_mask
;
989 if (!sctx
->vertex_buffers_dirty
|| !velems
)
992 count
= velems
->count
;
997 desc_list_byte_size
= velems
->desc_list_byte_size
;
998 first_vb_use_mask
= velems
->first_vb_use_mask
;
1000 /* Vertex buffer descriptors are the only ones which are uploaded
1001 * directly through a staging buffer and don't go through
1002 * the fine-grained upload path.
1004 unsigned buffer_offset
= 0;
1005 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1006 desc_list_byte_size
,
1007 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1009 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1010 if (!desc
->buffer
) {
1011 desc
->gpu_address
= 0;
1015 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
1017 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1018 desc
->buffer
, RADEON_USAGE_READ
,
1019 RADEON_PRIO_DESCRIPTORS
);
1021 assert(count
<= SI_MAX_ATTRIBS
);
1023 for (i
= 0; i
< count
; i
++) {
1024 struct pipe_vertex_buffer
*vb
;
1025 struct r600_resource
*rbuffer
;
1027 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1028 uint32_t *desc
= &ptr
[i
*4];
1030 vb
= &sctx
->vertex_buffer
[vbo_index
];
1031 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1033 memset(desc
, 0, 16);
1037 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1038 va
= rbuffer
->gpu_address
+ offset
;
1040 /* Fill in T# buffer resource description */
1042 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1043 S_008F04_STRIDE(vb
->stride
);
1045 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1046 /* Round up by rounding down and adding 1 */
1047 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1048 velems
->format_size
[i
]) /
1051 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1054 desc
[3] = velems
->rsrc_word3
[i
];
1056 if (first_vb_use_mask
& (1 << i
)) {
1057 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1058 (struct r600_resource
*)vb
->buffer
.resource
,
1059 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1063 /* Don't flush the const cache. It would have a very negative effect
1064 * on performance (confirmed by testing). New descriptors are always
1065 * uploaded to a fresh new buffer, so I don't think flushing the const
1066 * cache is needed. */
1067 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1068 sctx
->vertex_buffers_dirty
= false;
1069 sctx
->vertex_buffer_pointer_dirty
= true;
1070 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1075 /* CONSTANT BUFFERS */
1078 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1080 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1081 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1084 static struct si_descriptors
*
1085 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1087 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1090 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1091 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1095 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1096 si_optimal_tcc_alignment(sctx
, size
),
1098 (struct pipe_resource
**)rbuffer
, &tmp
);
1100 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1103 static void si_set_constant_buffer(struct si_context
*sctx
,
1104 struct si_buffer_resources
*buffers
,
1105 unsigned descriptors_idx
,
1106 uint slot
, const struct pipe_constant_buffer
*input
)
1108 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1109 assert(slot
< descs
->num_elements
);
1110 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1112 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1113 * with a NULL buffer). We need to use a dummy buffer instead. */
1114 if (sctx
->b
.chip_class
== CIK
&&
1115 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1116 input
= &sctx
->null_const_buf
;
1118 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1119 struct pipe_resource
*buffer
= NULL
;
1122 /* Upload the user buffer if needed. */
1123 if (input
->user_buffer
) {
1124 unsigned buffer_offset
;
1126 si_upload_const_buffer(sctx
,
1127 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1128 input
->buffer_size
, &buffer_offset
);
1130 /* Just unbind on failure. */
1131 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1134 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1136 pipe_resource_reference(&buffer
, input
->buffer
);
1137 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1138 /* Only track usage for non-user buffers. */
1139 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1142 /* Set the descriptor. */
1143 uint32_t *desc
= descs
->list
+ slot
*4;
1145 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1147 desc
[2] = input
->buffer_size
;
1148 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1149 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1150 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1151 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1152 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1153 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1155 buffers
->buffers
[slot
] = buffer
;
1156 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1157 (struct r600_resource
*)buffer
,
1158 buffers
->shader_usage_constbuf
,
1159 buffers
->priority_constbuf
, true);
1160 buffers
->enabled_mask
|= 1u << slot
;
1162 /* Clear the descriptor. */
1163 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1164 buffers
->enabled_mask
&= ~(1u << slot
);
1167 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1170 void si_set_rw_buffer(struct si_context
*sctx
,
1171 uint slot
, const struct pipe_constant_buffer
*input
)
1173 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1174 SI_DESCS_RW_BUFFERS
, slot
, input
);
1177 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1178 enum pipe_shader_type shader
, uint slot
,
1179 const struct pipe_constant_buffer
*input
)
1181 struct si_context
*sctx
= (struct si_context
*)ctx
;
1183 if (shader
>= SI_NUM_SHADERS
)
1186 slot
= si_get_constbuf_slot(slot
);
1187 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1188 si_const_and_shader_buffer_descriptors_idx(shader
),
1192 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1193 uint slot
, struct pipe_constant_buffer
*cbuf
)
1195 cbuf
->user_buffer
= NULL
;
1196 si_get_buffer_from_descriptors(
1197 &sctx
->const_and_shader_buffers
[shader
],
1198 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1199 si_get_constbuf_slot(slot
),
1200 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1203 /* SHADER BUFFERS */
1205 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1206 enum pipe_shader_type shader
,
1207 unsigned start_slot
, unsigned count
,
1208 const struct pipe_shader_buffer
*sbuffers
)
1210 struct si_context
*sctx
= (struct si_context
*)ctx
;
1211 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1212 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1215 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1217 for (i
= 0; i
< count
; ++i
) {
1218 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1219 struct r600_resource
*buf
;
1220 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1221 uint32_t *desc
= descs
->list
+ slot
* 4;
1224 if (!sbuffer
|| !sbuffer
->buffer
) {
1225 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1226 memset(desc
, 0, sizeof(uint32_t) * 4);
1227 buffers
->enabled_mask
&= ~(1u << slot
);
1228 sctx
->descriptors_dirty
|=
1229 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1233 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1234 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1237 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1239 desc
[2] = sbuffer
->buffer_size
;
1240 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1241 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1242 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1243 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1244 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1245 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1247 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1248 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1249 buffers
->shader_usage
,
1250 buffers
->priority
, true);
1251 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1253 buffers
->enabled_mask
|= 1u << slot
;
1254 sctx
->descriptors_dirty
|=
1255 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1257 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1258 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1262 void si_get_shader_buffers(struct si_context
*sctx
,
1263 enum pipe_shader_type shader
,
1264 uint start_slot
, uint count
,
1265 struct pipe_shader_buffer
*sbuf
)
1267 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1268 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1270 for (unsigned i
= 0; i
< count
; ++i
) {
1271 si_get_buffer_from_descriptors(
1273 si_get_shaderbuf_slot(start_slot
+ i
),
1274 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1275 &sbuf
[i
].buffer_size
);
1281 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1282 struct pipe_resource
*buffer
,
1283 unsigned stride
, unsigned num_records
,
1284 bool add_tid
, bool swizzle
,
1285 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1287 struct si_context
*sctx
= (struct si_context
*)ctx
;
1288 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1289 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1291 /* The stride field in the resource descriptor has 14 bits */
1292 assert(stride
< (1 << 14));
1294 assert(slot
< descs
->num_elements
);
1295 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1300 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1302 switch (element_size
) {
1304 assert(!"Unsupported ring buffer element size");
1320 switch (index_stride
) {
1322 assert(!"Unsupported ring buffer index stride");
1338 if (sctx
->b
.chip_class
>= VI
&& stride
)
1339 num_records
*= stride
;
1341 /* Set the descriptor. */
1342 uint32_t *desc
= descs
->list
+ slot
*4;
1344 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1345 S_008F04_STRIDE(stride
) |
1346 S_008F04_SWIZZLE_ENABLE(swizzle
);
1347 desc
[2] = num_records
;
1348 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1349 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1350 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1351 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1352 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1353 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1354 S_008F0C_INDEX_STRIDE(index_stride
) |
1355 S_008F0C_ADD_TID_ENABLE(add_tid
);
1357 if (sctx
->b
.chip_class
>= GFX9
)
1358 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1360 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1362 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1363 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1364 (struct r600_resource
*)buffer
,
1365 buffers
->shader_usage
, buffers
->priority
);
1366 buffers
->enabled_mask
|= 1u << slot
;
1368 /* Clear the descriptor. */
1369 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1370 buffers
->enabled_mask
&= ~(1u << slot
);
1373 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1376 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1377 uint32_t *desc
, uint64_t old_buf_va
,
1378 struct pipe_resource
*new_buf
)
1380 /* Retrieve the buffer offset from the descriptor. */
1381 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1383 assert(old_buf_va
<= old_desc_va
);
1384 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1386 /* Update the descriptor. */
1387 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1391 /* INTERNAL CONST BUFFERS */
1393 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1394 const struct pipe_poly_stipple
*state
)
1396 struct si_context
*sctx
= (struct si_context
*)ctx
;
1397 struct pipe_constant_buffer cb
= {};
1398 unsigned stipple
[32];
1401 for (i
= 0; i
< 32; i
++)
1402 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1404 cb
.user_buffer
= stipple
;
1405 cb
.buffer_size
= sizeof(stipple
);
1407 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1410 /* TEXTURE METADATA ENABLE/DISABLE */
1413 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1415 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1416 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1418 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1419 struct si_texture_handle
*, tex_handle
) {
1420 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1421 struct r600_texture
*rtex
;
1423 if (!res
|| res
->target
== PIPE_BUFFER
)
1426 rtex
= (struct r600_texture
*)res
;
1427 if (!color_needs_decompression(rtex
))
1430 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1431 struct si_texture_handle
*, *tex_handle
);
1434 util_dynarray_foreach(&sctx
->resident_img_handles
,
1435 struct si_image_handle
*, img_handle
) {
1436 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1437 struct pipe_resource
*res
= view
->resource
;
1438 struct r600_texture
*rtex
;
1440 if (!res
|| res
->target
== PIPE_BUFFER
)
1443 rtex
= (struct r600_texture
*)res
;
1444 if (!color_needs_decompression(rtex
))
1447 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1448 struct si_image_handle
*, *img_handle
);
1452 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1453 * while the texture is bound, possibly by a different context. In that case,
1454 * call this function to update needs_*_decompress_masks.
1456 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1458 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1459 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1460 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1461 si_update_shader_needs_decompress_mask(sctx
, i
);
1464 si_resident_handles_update_needs_color_decompress(sctx
);
1467 /* BUFFER DISCARD/INVALIDATION */
1469 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1470 static void si_reset_buffer_resources(struct si_context
*sctx
,
1471 struct si_buffer_resources
*buffers
,
1472 unsigned descriptors_idx
,
1474 struct pipe_resource
*buf
,
1476 enum radeon_bo_usage usage
,
1477 enum radeon_bo_priority priority
)
1479 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1480 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1483 unsigned i
= u_bit_scan(&mask
);
1484 if (buffers
->buffers
[i
] == buf
) {
1485 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1488 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1490 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1491 (struct r600_resource
*)buf
,
1492 usage
, priority
, true);
1497 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1500 struct si_context
*sctx
= (struct si_context
*)ctx
;
1501 struct r600_resource
*rbuffer
= r600_resource(buf
);
1503 unsigned num_elems
= sctx
->vertex_elements
?
1504 sctx
->vertex_elements
->count
: 0;
1506 /* We changed the buffer, now we need to bind it where the old one
1507 * was bound. This consists of 2 things:
1508 * 1) Updating the resource descriptor and dirtying it.
1509 * 2) Adding a relocation to the CS, so that it's usable.
1512 /* Vertex buffers. */
1513 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1514 for (i
= 0; i
< num_elems
; i
++) {
1515 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1517 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1519 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1522 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1523 sctx
->vertex_buffers_dirty
= true;
1529 /* Streamout buffers. (other internal buffers can't be invalidated) */
1530 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1531 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1532 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1533 struct si_descriptors
*descs
=
1534 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1536 if (buffers
->buffers
[i
] != buf
)
1539 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1541 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1543 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1544 rbuffer
, buffers
->shader_usage
,
1545 RADEON_PRIO_SHADER_RW_BUFFER
,
1548 /* Update the streamout state. */
1549 if (sctx
->streamout
.begin_emitted
)
1550 si_emit_streamout_end(sctx
);
1551 sctx
->streamout
.append_bitmask
=
1552 sctx
->streamout
.enabled_mask
;
1553 si_streamout_buffers_dirty(sctx
);
1557 /* Constant and shader buffers. */
1558 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1559 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1560 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1561 si_const_and_shader_buffer_descriptors_idx(shader
),
1562 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1564 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1565 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1568 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1569 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1570 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1571 si_const_and_shader_buffer_descriptors_idx(shader
),
1572 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1574 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1575 sctx
->const_and_shader_buffers
[shader
].priority
);
1578 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1579 /* Texture buffers - update bindings. */
1580 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1581 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1582 struct si_descriptors
*descs
=
1583 si_sampler_and_image_descriptors(sctx
, shader
);
1584 unsigned mask
= samplers
->enabled_mask
;
1587 unsigned i
= u_bit_scan(&mask
);
1588 if (samplers
->views
[i
]->texture
== buf
) {
1589 unsigned desc_slot
= si_get_sampler_slot(i
);
1591 si_desc_reset_buffer_offset(ctx
,
1595 sctx
->descriptors_dirty
|=
1596 1u << si_sampler_and_image_descriptors_idx(shader
);
1598 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1599 rbuffer
, RADEON_USAGE_READ
,
1600 RADEON_PRIO_SAMPLER_BUFFER
,
1608 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1609 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1610 struct si_images
*images
= &sctx
->images
[shader
];
1611 struct si_descriptors
*descs
=
1612 si_sampler_and_image_descriptors(sctx
, shader
);
1613 unsigned mask
= images
->enabled_mask
;
1616 unsigned i
= u_bit_scan(&mask
);
1618 if (images
->views
[i
].resource
== buf
) {
1619 unsigned desc_slot
= si_get_image_slot(i
);
1621 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1622 si_mark_image_range_valid(&images
->views
[i
]);
1624 si_desc_reset_buffer_offset(
1625 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1627 sctx
->descriptors_dirty
|=
1628 1u << si_sampler_and_image_descriptors_idx(shader
);
1630 radeon_add_to_buffer_list_check_mem(
1631 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1632 RADEON_USAGE_READWRITE
,
1633 RADEON_PRIO_SAMPLER_BUFFER
, true);
1639 /* Bindless texture handles */
1640 if (rbuffer
->texture_handle_allocated
) {
1641 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1643 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1644 struct si_texture_handle
*, tex_handle
) {
1645 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1646 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1648 if (view
->texture
== buf
) {
1649 si_set_buf_desc_address(rbuffer
,
1652 desc_slot
* 16 + 4);
1654 (*tex_handle
)->desc_dirty
= true;
1655 sctx
->bindless_descriptors_dirty
= true;
1657 radeon_add_to_buffer_list_check_mem(
1658 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1660 RADEON_PRIO_SAMPLER_BUFFER
, true);
1665 /* Bindless image handles */
1666 if (rbuffer
->image_handle_allocated
) {
1667 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1669 util_dynarray_foreach(&sctx
->resident_img_handles
,
1670 struct si_image_handle
*, img_handle
) {
1671 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1672 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1674 if (view
->resource
== buf
) {
1675 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1676 si_mark_image_range_valid(view
);
1678 si_set_buf_desc_address(rbuffer
,
1681 desc_slot
* 16 + 4);
1683 (*img_handle
)->desc_dirty
= true;
1684 sctx
->bindless_descriptors_dirty
= true;
1686 radeon_add_to_buffer_list_check_mem(
1687 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1688 RADEON_USAGE_READWRITE
,
1689 RADEON_PRIO_SAMPLER_BUFFER
, true);
1695 /* Reallocate a buffer a update all resource bindings where the buffer is
1698 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1699 * idle by discarding its contents. Apps usually tell us when to do this using
1700 * map_buffer flags, for example.
1702 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1704 struct si_context
*sctx
= (struct si_context
*)ctx
;
1705 struct r600_resource
*rbuffer
= r600_resource(buf
);
1706 uint64_t old_va
= rbuffer
->gpu_address
;
1708 /* Reallocate the buffer in the same pipe_resource. */
1709 si_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1711 si_rebind_buffer(ctx
, buf
, old_va
);
1714 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1716 unsigned num_dwords
)
1718 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1719 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1720 unsigned desc_slot_offset
= desc_slot
* 16;
1724 data
= desc
->list
+ desc_slot_offset
;
1725 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1727 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1728 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1729 S_370_WR_CONFIRM(1) |
1730 S_370_ENGINE_SEL(V_370_ME
));
1731 radeon_emit(cs
, va
);
1732 radeon_emit(cs
, va
>> 32);
1733 radeon_emit_array(cs
, data
, num_dwords
);
1736 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1738 if (!sctx
->bindless_descriptors_dirty
)
1741 /* Wait for graphics/compute to be idle before updating the resident
1742 * descriptors directly in memory, in case the GPU is using them.
1744 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1745 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1746 si_emit_cache_flush(sctx
);
1748 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1749 struct si_texture_handle
*, tex_handle
) {
1750 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1752 if (!(*tex_handle
)->desc_dirty
)
1755 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1756 (*tex_handle
)->desc_dirty
= false;
1759 util_dynarray_foreach(&sctx
->resident_img_handles
,
1760 struct si_image_handle
*, img_handle
) {
1761 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1763 if (!(*img_handle
)->desc_dirty
)
1766 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1767 (*img_handle
)->desc_dirty
= false;
1770 /* Invalidate L1 because it doesn't know that L2 changed. */
1771 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1772 si_emit_cache_flush(sctx
);
1774 sctx
->bindless_descriptors_dirty
= false;
1777 /* Update mutable image descriptor fields of all resident textures. */
1778 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1779 struct si_texture_handle
*tex_handle
)
1781 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1782 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1783 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1784 uint32_t desc_list
[16];
1786 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1789 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1790 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1791 desc
->list
+ desc_slot_offset
);
1793 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1794 sizeof(desc_list
))) {
1795 tex_handle
->desc_dirty
= true;
1796 sctx
->bindless_descriptors_dirty
= true;
1800 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1801 struct si_image_handle
*img_handle
)
1803 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1804 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1805 struct pipe_image_view
*view
= &img_handle
->view
;
1806 uint32_t desc_list
[8];
1808 if (view
->resource
->target
== PIPE_BUFFER
)
1811 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1813 si_set_shader_image_desc(sctx
, view
, true,
1814 desc
->list
+ desc_slot_offset
);
1816 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1817 sizeof(desc_list
))) {
1818 img_handle
->desc_dirty
= true;
1819 sctx
->bindless_descriptors_dirty
= true;
1823 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1825 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1826 struct si_texture_handle
*, tex_handle
) {
1827 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1830 util_dynarray_foreach(&sctx
->resident_img_handles
,
1831 struct si_image_handle
*, img_handle
) {
1832 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1835 si_upload_bindless_descriptors(sctx
);
1838 /* Update mutable image descriptor fields of all bound textures. */
1839 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1843 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1844 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1845 struct si_images
*images
= &sctx
->images
[shader
];
1849 mask
= images
->enabled_mask
;
1851 unsigned i
= u_bit_scan(&mask
);
1852 struct pipe_image_view
*view
= &images
->views
[i
];
1854 if (!view
->resource
||
1855 view
->resource
->target
== PIPE_BUFFER
)
1858 si_set_shader_image(sctx
, shader
, i
, view
, true);
1861 /* Sampler views. */
1862 mask
= samplers
->enabled_mask
;
1864 unsigned i
= u_bit_scan(&mask
);
1865 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1869 view
->texture
->target
== PIPE_BUFFER
)
1872 si_set_sampler_view(sctx
, shader
, i
,
1873 samplers
->views
[i
], true);
1876 si_update_shader_needs_decompress_mask(sctx
, shader
);
1879 si_update_all_resident_texture_descriptors(sctx
);
1882 /* SHADER USER DATA */
1884 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1887 sctx
->shader_pointers_dirty
|=
1888 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1889 SI_NUM_SHADER_DESCS
);
1891 if (shader
== PIPE_SHADER_VERTEX
)
1892 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1894 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1897 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1899 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1900 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1901 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1902 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1903 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1906 /* Set a base register address for user data constants in the given shader.
1907 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1909 static void si_set_user_data_base(struct si_context
*sctx
,
1910 unsigned shader
, uint32_t new_base
)
1912 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1914 if (*base
!= new_base
) {
1918 si_mark_shader_pointers_dirty(sctx
, shader
);
1920 if (shader
== PIPE_SHADER_VERTEX
)
1921 sctx
->last_vs_state
= ~0;
1926 /* This must be called when these shaders are changed from non-NULL to NULL
1929 * - tessellation control shader
1930 * - tessellation evaluation shader
1932 void si_shader_change_notify(struct si_context
*sctx
)
1934 /* VS can be bound as VS, ES, or LS. */
1935 if (sctx
->tes_shader
.cso
) {
1936 if (sctx
->b
.chip_class
>= GFX9
) {
1937 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1938 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1940 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1941 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1943 } else if (sctx
->gs_shader
.cso
) {
1944 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1945 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1947 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1948 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1951 /* TES can be bound as ES, VS, or not bound. */
1952 if (sctx
->tes_shader
.cso
) {
1953 if (sctx
->gs_shader
.cso
)
1954 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1955 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1957 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1958 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1960 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1964 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
1965 struct si_descriptors
*desc
,
1967 unsigned pointer_count
)
1969 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* 2, 0));
1970 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1973 static void si_emit_shader_pointer_body(struct radeon_winsys_cs
*cs
,
1974 struct si_descriptors
*desc
)
1976 uint64_t va
= desc
->gpu_address
;
1978 radeon_emit(cs
, va
);
1979 radeon_emit(cs
, va
>> 32);
1982 static void si_emit_shader_pointer(struct si_context
*sctx
,
1983 struct si_descriptors
*desc
,
1986 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1988 si_emit_shader_pointer_head(cs
, desc
, sh_base
, 1);
1989 si_emit_shader_pointer_body(cs
, desc
);
1992 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
1993 unsigned pointer_mask
,
1999 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2000 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2004 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2006 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2008 si_emit_shader_pointer_head(cs
, descs
, sh_base
, count
);
2009 for (int i
= 0; i
< count
; i
++)
2010 si_emit_shader_pointer_body(cs
, descs
+ i
);
2014 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2015 struct si_descriptors
*descs
)
2017 if (sctx
->b
.chip_class
== GFX9
) {
2018 /* Broadcast it to all shader stages. */
2019 si_emit_shader_pointer(sctx
, descs
,
2020 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2024 si_emit_shader_pointer(sctx
, descs
,
2025 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2026 si_emit_shader_pointer(sctx
, descs
,
2027 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2028 si_emit_shader_pointer(sctx
, descs
,
2029 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2030 si_emit_shader_pointer(sctx
, descs
,
2031 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2032 si_emit_shader_pointer(sctx
, descs
,
2033 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2034 si_emit_shader_pointer(sctx
, descs
,
2035 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2038 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2039 struct r600_atom
*atom
)
2041 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2043 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2044 si_emit_global_shader_pointers(sctx
,
2045 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2048 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2049 sh_base
[PIPE_SHADER_VERTEX
]);
2050 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2051 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2052 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2053 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2054 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2055 sh_base
[PIPE_SHADER_GEOMETRY
]);
2056 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2057 sh_base
[PIPE_SHADER_FRAGMENT
]);
2059 sctx
->shader_pointers_dirty
&=
2060 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2062 if (sctx
->vertex_buffer_pointer_dirty
) {
2063 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2064 sh_base
[PIPE_SHADER_VERTEX
]);
2065 sctx
->vertex_buffer_pointer_dirty
= false;
2068 if (sctx
->graphics_bindless_pointer_dirty
) {
2069 si_emit_global_shader_pointers(sctx
,
2070 &sctx
->bindless_descriptors
);
2071 sctx
->graphics_bindless_pointer_dirty
= false;
2075 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2077 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2079 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2080 R_00B900_COMPUTE_USER_DATA_0
);
2081 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2083 if (sctx
->compute_bindless_pointer_dirty
) {
2084 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2085 sctx
->compute_bindless_pointer_dirty
= false;
2091 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2092 struct si_descriptors
*desc
,
2093 unsigned shader_userdata_index
,
2094 unsigned num_elements
)
2096 MAYBE_UNUSED
unsigned desc_slot
;
2098 si_init_descriptors(desc
, shader_userdata_index
, 16, num_elements
);
2099 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2101 /* The first bindless descriptor is stored at slot 1, because 0 is not
2102 * considered to be a valid handle.
2104 sctx
->num_bindless_descriptors
= 1;
2106 /* Track which bindless slots are used (or not). */
2107 util_idalloc_init(&sctx
->bindless_used_slots
);
2108 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2110 /* Reserve slot 0 because it's an invalid handle for bindless. */
2111 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2112 assert(desc_slot
== 0);
2115 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2117 si_release_descriptors(&sctx
->bindless_descriptors
);
2118 util_idalloc_fini(&sctx
->bindless_used_slots
);
2121 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2123 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2126 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2127 if (desc_slot
>= desc
->num_elements
) {
2128 /* The array of bindless descriptors is full, resize it. */
2129 unsigned slot_size
= desc
->element_dw_size
* 4;
2130 unsigned new_num_elements
= desc
->num_elements
* 2;
2132 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2133 new_num_elements
* slot_size
);
2134 desc
->num_elements
= new_num_elements
;
2135 desc
->num_active_slots
= new_num_elements
;
2143 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2146 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2147 unsigned desc_slot
, desc_slot_offset
;
2149 /* Find a free slot. */
2150 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2152 /* For simplicity, sampler and image bindless descriptors use fixed
2153 * 16-dword slots for now. Image descriptors only need 8-dword but this
2154 * doesn't really matter because no real apps use image handles.
2156 desc_slot_offset
= desc_slot
* 16;
2158 /* Copy the descriptor into the array. */
2159 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2161 /* Re-upload the whole array of bindless descriptors into a new buffer.
2163 if (!si_upload_descriptors(sctx
, desc
))
2166 /* Make sure to re-emit the shader pointers for all stages. */
2167 sctx
->graphics_bindless_pointer_dirty
= true;
2168 sctx
->compute_bindless_pointer_dirty
= true;
2173 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2175 struct pipe_resource
*resource
,
2179 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2180 struct r600_resource
*buf
= r600_resource(resource
);
2181 unsigned desc_slot_offset
= desc_slot
* 16;
2182 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2183 uint64_t old_desc_va
;
2185 assert(resource
->target
== PIPE_BUFFER
);
2187 /* Retrieve the old buffer addr from the descriptor. */
2188 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2190 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2191 /* The buffer has been invalidated when the handle wasn't
2192 * resident, update the descriptor and the dirty flag.
2194 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2200 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2201 struct pipe_sampler_view
*view
,
2202 const struct pipe_sampler_state
*state
)
2204 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2205 struct si_context
*sctx
= (struct si_context
*)ctx
;
2206 struct si_texture_handle
*tex_handle
;
2207 struct si_sampler_state
*sstate
;
2208 uint32_t desc_list
[16];
2211 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2215 memset(desc_list
, 0, sizeof(desc_list
));
2216 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2218 sstate
= ctx
->create_sampler_state(ctx
, state
);
2224 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2225 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2226 ctx
->delete_sampler_state(ctx
, sstate
);
2228 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2230 if (!tex_handle
->desc_slot
) {
2235 handle
= tex_handle
->desc_slot
;
2237 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)handle
,
2243 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2245 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2250 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2252 struct si_context
*sctx
= (struct si_context
*)ctx
;
2253 struct si_texture_handle
*tex_handle
;
2254 struct hash_entry
*entry
;
2256 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2260 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2262 /* Allow this descriptor slot to be re-used. */
2263 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2265 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2266 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2270 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2271 uint64_t handle
, bool resident
)
2273 struct si_context
*sctx
= (struct si_context
*)ctx
;
2274 struct si_texture_handle
*tex_handle
;
2275 struct si_sampler_view
*sview
;
2276 struct hash_entry
*entry
;
2278 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2282 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2283 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2286 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2287 struct r600_texture
*rtex
=
2288 (struct r600_texture
*)sview
->base
.texture
;
2290 if (depth_needs_decompression(rtex
)) {
2291 util_dynarray_append(
2292 &sctx
->resident_tex_needs_depth_decompress
,
2293 struct si_texture_handle
*,
2297 if (color_needs_decompression(rtex
)) {
2298 util_dynarray_append(
2299 &sctx
->resident_tex_needs_color_decompress
,
2300 struct si_texture_handle
*,
2304 if (rtex
->dcc_offset
&&
2305 p_atomic_read(&rtex
->framebuffers_bound
))
2306 sctx
->need_check_render_feedback
= true;
2308 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2310 si_update_bindless_buffer_descriptor(sctx
,
2311 tex_handle
->desc_slot
,
2312 sview
->base
.texture
,
2313 sview
->base
.u
.buf
.offset
,
2314 &tex_handle
->desc_dirty
);
2317 /* Re-upload the descriptor if it has been updated while it
2320 if (tex_handle
->desc_dirty
)
2321 sctx
->bindless_descriptors_dirty
= true;
2323 /* Add the texture handle to the per-context list. */
2324 util_dynarray_append(&sctx
->resident_tex_handles
,
2325 struct si_texture_handle
*, tex_handle
);
2327 /* Add the buffers to the current CS in case si_begin_new_cs()
2328 * is not going to be called.
2330 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2332 sview
->is_stencil_sampler
, false);
2334 /* Remove the texture handle from the per-context list. */
2335 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2336 struct si_texture_handle
*,
2339 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2340 util_dynarray_delete_unordered(
2341 &sctx
->resident_tex_needs_depth_decompress
,
2342 struct si_texture_handle
*, tex_handle
);
2344 util_dynarray_delete_unordered(
2345 &sctx
->resident_tex_needs_color_decompress
,
2346 struct si_texture_handle
*, tex_handle
);
2351 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2352 const struct pipe_image_view
*view
)
2354 struct si_context
*sctx
= (struct si_context
*)ctx
;
2355 struct si_image_handle
*img_handle
;
2356 uint32_t desc_list
[8];
2359 if (!view
|| !view
->resource
)
2362 img_handle
= CALLOC_STRUCT(si_image_handle
);
2366 memset(desc_list
, 0, sizeof(desc_list
));
2367 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2369 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2371 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2373 if (!img_handle
->desc_slot
) {
2378 handle
= img_handle
->desc_slot
;
2380 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)handle
,
2386 util_copy_image_view(&img_handle
->view
, view
);
2388 r600_resource(view
->resource
)->image_handle_allocated
= true;
2393 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2395 struct si_context
*sctx
= (struct si_context
*)ctx
;
2396 struct si_image_handle
*img_handle
;
2397 struct hash_entry
*entry
;
2399 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2403 img_handle
= (struct si_image_handle
*)entry
->data
;
2405 util_copy_image_view(&img_handle
->view
, NULL
);
2406 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2410 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2411 uint64_t handle
, unsigned access
,
2414 struct si_context
*sctx
= (struct si_context
*)ctx
;
2415 struct si_image_handle
*img_handle
;
2416 struct pipe_image_view
*view
;
2417 struct r600_resource
*res
;
2418 struct hash_entry
*entry
;
2420 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2424 img_handle
= (struct si_image_handle
*)entry
->data
;
2425 view
= &img_handle
->view
;
2426 res
= (struct r600_resource
*)view
->resource
;
2429 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2430 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2431 unsigned level
= view
->u
.tex
.level
;
2433 if (color_needs_decompression(rtex
)) {
2434 util_dynarray_append(
2435 &sctx
->resident_img_needs_color_decompress
,
2436 struct si_image_handle
*,
2440 if (vi_dcc_enabled(rtex
, level
) &&
2441 p_atomic_read(&rtex
->framebuffers_bound
))
2442 sctx
->need_check_render_feedback
= true;
2444 si_update_bindless_image_descriptor(sctx
, img_handle
);
2446 si_update_bindless_buffer_descriptor(sctx
,
2447 img_handle
->desc_slot
,
2450 &img_handle
->desc_dirty
);
2453 /* Re-upload the descriptor if it has been updated while it
2456 if (img_handle
->desc_dirty
)
2457 sctx
->bindless_descriptors_dirty
= true;
2459 /* Add the image handle to the per-context list. */
2460 util_dynarray_append(&sctx
->resident_img_handles
,
2461 struct si_image_handle
*, img_handle
);
2463 /* Add the buffers to the current CS in case si_begin_new_cs()
2464 * is not going to be called.
2466 si_sampler_view_add_buffer(sctx
, view
->resource
,
2467 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2468 RADEON_USAGE_READWRITE
:
2469 RADEON_USAGE_READ
, false, false);
2471 /* Remove the image handle from the per-context list. */
2472 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2473 struct si_image_handle
*,
2476 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2477 util_dynarray_delete_unordered(
2478 &sctx
->resident_img_needs_color_decompress
,
2479 struct si_image_handle
*,
2486 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2488 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2490 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2491 sizeof(struct si_texture_handle
*);
2492 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2493 sizeof(struct si_image_handle
*);
2495 /* Add all resident texture handles. */
2496 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2497 struct si_texture_handle
*, tex_handle
) {
2498 struct si_sampler_view
*sview
=
2499 (struct si_sampler_view
*)(*tex_handle
)->view
;
2501 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2503 sview
->is_stencil_sampler
, false);
2506 /* Add all resident image handles. */
2507 util_dynarray_foreach(&sctx
->resident_img_handles
,
2508 struct si_image_handle
*, img_handle
) {
2509 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2511 si_sampler_view_add_buffer(sctx
, view
->resource
,
2512 RADEON_USAGE_READWRITE
,
2516 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2517 num_resident_img_handles
;
2520 /* INIT/DEINIT/UPLOAD */
2522 void si_init_all_descriptors(struct si_context
*sctx
)
2526 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2527 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2529 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2530 bool gfx9_tcs
= false;
2531 bool gfx9_gs
= false;
2532 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2533 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2535 if (sctx
->b
.chip_class
>= GFX9
) {
2536 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2537 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2540 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2541 si_const_and_shader_buffer_descriptors(sctx
, i
),
2543 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2544 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2545 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2546 RADEON_USAGE_READWRITE
,
2548 RADEON_PRIO_SHADER_RW_BUFFER
,
2549 RADEON_PRIO_CONST_BUFFER
);
2551 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, i
);
2552 si_init_descriptors(desc
,
2553 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2554 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2555 SI_SGPR_SAMPLERS_AND_IMAGES
,
2556 16, num_sampler_slots
);
2559 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2560 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2561 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2562 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2565 si_init_buffer_resources(&sctx
->rw_buffers
,
2566 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2567 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2568 /* The second set of usage/priority is used by
2569 * const buffers in RW buffer slots. */
2570 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2571 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2572 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2574 si_init_descriptors(&sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2575 4, SI_NUM_VERTEX_BUFFERS
);
2576 FREE(sctx
->vertex_buffers
.list
); /* not used */
2577 sctx
->vertex_buffers
.list
= NULL
;
2579 /* Initialize an array of 1024 bindless descriptors, when the limit is
2580 * reached, just make it larger and re-upload the whole array.
2582 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2583 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2586 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2588 /* Set pipe_context functions. */
2589 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2590 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2591 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2592 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2593 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2594 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2595 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2596 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2597 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2598 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2599 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2600 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2601 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2602 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2604 /* Shader user data. */
2605 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2606 si_emit_graphics_shader_pointers
);
2608 /* Set default and immutable mappings. */
2609 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2611 if (sctx
->b
.chip_class
>= GFX9
) {
2612 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2613 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2614 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2615 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2617 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2618 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2619 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2620 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2622 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2625 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2627 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2629 /* Assume nothing will go wrong: */
2630 sctx
->shader_pointers_dirty
|= dirty
;
2633 unsigned i
= u_bit_scan(&dirty
);
2635 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2639 sctx
->descriptors_dirty
&= ~mask
;
2641 si_upload_bindless_descriptors(sctx
);
2646 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2648 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2649 return si_upload_shader_descriptors(sctx
, mask
);
2652 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2654 /* Does not update rw_buffers as that is not needed for compute shaders
2655 * and the input buffer is using the same SGPR's anyway.
2657 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2658 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2659 return si_upload_shader_descriptors(sctx
, mask
);
2662 void si_release_all_descriptors(struct si_context
*sctx
)
2666 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2667 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2668 si_const_and_shader_buffer_descriptors(sctx
, i
));
2669 si_release_sampler_views(&sctx
->samplers
[i
]);
2670 si_release_image_views(&sctx
->images
[i
]);
2672 si_release_buffer_resources(&sctx
->rw_buffers
,
2673 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2674 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2675 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2677 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2678 si_release_descriptors(&sctx
->descriptors
[i
]);
2680 sctx
->vertex_buffers
.list
= NULL
; /* points into a mapped buffer */
2681 si_release_descriptors(&sctx
->vertex_buffers
);
2682 si_release_bindless_descriptors(sctx
);
2685 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2689 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2690 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2691 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2692 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2694 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2695 si_vertex_buffers_begin_new_cs(sctx
);
2697 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2698 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2699 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2701 si_shader_pointers_begin_new_cs(sctx
);
2704 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2705 uint64_t new_active_mask
)
2707 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2709 /* Ignore no-op updates and updates that disable all slots. */
2710 if (!new_active_mask
||
2711 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2712 desc
->num_active_slots
))
2716 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2717 assert(new_active_mask
== 0);
2719 /* Upload/dump descriptors if slots are being enabled. */
2720 if (first
< desc
->first_active_slot
||
2721 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2722 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2724 desc
->first_active_slot
= first
;
2725 desc
->num_active_slots
= count
;
2728 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2729 struct si_shader_selector
*sel
)
2734 si_set_active_descriptors(sctx
,
2735 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2736 sel
->active_const_and_shader_buffers
);
2737 si_set_active_descriptors(sctx
,
2738 si_sampler_and_image_descriptors_idx(sel
->type
),
2739 sel
->active_samplers_and_images
);