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winsys/radeon: fold cs_set_flush_callback into cs_create
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26 #include "../radeon/r600_cs.h"
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30
31 #include "util/u_memory.h"
32 #include "util/u_upload_mgr.h"
33
34 #define SI_NUM_CONTEXTS 16
35
36 static uint32_t null_desc[8]; /* zeros */
37
38 /* Set this if you want the 3D engine to wait until CP DMA is done.
39 * It should be set on the last CP DMA packet. */
40 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
41
42 /* Set this if the source data was used as a destination in a previous CP DMA
43 * packet. It's for preventing a read-after-write (RAW) hazard between two
44 * CP DMA packets. */
45 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
46
47 /* Emit a CP DMA packet to do a copy from one buffer to another.
48 * The size must fit in bits [20:0].
49 */
50 static void si_emit_cp_dma_copy_buffer(struct si_context *sctx,
51 uint64_t dst_va, uint64_t src_va,
52 unsigned size, unsigned flags)
53 {
54 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
55 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
56 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
57
58 assert(size);
59 assert((size & ((1<<21)-1)) == size);
60
61 if (sctx->b.chip_class >= CIK) {
62 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
63 radeon_emit(cs, sync_flag); /* CP_SYNC [31] */
64 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
65 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
66 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
67 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
68 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
69 } else {
70 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
71 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
72 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
73 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
74 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
75 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
76 }
77 }
78
79 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
80 static void si_emit_cp_dma_clear_buffer(struct si_context *sctx,
81 uint64_t dst_va, unsigned size,
82 uint32_t clear_value, unsigned flags)
83 {
84 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
85 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
86 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
87
88 assert(size);
89 assert((size & ((1<<21)-1)) == size);
90
91 if (sctx->b.chip_class >= CIK) {
92 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
93 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
94 radeon_emit(cs, clear_value); /* DATA [31:0] */
95 radeon_emit(cs, 0);
96 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
97 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
98 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
99 } else {
100 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
101 radeon_emit(cs, clear_value); /* DATA [31:0] */
102 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
103 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
104 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
105 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
106 }
107 }
108
109 static void si_init_descriptors(struct si_context *sctx,
110 struct si_descriptors *desc,
111 unsigned shader_userdata_reg,
112 unsigned element_dw_size,
113 unsigned num_elements,
114 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
115 {
116 uint64_t va;
117
118 assert(num_elements <= sizeof(desc->enabled_mask)*8);
119 assert(num_elements <= sizeof(desc->dirty_mask)*8);
120
121 desc->atom.emit = (void*)emit_func;
122 desc->shader_userdata_reg = shader_userdata_reg;
123 desc->element_dw_size = element_dw_size;
124 desc->num_elements = num_elements;
125 desc->context_size = num_elements * element_dw_size * 4;
126
127 desc->buffer = (struct r600_resource*)
128 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
129 PIPE_USAGE_DEFAULT,
130 SI_NUM_CONTEXTS * desc->context_size);
131
132 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer,
133 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
134 va = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b);
135
136 /* We don't check for CS space here, because this should be called
137 * only once at context initialization. */
138 si_emit_cp_dma_clear_buffer(sctx, va, desc->buffer->b.b.width0, 0,
139 R600_CP_DMA_SYNC);
140 }
141
142 static void si_release_descriptors(struct si_descriptors *desc)
143 {
144 pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
145 }
146
147 static void si_update_descriptors(struct si_context *sctx,
148 struct si_descriptors *desc)
149 {
150 if (desc->dirty_mask) {
151 desc->atom.num_dw =
152 7 + /* copy */
153 (4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
154 4; /* pointer update */
155 #if HAVE_LLVM >= 0x0305
156 if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
157 desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0)
158 desc->atom.num_dw += 4; /* second pointer update */
159 #endif
160 desc->atom.dirty = true;
161 /* The descriptors are read with the K cache. */
162 sctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
163 } else {
164 desc->atom.dirty = false;
165 }
166 }
167
168 static void si_emit_shader_pointer(struct si_context *sctx,
169 struct si_descriptors *desc)
170 {
171 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
172 uint64_t va = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b) +
173 desc->current_context_id * desc->context_size;
174
175 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
176 radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2);
177 radeon_emit(cs, va);
178 radeon_emit(cs, va >> 32);
179
180 #if HAVE_LLVM >= 0x0305
181 if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
182 desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0) {
183 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
184 radeon_emit(cs, (desc->shader_userdata_reg +
185 (R_00B330_SPI_SHADER_USER_DATA_ES_0 -
186 R_00B130_SPI_SHADER_USER_DATA_VS_0) -
187 SI_SH_REG_OFFSET) >> 2);
188 radeon_emit(cs, va);
189 radeon_emit(cs, va >> 32);
190 }
191 #endif
192 }
193
194 static void si_emit_descriptors(struct si_context *sctx,
195 struct si_descriptors *desc,
196 uint32_t **descriptors)
197 {
198 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
199 uint64_t va_base;
200 int packet_start;
201 int packet_size = 0;
202 int last_index = desc->num_elements; /* point to a non-existing element */
203 unsigned dirty_mask = desc->dirty_mask;
204 unsigned new_context_id = (desc->current_context_id + 1) % SI_NUM_CONTEXTS;
205
206 assert(dirty_mask);
207
208 va_base = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b);
209
210 /* Copy the descriptors to a new context slot. */
211 /* XXX Consider using TC or L2 for this copy on CIK. */
212 si_emit_cp_dma_copy_buffer(sctx,
213 va_base + new_context_id * desc->context_size,
214 va_base + desc->current_context_id * desc->context_size,
215 desc->context_size, R600_CP_DMA_SYNC);
216
217 va_base += new_context_id * desc->context_size;
218
219 /* Update the descriptors.
220 * Updates of consecutive descriptors are merged to one WRITE_DATA packet.
221 *
222 * XXX When unbinding lots of resources, consider clearing the memory
223 * with CP DMA instead of emitting zeros.
224 */
225 while (dirty_mask) {
226 int i = u_bit_scan(&dirty_mask);
227
228 assert(i < desc->num_elements);
229
230 if (last_index+1 == i && packet_size) {
231 /* Append new data at the end of the last packet. */
232 packet_size += desc->element_dw_size;
233 cs->buf[packet_start] = PKT3(PKT3_WRITE_DATA, packet_size, 0);
234 } else {
235 /* Start a new packet. */
236 uint64_t va = va_base + i * desc->element_dw_size * 4;
237
238 packet_start = cs->cdw;
239 packet_size = 2 + desc->element_dw_size;
240
241 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, packet_size, 0));
242 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_TC_OR_L2) |
243 PKT3_WRITE_DATA_WR_CONFIRM |
244 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
245 radeon_emit(cs, va & 0xFFFFFFFFUL);
246 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
247 }
248
249 radeon_emit_array(cs, descriptors[i], desc->element_dw_size);
250
251 last_index = i;
252 }
253
254 desc->dirty_mask = 0;
255 desc->current_context_id = new_context_id;
256
257 /* Now update the shader userdata pointer. */
258 si_emit_shader_pointer(sctx, desc);
259 }
260
261 static unsigned si_get_shader_user_data_base(unsigned shader)
262 {
263 switch (shader) {
264 case PIPE_SHADER_VERTEX:
265 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
266 case PIPE_SHADER_GEOMETRY:
267 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
268 case PIPE_SHADER_FRAGMENT:
269 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
270 default:
271 assert(0);
272 return 0;
273 }
274 }
275
276 /* SAMPLER VIEWS */
277
278 static void si_emit_sampler_views(struct si_context *sctx, struct r600_atom *atom)
279 {
280 struct si_sampler_views *views = (struct si_sampler_views*)atom;
281
282 si_emit_descriptors(sctx, &views->desc, views->desc_data);
283 }
284
285 static void si_init_sampler_views(struct si_context *sctx,
286 struct si_sampler_views *views,
287 unsigned shader)
288 {
289 si_init_descriptors(sctx, &views->desc,
290 si_get_shader_user_data_base(shader) +
291 SI_SGPR_RESOURCE * 4,
292 8, NUM_SAMPLER_VIEWS, si_emit_sampler_views);
293 }
294
295 static void si_release_sampler_views(struct si_sampler_views *views)
296 {
297 int i;
298
299 for (i = 0; i < Elements(views->views); i++) {
300 pipe_sampler_view_reference(&views->views[i], NULL);
301 }
302 si_release_descriptors(&views->desc);
303 }
304
305 static enum radeon_bo_priority si_get_resource_ro_priority(struct r600_resource *res)
306 {
307 if (res->b.b.target == PIPE_BUFFER)
308 return RADEON_PRIO_SHADER_BUFFER_RO;
309
310 if (res->b.b.nr_samples > 1)
311 return RADEON_PRIO_SHADER_TEXTURE_MSAA;
312
313 return RADEON_PRIO_SHADER_TEXTURE_RO;
314 }
315
316 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
317 struct si_sampler_views *views)
318 {
319 unsigned mask = views->desc.enabled_mask;
320
321 /* Add relocations to the CS. */
322 while (mask) {
323 int i = u_bit_scan(&mask);
324 struct si_pipe_sampler_view *rview =
325 (struct si_pipe_sampler_view*)views->views[i];
326
327 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
328 rview->resource, RADEON_USAGE_READ,
329 si_get_resource_ro_priority(rview->resource));
330 }
331
332 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer,
333 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
334
335 si_emit_shader_pointer(sctx, &views->desc);
336 }
337
338 void si_set_sampler_view(struct si_context *sctx, unsigned shader,
339 unsigned slot, struct pipe_sampler_view *view,
340 unsigned *view_desc)
341 {
342 struct si_sampler_views *views = &sctx->samplers[shader].views;
343
344 if (views->views[slot] == view)
345 return;
346
347 if (view) {
348 struct si_pipe_sampler_view *rview =
349 (struct si_pipe_sampler_view*)view;
350
351 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
352 rview->resource, RADEON_USAGE_READ,
353 si_get_resource_ro_priority(rview->resource));
354
355 pipe_sampler_view_reference(&views->views[slot], view);
356 views->desc_data[slot] = view_desc;
357 views->desc.enabled_mask |= 1 << slot;
358 } else {
359 pipe_sampler_view_reference(&views->views[slot], NULL);
360 views->desc_data[slot] = null_desc;
361 views->desc.enabled_mask &= ~(1 << slot);
362 }
363
364 views->desc.dirty_mask |= 1 << slot;
365 si_update_descriptors(sctx, &views->desc);
366 }
367
368 /* BUFFER RESOURCES */
369
370 static void si_emit_buffer_resources(struct si_context *sctx, struct r600_atom *atom)
371 {
372 struct si_buffer_resources *buffers = (struct si_buffer_resources*)atom;
373
374 si_emit_descriptors(sctx, &buffers->desc, buffers->desc_data);
375 }
376
377 static void si_init_buffer_resources(struct si_context *sctx,
378 struct si_buffer_resources *buffers,
379 unsigned num_buffers, unsigned shader,
380 unsigned shader_userdata_index,
381 enum radeon_bo_usage shader_usage,
382 enum radeon_bo_priority priority)
383 {
384 int i;
385
386 buffers->num_buffers = num_buffers;
387 buffers->shader_usage = shader_usage;
388 buffers->priority = priority;
389 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
390 buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
391
392 /* si_emit_descriptors only accepts an array of arrays.
393 * This adds such an array. */
394 buffers->desc_data = CALLOC(num_buffers, sizeof(uint32_t*));
395 for (i = 0; i < num_buffers; i++) {
396 buffers->desc_data[i] = &buffers->desc_storage[i*4];
397 }
398
399 si_init_descriptors(sctx, &buffers->desc,
400 si_get_shader_user_data_base(shader) +
401 shader_userdata_index*4, 4, num_buffers,
402 si_emit_buffer_resources);
403 }
404
405 static void si_release_buffer_resources(struct si_buffer_resources *buffers)
406 {
407 int i;
408
409 for (i = 0; i < buffers->num_buffers; i++) {
410 pipe_resource_reference(&buffers->buffers[i], NULL);
411 }
412
413 FREE(buffers->buffers);
414 FREE(buffers->desc_storage);
415 FREE(buffers->desc_data);
416 si_release_descriptors(&buffers->desc);
417 }
418
419 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
420 struct si_buffer_resources *buffers)
421 {
422 unsigned mask = buffers->desc.enabled_mask;
423
424 /* Add relocations to the CS. */
425 while (mask) {
426 int i = u_bit_scan(&mask);
427
428 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
429 (struct r600_resource*)buffers->buffers[i],
430 buffers->shader_usage, buffers->priority);
431 }
432
433 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
434 buffers->desc.buffer, RADEON_USAGE_READWRITE,
435 RADEON_PRIO_SHADER_DATA);
436
437 si_emit_shader_pointer(sctx, &buffers->desc);
438 }
439
440 /* CONSTANT BUFFERS */
441
442 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
443 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
444 {
445 if (SI_BIG_ENDIAN) {
446 uint32_t *tmpPtr;
447 unsigned i;
448
449 if (!(tmpPtr = malloc(size))) {
450 R600_ERR("Failed to allocate BE swap buffer.\n");
451 return;
452 }
453
454 for (i = 0; i < size / 4; ++i) {
455 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
456 }
457
458 u_upload_data(sctx->b.uploader, 0, size, tmpPtr, const_offset,
459 (struct pipe_resource**)rbuffer);
460
461 free(tmpPtr);
462 } else {
463 u_upload_data(sctx->b.uploader, 0, size, ptr, const_offset,
464 (struct pipe_resource**)rbuffer);
465 }
466 }
467
468 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint slot,
469 struct pipe_constant_buffer *input)
470 {
471 struct si_context *sctx = (struct si_context *)ctx;
472 struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
473
474 if (shader >= SI_NUM_SHADERS)
475 return;
476
477 assert(slot < buffers->num_buffers);
478 pipe_resource_reference(&buffers->buffers[slot], NULL);
479
480 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
481 * with a NULL buffer). We need to use a dummy buffer instead. */
482 if (sctx->b.chip_class == CIK &&
483 (!input || (!input->buffer && !input->user_buffer)))
484 input = &sctx->null_const_buf;
485
486 if (input && (input->buffer || input->user_buffer)) {
487 struct pipe_resource *buffer = NULL;
488 uint64_t va;
489
490 /* Upload the user buffer if needed. */
491 if (input->user_buffer) {
492 unsigned buffer_offset;
493
494 si_upload_const_buffer(sctx,
495 (struct r600_resource**)&buffer, input->user_buffer,
496 input->buffer_size, &buffer_offset);
497 va = r600_resource_va(ctx->screen, buffer) + buffer_offset;
498 } else {
499 pipe_resource_reference(&buffer, input->buffer);
500 va = r600_resource_va(ctx->screen, buffer) + input->buffer_offset;
501 }
502
503 /* Set the descriptor. */
504 uint32_t *desc = buffers->desc_data[slot];
505 desc[0] = va;
506 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
507 S_008F04_STRIDE(0);
508 desc[2] = input->buffer_size;
509 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
510 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
511 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
512 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
513 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
514 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
515
516 buffers->buffers[slot] = buffer;
517 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
518 (struct r600_resource*)buffer,
519 buffers->shader_usage, buffers->priority);
520 buffers->desc.enabled_mask |= 1 << slot;
521 } else {
522 /* Clear the descriptor. */
523 memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4);
524 buffers->desc.enabled_mask &= ~(1 << slot);
525 }
526
527 buffers->desc.dirty_mask |= 1 << slot;
528 si_update_descriptors(sctx, &buffers->desc);
529 }
530
531 /* RING BUFFERS */
532
533 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
534 struct pipe_constant_buffer *input,
535 unsigned stride, unsigned num_records,
536 bool add_tid, bool swizzle,
537 unsigned element_size, unsigned index_stride)
538 {
539 struct si_context *sctx = (struct si_context *)ctx;
540 struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
541
542 if (shader >= SI_NUM_SHADERS)
543 return;
544
545 /* The stride field in the resource descriptor has 14 bits */
546 assert(stride < (1 << 14));
547
548 assert(slot < buffers->num_buffers);
549 pipe_resource_reference(&buffers->buffers[slot], NULL);
550
551 if (input && input->buffer) {
552 uint64_t va;
553
554 va = r600_resource_va(ctx->screen, input->buffer);
555
556 switch (element_size) {
557 default:
558 assert(!"Unsupported ring buffer element size");
559 case 0:
560 case 2:
561 element_size = 0;
562 break;
563 case 4:
564 element_size = 1;
565 break;
566 case 8:
567 element_size = 2;
568 break;
569 case 16:
570 element_size = 3;
571 break;
572 }
573
574 switch (index_stride) {
575 default:
576 assert(!"Unsupported ring buffer index stride");
577 case 0:
578 case 8:
579 index_stride = 0;
580 break;
581 case 16:
582 index_stride = 1;
583 break;
584 case 32:
585 index_stride = 2;
586 break;
587 case 64:
588 index_stride = 3;
589 break;
590 }
591
592 /* Set the descriptor. */
593 uint32_t *desc = buffers->desc_data[slot];
594 desc[0] = va;
595 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
596 S_008F04_STRIDE(stride) |
597 S_008F04_SWIZZLE_ENABLE(swizzle);
598 desc[2] = num_records;
599 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
600 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
601 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
602 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
603 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
604 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
605 S_008F0C_ELEMENT_SIZE(element_size) |
606 S_008F0C_INDEX_STRIDE(index_stride) |
607 S_008F0C_ADD_TID_ENABLE(add_tid);
608
609 pipe_resource_reference(&buffers->buffers[slot], input->buffer);
610 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
611 (struct r600_resource*)input->buffer,
612 buffers->shader_usage, buffers->priority);
613 buffers->desc.enabled_mask |= 1 << slot;
614 } else {
615 /* Clear the descriptor. */
616 memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4);
617 buffers->desc.enabled_mask &= ~(1 << slot);
618 }
619
620 buffers->desc.dirty_mask |= 1 << slot;
621 si_update_descriptors(sctx, &buffers->desc);
622 }
623
624 /* STREAMOUT BUFFERS */
625
626 static void si_set_streamout_targets(struct pipe_context *ctx,
627 unsigned num_targets,
628 struct pipe_stream_output_target **targets,
629 const unsigned *offsets)
630 {
631 struct si_context *sctx = (struct si_context *)ctx;
632 struct si_buffer_resources *buffers = &sctx->rw_buffers[PIPE_SHADER_VERTEX];
633 unsigned old_num_targets = sctx->b.streamout.num_targets;
634 unsigned i, bufidx;
635
636 /* Streamout buffers must be bound in 2 places:
637 * 1) in VGT by setting the VGT_STRMOUT registers
638 * 2) as shader resources
639 */
640
641 /* Set the VGT regs. */
642 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
643
644 /* Set the shader resources.*/
645 for (i = 0; i < num_targets; i++) {
646 bufidx = SI_RW_SO + i;
647
648 if (targets[i]) {
649 struct pipe_resource *buffer = targets[i]->buffer;
650 uint64_t va = r600_resource_va(ctx->screen, buffer);
651
652 /* Set the descriptor. */
653 uint32_t *desc = buffers->desc_data[bufidx];
654 desc[0] = va;
655 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
656 desc[2] = 0xffffffff;
657 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
658 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
659 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
660 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
661
662 /* Set the resource. */
663 pipe_resource_reference(&buffers->buffers[bufidx],
664 buffer);
665 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
666 (struct r600_resource*)buffer,
667 buffers->shader_usage, buffers->priority);
668 buffers->desc.enabled_mask |= 1 << bufidx;
669 } else {
670 /* Clear the descriptor and unset the resource. */
671 memset(buffers->desc_data[bufidx], 0,
672 sizeof(uint32_t) * 4);
673 pipe_resource_reference(&buffers->buffers[bufidx],
674 NULL);
675 buffers->desc.enabled_mask &= ~(1 << bufidx);
676 }
677 buffers->desc.dirty_mask |= 1 << bufidx;
678 }
679 for (; i < old_num_targets; i++) {
680 bufidx = SI_RW_SO + i;
681 /* Clear the descriptor and unset the resource. */
682 memset(buffers->desc_data[bufidx], 0, sizeof(uint32_t) * 4);
683 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
684 buffers->desc.enabled_mask &= ~(1 << bufidx);
685 buffers->desc.dirty_mask |= 1 << bufidx;
686 }
687
688 si_update_descriptors(sctx, &buffers->desc);
689 }
690
691 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
692 uint32_t *desc, uint64_t old_buf_va,
693 struct pipe_resource *new_buf)
694 {
695 /* Retrieve the buffer offset from the descriptor. */
696 uint64_t old_desc_va =
697 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
698
699 assert(old_buf_va <= old_desc_va);
700 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
701
702 /* Update the descriptor. */
703 uint64_t va = r600_resource_va(ctx->screen, new_buf) + offset_within_buffer;
704
705 desc[0] = va;
706 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
707 S_008F04_BASE_ADDRESS_HI(va >> 32);
708 }
709
710 /* BUFFER DISCARD/INVALIDATION */
711
712 /* Reallocate a buffer a update all resource bindings where the buffer is
713 * bound.
714 *
715 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
716 * idle by discarding its contents. Apps usually tell us when to do this using
717 * map_buffer flags, for example.
718 */
719 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
720 {
721 struct si_context *sctx = (struct si_context*)ctx;
722 struct r600_resource *rbuffer = r600_resource(buf);
723 unsigned i, shader, alignment = rbuffer->buf->alignment;
724 uint64_t old_va = r600_resource_va(ctx->screen, buf);
725
726 /* Reallocate the buffer in the same pipe_resource. */
727 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
728 alignment, TRUE);
729
730 /* We changed the buffer, now we need to bind it where the old one
731 * was bound. This consists of 2 things:
732 * 1) Updating the resource descriptor and dirtying it.
733 * 2) Adding a relocation to the CS, so that it's usable.
734 */
735
736 /* Vertex buffers. */
737 /* Nothing to do. Vertex buffer bindings are updated before every draw call. */
738
739 /* Read/Write buffers. */
740 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
741 struct si_buffer_resources *buffers = &sctx->rw_buffers[shader];
742 bool found = false;
743 uint32_t mask = buffers->desc.enabled_mask;
744
745 while (mask) {
746 i = u_bit_scan(&mask);
747 if (buffers->buffers[i] == buf) {
748 si_desc_reset_buffer_offset(ctx, buffers->desc_data[i],
749 old_va, buf);
750
751 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
752 rbuffer, buffers->shader_usage,
753 buffers->priority);
754
755 buffers->desc.dirty_mask |= 1 << i;
756 found = true;
757
758 if (i >= SI_RW_SO && shader == PIPE_SHADER_VERTEX) {
759 /* Update the streamout state. */
760 if (sctx->b.streamout.begin_emitted) {
761 r600_emit_streamout_end(&sctx->b);
762 }
763 sctx->b.streamout.append_bitmask =
764 sctx->b.streamout.enabled_mask;
765 r600_streamout_buffers_dirty(&sctx->b);
766 }
767 }
768 }
769 if (found) {
770 si_update_descriptors(sctx, &buffers->desc);
771 }
772 }
773
774 /* Constant buffers. */
775 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
776 struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
777 bool found = false;
778 uint32_t mask = buffers->desc.enabled_mask;
779
780 while (mask) {
781 unsigned i = u_bit_scan(&mask);
782 if (buffers->buffers[i] == buf) {
783 si_desc_reset_buffer_offset(ctx, buffers->desc_data[i],
784 old_va, buf);
785
786 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
787 rbuffer, buffers->shader_usage,
788 buffers->priority);
789
790 buffers->desc.dirty_mask |= 1 << i;
791 found = true;
792 }
793 }
794 if (found) {
795 si_update_descriptors(sctx, &buffers->desc);
796 }
797 }
798
799 /* Texture buffers. */
800 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
801 struct si_sampler_views *views = &sctx->samplers[shader].views;
802 bool found = false;
803 uint32_t mask = views->desc.enabled_mask;
804
805 while (mask) {
806 unsigned i = u_bit_scan(&mask);
807 if (views->views[i]->texture == buf) {
808 /* This updates the sampler view directly. */
809 si_desc_reset_buffer_offset(ctx, views->desc_data[i],
810 old_va, buf);
811
812 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
813 rbuffer, RADEON_USAGE_READ,
814 RADEON_PRIO_SHADER_BUFFER_RO);
815
816 views->desc.dirty_mask |= 1 << i;
817 found = true;
818 }
819 }
820 if (found) {
821 si_update_descriptors(sctx, &views->desc);
822 }
823 }
824 }
825
826 /* CP DMA */
827
828 /* The max number of bytes to copy per packet. */
829 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
830
831 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
832 unsigned offset, unsigned size, unsigned value)
833 {
834 struct si_context *sctx = (struct si_context*)ctx;
835
836 if (!size)
837 return;
838
839 /* Mark the buffer range of destination as valid (initialized),
840 * so that transfer_map knows it should wait for the GPU when mapping
841 * that range. */
842 util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
843 offset + size);
844
845 /* Fallback for unaligned clears. */
846 if (offset % 4 != 0 || size % 4 != 0) {
847 uint32_t *map = sctx->b.ws->buffer_map(r600_resource(dst)->cs_buf,
848 sctx->b.rings.gfx.cs,
849 PIPE_TRANSFER_WRITE);
850 size /= 4;
851 for (unsigned i = 0; i < size; i++)
852 *map++ = value;
853 return;
854 }
855
856 uint64_t va = r600_resource_va(&sctx->screen->b.b, dst) + offset;
857
858 /* Flush the caches where the resource is bound. */
859 /* XXX only flush the caches where the buffer is bound. */
860 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
861 R600_CONTEXT_INV_CONST_CACHE |
862 R600_CONTEXT_FLUSH_AND_INV_CB |
863 R600_CONTEXT_FLUSH_AND_INV_DB |
864 R600_CONTEXT_FLUSH_AND_INV_CB_META |
865 R600_CONTEXT_FLUSH_AND_INV_DB_META;
866 sctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
867
868 while (size) {
869 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
870 unsigned dma_flags = 0;
871
872 si_need_cs_space(sctx, 7 + (sctx->b.flags ? sctx->cache_flush.num_dw : 0),
873 FALSE);
874
875 /* This must be done after need_cs_space. */
876 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
877 (struct r600_resource*)dst, RADEON_USAGE_WRITE,
878 RADEON_PRIO_MIN);
879
880 /* Flush the caches for the first copy only.
881 * Also wait for the previous CP DMA operations. */
882 if (sctx->b.flags) {
883 si_emit_cache_flush(&sctx->b, NULL);
884 dma_flags |= SI_CP_DMA_RAW_WAIT; /* same as WAIT_UNTIL=CP_DMA_IDLE */
885 }
886
887 /* Do the synchronization after the last copy, so that all data is written to memory. */
888 if (size == byte_count)
889 dma_flags |= R600_CP_DMA_SYNC;
890
891 /* Emit the clear packet. */
892 si_emit_cp_dma_clear_buffer(sctx, va, byte_count, value, dma_flags);
893
894 size -= byte_count;
895 va += byte_count;
896 }
897
898 /* Flush the caches again in case the 3D engine has been prefetching
899 * the resource. */
900 /* XXX only flush the caches where the buffer is bound. */
901 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
902 R600_CONTEXT_INV_CONST_CACHE |
903 R600_CONTEXT_FLUSH_AND_INV_CB |
904 R600_CONTEXT_FLUSH_AND_INV_DB |
905 R600_CONTEXT_FLUSH_AND_INV_CB_META |
906 R600_CONTEXT_FLUSH_AND_INV_DB_META;
907 }
908
909 void si_copy_buffer(struct si_context *sctx,
910 struct pipe_resource *dst, struct pipe_resource *src,
911 uint64_t dst_offset, uint64_t src_offset, unsigned size)
912 {
913 if (!size)
914 return;
915
916 /* Mark the buffer range of destination as valid (initialized),
917 * so that transfer_map knows it should wait for the GPU when mapping
918 * that range. */
919 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
920 dst_offset + size);
921
922 dst_offset += r600_resource_va(&sctx->screen->b.b, dst);
923 src_offset += r600_resource_va(&sctx->screen->b.b, src);
924
925 /* Flush the caches where the resource is bound. */
926 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
927 R600_CONTEXT_INV_CONST_CACHE |
928 R600_CONTEXT_FLUSH_AND_INV_CB |
929 R600_CONTEXT_FLUSH_AND_INV_DB |
930 R600_CONTEXT_FLUSH_AND_INV_CB_META |
931 R600_CONTEXT_FLUSH_AND_INV_DB_META |
932 R600_CONTEXT_WAIT_3D_IDLE;
933
934 while (size) {
935 unsigned sync_flags = 0;
936 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
937
938 si_need_cs_space(sctx, 7 + (sctx->b.flags ? sctx->cache_flush.num_dw : 0), FALSE);
939
940 /* Flush the caches for the first copy only. Also wait for old CP DMA packets to complete. */
941 if (sctx->b.flags) {
942 si_emit_cache_flush(&sctx->b, NULL);
943 sync_flags |= SI_CP_DMA_RAW_WAIT;
944 }
945
946 /* Do the synchronization after the last copy, so that all data is written to memory. */
947 if (size == byte_count) {
948 sync_flags |= R600_CP_DMA_SYNC;
949 }
950
951 /* This must be done after r600_need_cs_space. */
952 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src,
953 RADEON_USAGE_READ, RADEON_PRIO_MIN);
954 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst,
955 RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
956
957 si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset, byte_count, sync_flags);
958
959 size -= byte_count;
960 src_offset += byte_count;
961 dst_offset += byte_count;
962 }
963
964 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
965 R600_CONTEXT_INV_CONST_CACHE |
966 R600_CONTEXT_FLUSH_AND_INV_CB |
967 R600_CONTEXT_FLUSH_AND_INV_DB |
968 R600_CONTEXT_FLUSH_AND_INV_CB_META |
969 R600_CONTEXT_FLUSH_AND_INV_DB_META;
970 }
971
972 /* INIT/DEINIT */
973
974 void si_init_all_descriptors(struct si_context *sctx)
975 {
976 int i;
977
978 for (i = 0; i < SI_NUM_SHADERS; i++) {
979 si_init_buffer_resources(sctx, &sctx->const_buffers[i],
980 NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
981 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO);
982 si_init_buffer_resources(sctx, &sctx->rw_buffers[i],
983 i == PIPE_SHADER_VERTEX ?
984 SI_RW_SO + 4 : SI_RW_SO,
985 i, SI_SGPR_RW_BUFFERS,
986 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
987
988 si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
989
990 sctx->atoms.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
991 sctx->atoms.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
992 sctx->atoms.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
993 }
994
995
996 /* Set pipe_context functions. */
997 sctx->b.b.set_constant_buffer = si_set_constant_buffer;
998 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
999 sctx->b.clear_buffer = si_clear_buffer;
1000 sctx->b.invalidate_buffer = si_invalidate_buffer;
1001 }
1002
1003 void si_release_all_descriptors(struct si_context *sctx)
1004 {
1005 int i;
1006
1007 for (i = 0; i < SI_NUM_SHADERS; i++) {
1008 si_release_buffer_resources(&sctx->const_buffers[i]);
1009 si_release_buffer_resources(&sctx->rw_buffers[i]);
1010 si_release_sampler_views(&sctx->samplers[i].views);
1011 }
1012 }
1013
1014 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1015 {
1016 int i;
1017
1018 for (i = 0; i < SI_NUM_SHADERS; i++) {
1019 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1020 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers[i]);
1021 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1022 }
1023 }