2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/hash_table.h"
64 #include "util/u_format.h"
65 #include "util/u_memory.h"
66 #include "util/u_upload_mgr.h"
69 /* NULL image and buffer descriptor for textures (alpha = 1) and images
72 * For images, all fields must be zero except for the swizzle, which
73 * supports arbitrary combinations of 0s and 1s. The texture type must be
74 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 * This is the only reason why the buffer descriptor must be in words [4:7].
80 static uint32_t null_texture_descriptor
[8] = {
84 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
85 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
86 /* the rest must contain zeros, which is also used by the buffer
90 static uint32_t null_image_descriptor
[8] = {
94 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
95 /* the rest must contain zeros, which is also used by the buffer
99 static void si_init_descriptor_list(uint32_t *desc_list
,
100 unsigned element_dw_size
,
101 unsigned num_elements
,
102 const uint32_t *null_descriptor
)
106 /* Initialize the array to NULL descriptors if the element size is 8. */
107 if (null_descriptor
) {
108 assert(element_dw_size
% 8 == 0);
109 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
110 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
114 static void si_init_descriptors(struct si_context
*sctx
,
115 struct si_descriptors
*desc
,
116 unsigned shader_userdata_index
,
117 unsigned element_dw_size
,
118 unsigned num_elements
,
119 unsigned first_ce_slot
,
120 unsigned num_ce_slots
,
123 assert(num_elements
<= sizeof(desc
->dirty_mask
)*8);
125 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
126 desc
->element_dw_size
= element_dw_size
;
127 desc
->num_elements
= num_elements
;
128 desc
->first_ce_slot
= sctx
->ce_ib
? first_ce_slot
: 0;
129 desc
->num_ce_slots
= sctx
->ce_ib
? num_ce_slots
: 0;
130 desc
->dirty_mask
= u_bit_consecutive64(0, num_elements
);
131 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
133 if (desc
->num_ce_slots
) {
134 desc
->uses_ce
= true;
135 desc
->ce_offset
= *ce_offset
;
137 *ce_offset
+= element_dw_size
* desc
->num_ce_slots
* 4;
141 static void si_release_descriptors(struct si_descriptors
*desc
)
143 r600_resource_reference(&desc
->buffer
, NULL
);
147 static bool si_ce_upload(struct si_context
*sctx
, unsigned ce_offset
, unsigned size
,
148 unsigned *out_offset
, struct r600_resource
**out_buf
)
152 u_suballocator_alloc(sctx
->ce_suballocator
, size
,
153 si_optimal_tcc_alignment(sctx
, size
),
155 (struct pipe_resource
**)out_buf
);
159 va
= (*out_buf
)->gpu_address
+ *out_offset
;
161 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_DUMP_CONST_RAM
, 3, 0));
162 radeon_emit(sctx
->ce_ib
, ce_offset
);
163 radeon_emit(sctx
->ce_ib
, size
/ 4);
164 radeon_emit(sctx
->ce_ib
, va
);
165 radeon_emit(sctx
->ce_ib
, va
>> 32);
167 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *out_buf
,
168 RADEON_USAGE_READWRITE
, RADEON_PRIO_DESCRIPTORS
);
170 sctx
->ce_need_synchronization
= true;
174 void si_ce_save_all_descriptors_at_ib_end(struct si_context
* sctx
)
176 bool success
= si_ce_upload(sctx
, 0, sctx
->total_ce_ram_allocated
,
177 &sctx
->ce_ram_saved_offset
,
178 &sctx
->ce_ram_saved_buffer
);
183 void si_ce_restore_all_descriptors_at_ib_start(struct si_context
*sctx
)
185 if (!sctx
->ce_ram_saved_buffer
)
188 struct radeon_winsys_cs
*ib
= sctx
->ce_preamble_ib
;
192 uint64_t va
= sctx
->ce_ram_saved_buffer
->gpu_address
+
193 sctx
->ce_ram_saved_offset
;
195 radeon_emit(ib
, PKT3(PKT3_LOAD_CONST_RAM
, 3, 0));
197 radeon_emit(ib
, va
>> 32);
198 radeon_emit(ib
, sctx
->total_ce_ram_allocated
/ 4);
201 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
202 sctx
->ce_ram_saved_buffer
,
203 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
206 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
)
208 radeon_emit(ib
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
209 radeon_emit(ib
, CONTEXT_CONTROL_LOAD_ENABLE(1) |
210 CONTEXT_CONTROL_LOAD_CE_RAM(1));
211 radeon_emit(ib
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
214 static bool si_upload_descriptors(struct si_context
*sctx
,
215 struct si_descriptors
*desc
,
216 struct r600_atom
* atom
)
218 unsigned slot_size
= desc
->element_dw_size
* 4;
219 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
220 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
222 /* Skip the upload if no shader is using the descriptors. dirty_mask
223 * will stay dirty and the descriptors will be uploaded when there is
224 * a shader using them.
230 const uint32_t *list
= desc
->list
+
231 desc
->first_ce_slot
* desc
->element_dw_size
;
232 uint64_t mask
= (desc
->dirty_mask
>> desc
->first_ce_slot
) &
233 u_bit_consecutive64(0, desc
->num_ce_slots
);
238 u_bit_scan_consecutive_range64(&mask
, &begin
, &count
);
240 begin
*= desc
->element_dw_size
;
241 count
*= desc
->element_dw_size
;
243 radeon_emit(sctx
->ce_ib
,
244 PKT3(PKT3_WRITE_CONST_RAM
, count
, 0));
245 radeon_emit(sctx
->ce_ib
, desc
->ce_offset
+ begin
* 4);
246 radeon_emit_array(sctx
->ce_ib
, list
+ begin
, count
);
249 if (!si_ce_upload(sctx
,
251 (first_slot_offset
- desc
->first_ce_slot
* slot_size
),
252 upload_size
, (unsigned*)&desc
->buffer_offset
,
258 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
259 si_optimal_tcc_alignment(sctx
, upload_size
),
260 (unsigned*)&desc
->buffer_offset
,
261 (struct pipe_resource
**)&desc
->buffer
,
264 return false; /* skip the draw call */
266 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
268 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
270 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
271 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
274 /* The shader pointer should point to slot 0. */
275 desc
->buffer_offset
-= first_slot_offset
;
277 desc
->dirty_mask
= 0;
280 si_mark_atom_dirty(sctx
, atom
);
286 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
291 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
292 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
298 si_sampler_and_image_descriptors_idx(unsigned shader
)
300 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
301 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
304 static struct si_descriptors
*
305 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
307 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
310 static void si_release_sampler_views(struct si_sampler_views
*views
)
314 for (i
= 0; i
< ARRAY_SIZE(views
->views
); i
++) {
315 pipe_sampler_view_reference(&views
->views
[i
], NULL
);
319 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
320 struct pipe_resource
*resource
,
321 enum radeon_bo_usage usage
,
322 bool is_stencil_sampler
,
325 struct r600_resource
*rres
;
326 struct r600_texture
*rtex
;
327 enum radeon_bo_priority priority
;
332 if (resource
->target
!= PIPE_BUFFER
) {
333 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
335 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
336 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
339 rres
= (struct r600_resource
*)resource
;
340 priority
= r600_get_sampler_view_priority(rres
);
342 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
343 rres
, usage
, priority
,
346 if (resource
->target
== PIPE_BUFFER
)
349 /* Now add separate DCC or HTILE. */
350 rtex
= (struct r600_texture
*)resource
;
351 if (rtex
->dcc_separate_buffer
) {
352 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
353 rtex
->dcc_separate_buffer
, usage
,
354 RADEON_PRIO_DCC
, check_mem
);
358 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
359 struct si_sampler_views
*views
)
361 unsigned mask
= views
->enabled_mask
;
363 /* Add buffers to the CS. */
365 int i
= u_bit_scan(&mask
);
366 struct si_sampler_view
*sview
= (struct si_sampler_view
*)views
->views
[i
];
368 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
370 sview
->is_stencil_sampler
, false);
374 /* Set buffer descriptor fields that can be changed by reallocations. */
375 static void si_set_buf_desc_address(struct r600_resource
*buf
,
376 uint64_t offset
, uint32_t *state
)
378 uint64_t va
= buf
->gpu_address
+ offset
;
381 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
382 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
385 /* Set texture descriptor fields that can be changed by reallocations.
388 * \param base_level_info information of the level of BASE_ADDRESS
389 * \param base_level the level of BASE_ADDRESS
390 * \param first_level pipe_sampler_view.u.tex.first_level
391 * \param block_width util_format_get_blockwidth()
392 * \param is_stencil select between separate Z & Stencil
393 * \param state descriptor to update
395 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
396 struct r600_texture
*tex
,
397 const struct legacy_surf_level
*base_level_info
,
398 unsigned base_level
, unsigned first_level
,
399 unsigned block_width
, bool is_stencil
,
402 uint64_t va
, meta_va
= 0;
404 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
405 tex
= tex
->flushed_depth_texture
;
409 va
= tex
->resource
.gpu_address
;
411 if (sscreen
->b
.chip_class
>= GFX9
) {
412 /* Only stencil_offset needs to be added here. */
414 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
416 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
418 va
+= base_level_info
->offset
;
422 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
423 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
425 if (sscreen
->b
.chip_class
>= VI
) {
426 state
[6] &= C_008F28_COMPRESSION_EN
;
429 if (vi_dcc_enabled(tex
, first_level
)) {
430 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
433 if (sscreen
->b
.chip_class
<= VI
)
434 meta_va
+= base_level_info
->dcc_offset
;
435 } else if (tex
->tc_compatible_htile
&& first_level
== 0) {
436 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
440 state
[6] |= S_008F28_COMPRESSION_EN(1);
441 state
[7] = meta_va
>> 8;
445 if (sscreen
->b
.chip_class
>= GFX9
) {
446 state
[3] &= C_008F1C_SW_MODE
;
447 state
[4] &= C_008F20_PITCH_GFX9
;
450 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
451 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
453 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
454 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
457 state
[5] &= C_008F24_META_DATA_ADDRESS
&
458 C_008F24_META_PIPE_ALIGNED
&
459 C_008F24_META_RB_ALIGNED
;
461 struct gfx9_surf_meta_flags meta
;
464 meta
= tex
->surface
.u
.gfx9
.dcc
;
466 meta
= tex
->surface
.u
.gfx9
.htile
;
468 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
469 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
470 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
474 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
475 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
477 state
[3] &= C_008F1C_TILING_INDEX
;
478 state
[3] |= S_008F1C_TILING_INDEX(index
);
479 state
[4] &= C_008F20_PITCH_GFX6
;
480 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
484 static void si_set_sampler_view_desc(struct si_context
*sctx
,
485 struct si_sampler_view
*sview
,
486 struct si_sampler_state
*sstate
,
489 struct pipe_sampler_view
*view
= &sview
->base
;
490 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
491 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
493 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
494 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
495 if (!r600_texture_disable_dcc(&sctx
->b
, rtex
))
496 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
498 sview
->dcc_incompatible
= false;
501 assert(rtex
); /* views with texture == NULL aren't supported */
502 memcpy(desc
, sview
->state
, 8*4);
505 si_set_buf_desc_address(&rtex
->resource
,
506 sview
->base
.u
.buf
.offset
,
509 bool is_separate_stencil
= rtex
->db_compatible
&&
510 sview
->is_stencil_sampler
;
512 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
513 sview
->base_level_info
,
515 sview
->base
.u
.tex
.first_level
,
521 if (!is_buffer
&& rtex
->fmask
.size
) {
522 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
524 /* Disable FMASK and bind sampler state in [12:15]. */
525 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
528 memcpy(desc
+ 12, sstate
->val
, 4*4);
532 static void si_set_sampler_view(struct si_context
*sctx
,
534 unsigned slot
, struct pipe_sampler_view
*view
,
535 bool disallow_early_out
)
537 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
538 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
539 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
540 unsigned desc_slot
= si_get_sampler_slot(slot
);
541 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
543 if (views
->views
[slot
] == view
&& !disallow_early_out
)
547 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
549 si_set_sampler_view_desc(sctx
, rview
,
550 views
->sampler_states
[slot
], desc
);
552 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
)
553 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
555 pipe_sampler_view_reference(&views
->views
[slot
], view
);
556 views
->enabled_mask
|= 1u << slot
;
558 /* Since this can flush, it must be done after enabled_mask is
560 si_sampler_view_add_buffer(sctx
, view
->texture
,
562 rview
->is_stencil_sampler
, true);
564 pipe_sampler_view_reference(&views
->views
[slot
], NULL
);
565 memcpy(desc
, null_texture_descriptor
, 8*4);
566 /* Only clear the lower dwords of FMASK. */
567 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
568 /* Re-set the sampler state if we are transitioning from FMASK. */
569 if (views
->sampler_states
[slot
])
571 views
->sampler_states
[slot
]->val
, 4*4);
573 views
->enabled_mask
&= ~(1u << slot
);
576 descs
->dirty_mask
|= 1ull << desc_slot
;
577 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
580 static bool color_needs_decompression(struct r600_texture
*rtex
)
582 return rtex
->fmask
.size
||
583 (rtex
->dirty_level_mask
&&
584 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
587 static bool depth_needs_decompression(struct r600_texture
*rtex
)
589 /* If the depth/stencil texture is TC-compatible, no decompression
590 * will be done. The decompression function will only flush DB caches
591 * to make it coherent with shaders. That's necessary because the driver
592 * doesn't flush DB caches in any other case.
594 return rtex
->db_compatible
;
597 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
600 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
601 unsigned shader_bit
= 1 << shader
;
603 if (samplers
->needs_depth_decompress_mask
||
604 samplers
->needs_color_decompress_mask
||
605 sctx
->images
[shader
].needs_color_decompress_mask
)
606 sctx
->shader_needs_decompress_mask
|= shader_bit
;
608 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
611 static void si_set_sampler_views(struct pipe_context
*ctx
,
612 enum pipe_shader_type shader
, unsigned start
,
614 struct pipe_sampler_view
**views
)
616 struct si_context
*sctx
= (struct si_context
*)ctx
;
617 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
620 if (!count
|| shader
>= SI_NUM_SHADERS
)
623 for (i
= 0; i
< count
; i
++) {
624 unsigned slot
= start
+ i
;
626 if (!views
|| !views
[i
]) {
627 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
628 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
629 si_set_sampler_view(sctx
, shader
, slot
, NULL
, false);
633 si_set_sampler_view(sctx
, shader
, slot
, views
[i
], false);
635 if (views
[i
]->texture
&& views
[i
]->texture
->target
!= PIPE_BUFFER
) {
636 struct r600_texture
*rtex
=
637 (struct r600_texture
*)views
[i
]->texture
;
639 if (depth_needs_decompression(rtex
)) {
640 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
642 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
644 if (color_needs_decompression(rtex
)) {
645 samplers
->needs_color_decompress_mask
|= 1u << slot
;
647 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
650 if (rtex
->dcc_offset
&&
651 p_atomic_read(&rtex
->framebuffers_bound
))
652 sctx
->need_check_render_feedback
= true;
654 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
655 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
659 si_update_shader_needs_decompress_mask(sctx
, shader
);
663 si_samplers_update_needs_color_decompress_mask(struct si_textures_info
*samplers
)
665 unsigned mask
= samplers
->views
.enabled_mask
;
668 int i
= u_bit_scan(&mask
);
669 struct pipe_resource
*res
= samplers
->views
.views
[i
]->texture
;
671 if (res
&& res
->target
!= PIPE_BUFFER
) {
672 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
674 if (color_needs_decompression(rtex
)) {
675 samplers
->needs_color_decompress_mask
|= 1u << i
;
677 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
686 si_release_image_views(struct si_images_info
*images
)
690 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
691 struct pipe_image_view
*view
= &images
->views
[i
];
693 pipe_resource_reference(&view
->resource
, NULL
);
698 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images_info
*images
)
700 uint mask
= images
->enabled_mask
;
702 /* Add buffers to the CS. */
704 int i
= u_bit_scan(&mask
);
705 struct pipe_image_view
*view
= &images
->views
[i
];
707 assert(view
->resource
);
709 si_sampler_view_add_buffer(sctx
, view
->resource
,
710 RADEON_USAGE_READWRITE
, false, false);
715 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
717 struct si_images_info
*images
= &ctx
->images
[shader
];
719 if (images
->enabled_mask
& (1u << slot
)) {
720 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
721 unsigned desc_slot
= si_get_image_slot(slot
);
723 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
724 images
->needs_color_decompress_mask
&= ~(1 << slot
);
726 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
727 images
->enabled_mask
&= ~(1u << slot
);
728 /* two 8-byte images share one 16-byte slot */
729 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
730 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
735 si_mark_image_range_valid(const struct pipe_image_view
*view
)
737 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
739 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
741 util_range_add(&res
->valid_buffer_range
,
743 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
746 static void si_set_shader_image_desc(struct si_context
*ctx
,
747 const struct pipe_image_view
*view
,
748 bool skip_decompress
,
751 struct si_screen
*screen
= ctx
->screen
;
752 struct r600_resource
*res
;
754 res
= (struct r600_resource
*)view
->resource
;
756 if (res
->b
.b
.target
== PIPE_BUFFER
) {
757 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
758 si_mark_image_range_valid(view
);
760 si_make_buffer_descriptor(screen
, res
,
763 view
->u
.buf
.size
, desc
);
764 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
766 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
767 struct r600_texture
*tex
= (struct r600_texture
*)res
;
768 unsigned level
= view
->u
.tex
.level
;
769 unsigned width
, height
, depth
, hw_level
;
770 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
772 assert(!tex
->is_depth
);
773 assert(tex
->fmask
.size
== 0);
775 if (uses_dcc
&& !skip_decompress
&&
776 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
777 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
778 /* If DCC can't be disabled, at least decompress it.
779 * The decompression is relatively cheap if the surface
780 * has been decompressed already.
782 if (!r600_texture_disable_dcc(&ctx
->b
, tex
))
783 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
786 if (ctx
->b
.chip_class
>= GFX9
) {
787 /* Always set the base address. The swizzle modes don't
788 * allow setting mipmap level offsets as the base.
790 width
= res
->b
.b
.width0
;
791 height
= res
->b
.b
.height0
;
792 depth
= res
->b
.b
.depth0
;
795 /* Always force the base level to the selected level.
797 * This is required for 3D textures, where otherwise
798 * selecting a single slice for non-layered bindings
799 * fails. It doesn't hurt the other targets.
801 width
= u_minify(res
->b
.b
.width0
, level
);
802 height
= u_minify(res
->b
.b
.height0
, level
);
803 depth
= u_minify(res
->b
.b
.depth0
, level
);
807 si_make_texture_descriptor(screen
, tex
,
808 false, res
->b
.b
.target
,
809 view
->format
, swizzle
,
811 view
->u
.tex
.first_layer
,
812 view
->u
.tex
.last_layer
,
813 width
, height
, depth
,
815 si_set_mutable_tex_desc_fields(screen
, tex
,
816 &tex
->surface
.u
.legacy
.level
[level
],
818 util_format_get_blockwidth(view
->format
),
823 static void si_set_shader_image(struct si_context
*ctx
,
825 unsigned slot
, const struct pipe_image_view
*view
,
826 bool skip_decompress
)
828 struct si_images_info
*images
= &ctx
->images
[shader
];
829 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
830 struct r600_resource
*res
;
831 unsigned desc_slot
= si_get_image_slot(slot
);
832 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
834 if (!view
|| !view
->resource
) {
835 si_disable_shader_image(ctx
, shader
, slot
);
839 res
= (struct r600_resource
*)view
->resource
;
841 if (&images
->views
[slot
] != view
)
842 util_copy_image_view(&images
->views
[slot
], view
);
844 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
846 if (res
->b
.b
.target
== PIPE_BUFFER
) {
847 images
->needs_color_decompress_mask
&= ~(1 << slot
);
848 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
850 struct r600_texture
*tex
= (struct r600_texture
*)res
;
851 unsigned level
= view
->u
.tex
.level
;
853 if (color_needs_decompression(tex
)) {
854 images
->needs_color_decompress_mask
|= 1 << slot
;
856 images
->needs_color_decompress_mask
&= ~(1 << slot
);
859 if (vi_dcc_enabled(tex
, level
) &&
860 p_atomic_read(&tex
->framebuffers_bound
))
861 ctx
->need_check_render_feedback
= true;
864 images
->enabled_mask
|= 1u << slot
;
865 /* two 8-byte images share one 16-byte slot */
866 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
867 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
869 /* Since this can flush, it must be done after enabled_mask is updated. */
870 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
871 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
872 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
877 si_set_shader_images(struct pipe_context
*pipe
,
878 enum pipe_shader_type shader
,
879 unsigned start_slot
, unsigned count
,
880 const struct pipe_image_view
*views
)
882 struct si_context
*ctx
= (struct si_context
*)pipe
;
885 assert(shader
< SI_NUM_SHADERS
);
890 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
893 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
894 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
896 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
897 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
900 si_update_shader_needs_decompress_mask(ctx
, shader
);
904 si_images_update_needs_color_decompress_mask(struct si_images_info
*images
)
906 unsigned mask
= images
->enabled_mask
;
909 int i
= u_bit_scan(&mask
);
910 struct pipe_resource
*res
= images
->views
[i
].resource
;
912 if (res
&& res
->target
!= PIPE_BUFFER
) {
913 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
915 if (color_needs_decompression(rtex
)) {
916 images
->needs_color_decompress_mask
|= 1 << i
;
918 images
->needs_color_decompress_mask
&= ~(1 << i
);
926 static void si_bind_sampler_states(struct pipe_context
*ctx
,
927 enum pipe_shader_type shader
,
928 unsigned start
, unsigned count
, void **states
)
930 struct si_context
*sctx
= (struct si_context
*)ctx
;
931 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
932 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
933 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
936 if (!count
|| shader
>= SI_NUM_SHADERS
)
939 for (i
= 0; i
< count
; i
++) {
940 unsigned slot
= start
+ i
;
941 unsigned desc_slot
= si_get_sampler_slot(slot
);
944 sstates
[i
] == samplers
->views
.sampler_states
[slot
])
948 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
950 samplers
->views
.sampler_states
[slot
] = sstates
[i
];
952 /* If FMASK is bound, don't overwrite it.
953 * The sampler state will be set after FMASK is unbound.
955 if (samplers
->views
.views
[slot
] &&
956 samplers
->views
.views
[slot
]->texture
&&
957 samplers
->views
.views
[slot
]->texture
->target
!= PIPE_BUFFER
&&
958 ((struct r600_texture
*)samplers
->views
.views
[slot
]->texture
)->fmask
.size
)
961 memcpy(desc
->list
+ desc_slot
* 16 + 12, sstates
[i
]->val
, 4*4);
962 desc
->dirty_mask
|= 1ull << desc_slot
;
963 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
967 /* BUFFER RESOURCES */
969 static void si_init_buffer_resources(struct si_context
*sctx
,
970 struct si_buffer_resources
*buffers
,
971 struct si_descriptors
*descs
,
972 unsigned num_buffers
,
973 unsigned first_ce_slot
,
974 unsigned num_ce_slots
,
975 unsigned shader_userdata_index
,
976 enum radeon_bo_usage shader_usage
,
977 enum radeon_bo_usage shader_usage_constbuf
,
978 enum radeon_bo_priority priority
,
979 enum radeon_bo_priority priority_constbuf
,
982 buffers
->shader_usage
= shader_usage
;
983 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
984 buffers
->priority
= priority
;
985 buffers
->priority_constbuf
= priority_constbuf
;
986 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
988 si_init_descriptors(sctx
, descs
, shader_userdata_index
, 4, num_buffers
,
989 first_ce_slot
, num_ce_slots
, ce_offset
);
992 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
993 struct si_descriptors
*descs
)
997 for (i
= 0; i
< descs
->num_elements
; i
++) {
998 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1001 FREE(buffers
->buffers
);
1004 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1005 struct si_buffer_resources
*buffers
)
1007 unsigned mask
= buffers
->enabled_mask
;
1009 /* Add buffers to the CS. */
1011 int i
= u_bit_scan(&mask
);
1013 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1014 r600_resource(buffers
->buffers
[i
]),
1015 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
1016 buffers
->shader_usage_constbuf
,
1017 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1018 buffers
->priority_constbuf
);
1022 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1023 struct si_descriptors
*descs
,
1024 unsigned idx
, struct pipe_resource
**buf
,
1025 unsigned *offset
, unsigned *size
)
1027 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1029 struct r600_resource
*res
= r600_resource(*buf
);
1030 const uint32_t *desc
= descs
->list
+ idx
* 4;
1035 assert(G_008F04_STRIDE(desc
[1]) == 0);
1036 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
1038 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1039 *offset
= va
- res
->gpu_address
;
1043 /* VERTEX BUFFERS */
1045 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1047 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1048 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1051 for (i
= 0; i
< count
; i
++) {
1052 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1054 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1056 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1059 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1060 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1061 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1066 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1067 desc
->buffer
, RADEON_USAGE_READ
,
1068 RADEON_PRIO_DESCRIPTORS
);
1071 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1073 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1074 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1076 unsigned desc_list_byte_size
;
1077 unsigned first_vb_use_mask
;
1081 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1084 count
= velems
->count
;
1089 desc_list_byte_size
= velems
->desc_list_byte_size
;
1090 first_vb_use_mask
= velems
->first_vb_use_mask
;
1092 /* Vertex buffer descriptors are the only ones which are uploaded
1093 * directly through a staging buffer and don't go through
1094 * the fine-grained upload path.
1096 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1097 desc_list_byte_size
,
1098 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1099 (unsigned*)&desc
->buffer_offset
,
1100 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1105 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1106 desc
->buffer
, RADEON_USAGE_READ
,
1107 RADEON_PRIO_DESCRIPTORS
);
1109 assert(count
<= SI_MAX_ATTRIBS
);
1111 for (i
= 0; i
< count
; i
++) {
1112 struct pipe_vertex_buffer
*vb
;
1113 struct r600_resource
*rbuffer
;
1115 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1116 uint32_t *desc
= &ptr
[i
*4];
1118 vb
= &sctx
->vertex_buffer
[vbo_index
];
1119 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1121 memset(desc
, 0, 16);
1125 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1126 va
= rbuffer
->gpu_address
+ offset
;
1128 /* Fill in T# buffer resource description */
1130 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1131 S_008F04_STRIDE(vb
->stride
);
1133 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1134 /* Round up by rounding down and adding 1 */
1135 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1136 velems
->format_size
[i
]) /
1139 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1142 desc
[3] = velems
->rsrc_word3
[i
];
1144 if (first_vb_use_mask
& (1 << i
)) {
1145 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1146 (struct r600_resource
*)vb
->buffer
.resource
,
1147 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1151 /* Don't flush the const cache. It would have a very negative effect
1152 * on performance (confirmed by testing). New descriptors are always
1153 * uploaded to a fresh new buffer, so I don't think flushing the const
1154 * cache is needed. */
1155 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1156 if (sctx
->b
.chip_class
>= CIK
)
1157 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
1158 sctx
->vertex_buffers_dirty
= false;
1159 sctx
->vertex_buffer_pointer_dirty
= true;
1164 /* CONSTANT BUFFERS */
1167 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1169 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1170 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1173 static struct si_descriptors
*
1174 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1176 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1179 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1180 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1184 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1185 si_optimal_tcc_alignment(sctx
, size
),
1187 (struct pipe_resource
**)rbuffer
, &tmp
);
1189 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1192 static void si_set_constant_buffer(struct si_context
*sctx
,
1193 struct si_buffer_resources
*buffers
,
1194 unsigned descriptors_idx
,
1195 uint slot
, const struct pipe_constant_buffer
*input
)
1197 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1198 assert(slot
< descs
->num_elements
);
1199 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1201 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1202 * with a NULL buffer). We need to use a dummy buffer instead. */
1203 if (sctx
->b
.chip_class
== CIK
&&
1204 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1205 input
= &sctx
->null_const_buf
;
1207 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1208 struct pipe_resource
*buffer
= NULL
;
1211 /* Upload the user buffer if needed. */
1212 if (input
->user_buffer
) {
1213 unsigned buffer_offset
;
1215 si_upload_const_buffer(sctx
,
1216 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1217 input
->buffer_size
, &buffer_offset
);
1219 /* Just unbind on failure. */
1220 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1223 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1225 pipe_resource_reference(&buffer
, input
->buffer
);
1226 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1227 /* Only track usage for non-user buffers. */
1228 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1231 /* Set the descriptor. */
1232 uint32_t *desc
= descs
->list
+ slot
*4;
1234 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1236 desc
[2] = input
->buffer_size
;
1237 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1238 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1239 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1240 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1241 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1242 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1244 buffers
->buffers
[slot
] = buffer
;
1245 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1246 (struct r600_resource
*)buffer
,
1247 buffers
->shader_usage_constbuf
,
1248 buffers
->priority_constbuf
, true);
1249 buffers
->enabled_mask
|= 1u << slot
;
1251 /* Clear the descriptor. */
1252 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1253 buffers
->enabled_mask
&= ~(1u << slot
);
1256 descs
->dirty_mask
|= 1u << slot
;
1257 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1260 void si_set_rw_buffer(struct si_context
*sctx
,
1261 uint slot
, const struct pipe_constant_buffer
*input
)
1263 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1264 SI_DESCS_RW_BUFFERS
, slot
, input
);
1267 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1268 enum pipe_shader_type shader
, uint slot
,
1269 const struct pipe_constant_buffer
*input
)
1271 struct si_context
*sctx
= (struct si_context
*)ctx
;
1273 if (shader
>= SI_NUM_SHADERS
)
1276 slot
= si_get_constbuf_slot(slot
);
1277 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1278 si_const_and_shader_buffer_descriptors_idx(shader
),
1282 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1283 uint slot
, struct pipe_constant_buffer
*cbuf
)
1285 cbuf
->user_buffer
= NULL
;
1286 si_get_buffer_from_descriptors(
1287 &sctx
->const_and_shader_buffers
[shader
],
1288 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1289 si_get_constbuf_slot(slot
),
1290 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1293 /* SHADER BUFFERS */
1295 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1296 enum pipe_shader_type shader
,
1297 unsigned start_slot
, unsigned count
,
1298 const struct pipe_shader_buffer
*sbuffers
)
1300 struct si_context
*sctx
= (struct si_context
*)ctx
;
1301 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1302 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1305 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1307 for (i
= 0; i
< count
; ++i
) {
1308 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1309 struct r600_resource
*buf
;
1310 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1311 uint32_t *desc
= descs
->list
+ slot
* 4;
1314 if (!sbuffer
|| !sbuffer
->buffer
) {
1315 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1316 memset(desc
, 0, sizeof(uint32_t) * 4);
1317 buffers
->enabled_mask
&= ~(1u << slot
);
1318 descs
->dirty_mask
|= 1u << slot
;
1319 sctx
->descriptors_dirty
|=
1320 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1324 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1325 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1328 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1330 desc
[2] = sbuffer
->buffer_size
;
1331 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1332 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1333 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1334 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1335 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1336 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1338 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1339 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1340 buffers
->shader_usage
,
1341 buffers
->priority
, true);
1342 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1344 buffers
->enabled_mask
|= 1u << slot
;
1345 descs
->dirty_mask
|= 1u << slot
;
1346 sctx
->descriptors_dirty
|=
1347 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1349 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1350 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1354 void si_get_shader_buffers(struct si_context
*sctx
,
1355 enum pipe_shader_type shader
,
1356 uint start_slot
, uint count
,
1357 struct pipe_shader_buffer
*sbuf
)
1359 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1360 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1362 for (unsigned i
= 0; i
< count
; ++i
) {
1363 si_get_buffer_from_descriptors(
1365 si_get_shaderbuf_slot(start_slot
+ i
),
1366 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1367 &sbuf
[i
].buffer_size
);
1373 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1374 struct pipe_resource
*buffer
,
1375 unsigned stride
, unsigned num_records
,
1376 bool add_tid
, bool swizzle
,
1377 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1379 struct si_context
*sctx
= (struct si_context
*)ctx
;
1380 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1381 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1383 /* The stride field in the resource descriptor has 14 bits */
1384 assert(stride
< (1 << 14));
1386 assert(slot
< descs
->num_elements
);
1387 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1392 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1394 switch (element_size
) {
1396 assert(!"Unsupported ring buffer element size");
1412 switch (index_stride
) {
1414 assert(!"Unsupported ring buffer index stride");
1430 if (sctx
->b
.chip_class
>= VI
&& stride
)
1431 num_records
*= stride
;
1433 /* Set the descriptor. */
1434 uint32_t *desc
= descs
->list
+ slot
*4;
1436 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1437 S_008F04_STRIDE(stride
) |
1438 S_008F04_SWIZZLE_ENABLE(swizzle
);
1439 desc
[2] = num_records
;
1440 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1441 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1442 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1443 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1444 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1445 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1446 S_008F0C_INDEX_STRIDE(index_stride
) |
1447 S_008F0C_ADD_TID_ENABLE(add_tid
);
1449 if (sctx
->b
.chip_class
>= GFX9
)
1450 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1452 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1454 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1455 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1456 (struct r600_resource
*)buffer
,
1457 buffers
->shader_usage
, buffers
->priority
);
1458 buffers
->enabled_mask
|= 1u << slot
;
1460 /* Clear the descriptor. */
1461 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1462 buffers
->enabled_mask
&= ~(1u << slot
);
1465 descs
->dirty_mask
|= 1u << slot
;
1466 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1469 /* STREAMOUT BUFFERS */
1471 static void si_set_streamout_targets(struct pipe_context
*ctx
,
1472 unsigned num_targets
,
1473 struct pipe_stream_output_target
**targets
,
1474 const unsigned *offsets
)
1476 struct si_context
*sctx
= (struct si_context
*)ctx
;
1477 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1478 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1479 unsigned old_num_targets
= sctx
->b
.streamout
.num_targets
;
1482 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1483 if (sctx
->b
.streamout
.num_targets
&& sctx
->b
.streamout
.begin_emitted
) {
1484 /* Since streamout uses vector writes which go through TC L2
1485 * and most other clients can use TC L2 as well, we don't need
1488 * The only cases which requires flushing it is VGT DMA index
1489 * fetching (on <= CIK) and indirect draw data, which are rare
1490 * cases. Thus, flag the TC L2 dirtiness in the resource and
1491 * handle it at draw call time.
1493 for (i
= 0; i
< sctx
->b
.streamout
.num_targets
; i
++)
1494 if (sctx
->b
.streamout
.targets
[i
])
1495 r600_resource(sctx
->b
.streamout
.targets
[i
]->b
.buffer
)->TC_L2_dirty
= true;
1497 /* Invalidate the scalar cache in case a streamout buffer is
1498 * going to be used as a constant buffer.
1500 * Invalidate TC L1, because streamout bypasses it (done by
1501 * setting GLC=1 in the store instruction), but it can contain
1502 * outdated data of streamout buffers.
1504 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1505 * used as an input immediately.
1507 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
1508 SI_CONTEXT_INV_VMEM_L1
|
1509 SI_CONTEXT_VS_PARTIAL_FLUSH
;
1512 /* All readers of the streamout targets need to be finished before we can
1513 * start writing to the targets.
1516 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1517 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1519 /* Streamout buffers must be bound in 2 places:
1520 * 1) in VGT by setting the VGT_STRMOUT registers
1521 * 2) as shader resources
1524 /* Set the VGT regs. */
1525 r600_set_streamout_targets(ctx
, num_targets
, targets
, offsets
);
1527 /* Set the shader resources.*/
1528 for (i
= 0; i
< num_targets
; i
++) {
1529 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1532 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
1533 uint64_t va
= r600_resource(buffer
)->gpu_address
;
1535 /* Set the descriptor.
1537 * On VI, the format must be non-INVALID, otherwise
1538 * the buffer will be considered not bound and store
1539 * instructions will be no-ops.
1541 uint32_t *desc
= descs
->list
+ bufidx
*4;
1543 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1544 desc
[2] = 0xffffffff;
1545 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1546 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1547 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1548 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1549 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1551 /* Set the resource. */
1552 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1554 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1555 (struct r600_resource
*)buffer
,
1556 buffers
->shader_usage
,
1557 RADEON_PRIO_SHADER_RW_BUFFER
,
1559 r600_resource(buffer
)->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
1561 buffers
->enabled_mask
|= 1u << bufidx
;
1563 /* Clear the descriptor and unset the resource. */
1564 memset(descs
->list
+ bufidx
*4, 0,
1565 sizeof(uint32_t) * 4);
1566 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1568 buffers
->enabled_mask
&= ~(1u << bufidx
);
1570 descs
->dirty_mask
|= 1u << bufidx
;
1572 for (; i
< old_num_targets
; i
++) {
1573 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1574 /* Clear the descriptor and unset the resource. */
1575 memset(descs
->list
+ bufidx
*4, 0, sizeof(uint32_t) * 4);
1576 pipe_resource_reference(&buffers
->buffers
[bufidx
], NULL
);
1577 buffers
->enabled_mask
&= ~(1u << bufidx
);
1578 descs
->dirty_mask
|= 1u << bufidx
;
1581 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1584 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1585 uint32_t *desc
, uint64_t old_buf_va
,
1586 struct pipe_resource
*new_buf
)
1588 /* Retrieve the buffer offset from the descriptor. */
1589 uint64_t old_desc_va
=
1590 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
1592 assert(old_buf_va
<= old_desc_va
);
1593 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1595 /* Update the descriptor. */
1596 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1600 /* INTERNAL CONST BUFFERS */
1602 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1603 const struct pipe_poly_stipple
*state
)
1605 struct si_context
*sctx
= (struct si_context
*)ctx
;
1606 struct pipe_constant_buffer cb
= {};
1607 unsigned stipple
[32];
1610 for (i
= 0; i
< 32; i
++)
1611 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1613 cb
.user_buffer
= stipple
;
1614 cb
.buffer_size
= sizeof(stipple
);
1616 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1619 /* TEXTURE METADATA ENABLE/DISABLE */
1622 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1624 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1625 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1627 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1628 struct si_texture_handle
*, tex_handle
) {
1629 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1630 struct r600_texture
*rtex
;
1632 if (!res
|| res
->target
== PIPE_BUFFER
)
1635 rtex
= (struct r600_texture
*)res
;
1636 if (!color_needs_decompression(rtex
))
1639 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1640 struct si_texture_handle
*, *tex_handle
);
1643 util_dynarray_foreach(&sctx
->resident_img_handles
,
1644 struct si_image_handle
*, img_handle
) {
1645 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1646 struct pipe_resource
*res
= view
->resource
;
1647 struct r600_texture
*rtex
;
1649 if (!res
|| res
->target
== PIPE_BUFFER
)
1652 rtex
= (struct r600_texture
*)res
;
1653 if (!color_needs_decompression(rtex
))
1656 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1657 struct si_image_handle
*, *img_handle
);
1661 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1662 * while the texture is bound, possibly by a different context. In that case,
1663 * call this function to update needs_*_decompress_masks.
1665 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1667 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1668 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1669 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1670 si_update_shader_needs_decompress_mask(sctx
, i
);
1673 si_resident_handles_update_needs_color_decompress(sctx
);
1676 /* BUFFER DISCARD/INVALIDATION */
1678 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1679 static void si_reset_buffer_resources(struct si_context
*sctx
,
1680 struct si_buffer_resources
*buffers
,
1681 unsigned descriptors_idx
,
1683 struct pipe_resource
*buf
,
1685 enum radeon_bo_usage usage
,
1686 enum radeon_bo_priority priority
)
1688 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1689 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1692 unsigned i
= u_bit_scan(&mask
);
1693 if (buffers
->buffers
[i
] == buf
) {
1694 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1697 descs
->dirty_mask
|= 1u << i
;
1698 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1700 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1701 (struct r600_resource
*)buf
,
1702 usage
, priority
, true);
1707 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1710 struct si_context
*sctx
= (struct si_context
*)ctx
;
1711 struct r600_resource
*rbuffer
= r600_resource(buf
);
1713 unsigned num_elems
= sctx
->vertex_elements
?
1714 sctx
->vertex_elements
->count
: 0;
1716 /* We changed the buffer, now we need to bind it where the old one
1717 * was bound. This consists of 2 things:
1718 * 1) Updating the resource descriptor and dirtying it.
1719 * 2) Adding a relocation to the CS, so that it's usable.
1722 /* Vertex buffers. */
1723 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1724 for (i
= 0; i
< num_elems
; i
++) {
1725 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1727 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1729 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1732 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1733 sctx
->vertex_buffers_dirty
= true;
1739 /* Streamout buffers. (other internal buffers can't be invalidated) */
1740 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1741 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1742 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1743 struct si_descriptors
*descs
=
1744 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1746 if (buffers
->buffers
[i
] != buf
)
1749 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1751 descs
->dirty_mask
|= 1u << i
;
1752 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1754 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1755 rbuffer
, buffers
->shader_usage
,
1756 RADEON_PRIO_SHADER_RW_BUFFER
,
1759 /* Update the streamout state. */
1760 if (sctx
->b
.streamout
.begin_emitted
)
1761 r600_emit_streamout_end(&sctx
->b
);
1762 sctx
->b
.streamout
.append_bitmask
=
1763 sctx
->b
.streamout
.enabled_mask
;
1764 r600_streamout_buffers_dirty(&sctx
->b
);
1768 /* Constant and shader buffers. */
1769 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1770 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1771 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1772 si_const_and_shader_buffer_descriptors_idx(shader
),
1773 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1775 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1776 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1779 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1780 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1781 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1782 si_const_and_shader_buffer_descriptors_idx(shader
),
1783 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1785 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1786 sctx
->const_and_shader_buffers
[shader
].priority
);
1789 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1790 /* Texture buffers - update bindings. */
1791 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1792 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
1793 struct si_descriptors
*descs
=
1794 si_sampler_and_image_descriptors(sctx
, shader
);
1795 unsigned mask
= views
->enabled_mask
;
1798 unsigned i
= u_bit_scan(&mask
);
1799 if (views
->views
[i
]->texture
== buf
) {
1800 unsigned desc_slot
= si_get_sampler_slot(i
);
1802 si_desc_reset_buffer_offset(ctx
,
1806 descs
->dirty_mask
|= 1ull << desc_slot
;
1807 sctx
->descriptors_dirty
|=
1808 1u << si_sampler_and_image_descriptors_idx(shader
);
1810 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1811 rbuffer
, RADEON_USAGE_READ
,
1812 RADEON_PRIO_SAMPLER_BUFFER
,
1820 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1821 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1822 struct si_images_info
*images
= &sctx
->images
[shader
];
1823 struct si_descriptors
*descs
=
1824 si_sampler_and_image_descriptors(sctx
, shader
);
1825 unsigned mask
= images
->enabled_mask
;
1828 unsigned i
= u_bit_scan(&mask
);
1830 if (images
->views
[i
].resource
== buf
) {
1831 unsigned desc_slot
= si_get_image_slot(i
);
1833 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1834 si_mark_image_range_valid(&images
->views
[i
]);
1836 si_desc_reset_buffer_offset(
1837 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1839 /* two 8-byte images share one 16-byte slot */
1840 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
1841 sctx
->descriptors_dirty
|=
1842 1u << si_sampler_and_image_descriptors_idx(shader
);
1844 radeon_add_to_buffer_list_check_mem(
1845 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1846 RADEON_USAGE_READWRITE
,
1847 RADEON_PRIO_SAMPLER_BUFFER
, true);
1853 /* Bindless texture handles */
1854 if (rbuffer
->texture_handle_allocated
) {
1855 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1856 struct si_texture_handle
*, tex_handle
) {
1857 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1858 struct si_bindless_descriptor
*desc
= (*tex_handle
)->desc
;
1860 if (view
->texture
== buf
) {
1861 si_set_buf_desc_address(rbuffer
,
1863 &desc
->desc_list
[4]);
1865 sctx
->bindless_descriptors_dirty
= true;
1867 radeon_add_to_buffer_list_check_mem(
1868 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1870 RADEON_PRIO_SAMPLER_BUFFER
, true);
1875 /* Bindless image handles */
1876 if (rbuffer
->image_handle_allocated
) {
1877 util_dynarray_foreach(&sctx
->resident_img_handles
,
1878 struct si_image_handle
*, img_handle
) {
1879 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1880 struct si_bindless_descriptor
*desc
= (*img_handle
)->desc
;
1882 if (view
->resource
== buf
) {
1883 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1884 si_mark_image_range_valid(view
);
1886 si_set_buf_desc_address(rbuffer
,
1888 &desc
->desc_list
[4]);
1890 sctx
->bindless_descriptors_dirty
= true;
1892 radeon_add_to_buffer_list_check_mem(
1893 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1894 RADEON_USAGE_READWRITE
,
1895 RADEON_PRIO_SAMPLER_BUFFER
, true);
1901 /* Reallocate a buffer a update all resource bindings where the buffer is
1904 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1905 * idle by discarding its contents. Apps usually tell us when to do this using
1906 * map_buffer flags, for example.
1908 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1910 struct si_context
*sctx
= (struct si_context
*)ctx
;
1911 struct r600_resource
*rbuffer
= r600_resource(buf
);
1912 uint64_t old_va
= rbuffer
->gpu_address
;
1914 /* Reallocate the buffer in the same pipe_resource. */
1915 r600_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1917 si_rebind_buffer(ctx
, buf
, old_va
);
1920 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1921 struct si_bindless_descriptor
*desc
)
1923 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1924 uint64_t va
= desc
->buffer
->gpu_address
+ desc
->offset
;
1925 unsigned num_dwords
= sizeof(desc
->desc_list
) / 4;
1927 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1928 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1929 S_370_WR_CONFIRM(1) |
1930 S_370_ENGINE_SEL(V_370_ME
));
1931 radeon_emit(cs
, va
);
1932 radeon_emit(cs
, va
>> 32);
1933 radeon_emit_array(cs
, desc
->desc_list
, num_dwords
);
1936 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1938 if (!sctx
->bindless_descriptors_dirty
)
1941 /* Wait for graphics/compute to be idle before updating the resident
1942 * descriptors directly in memory, in case the GPU is using them.
1944 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1945 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1946 si_emit_cache_flush(sctx
);
1948 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1949 struct si_texture_handle
*, tex_handle
) {
1950 struct si_bindless_descriptor
*desc
= (*tex_handle
)->desc
;
1955 si_upload_bindless_descriptor(sctx
, desc
);
1956 desc
->dirty
= false;
1959 util_dynarray_foreach(&sctx
->resident_img_handles
,
1960 struct si_image_handle
*, img_handle
) {
1961 struct si_bindless_descriptor
*desc
= (*img_handle
)->desc
;
1966 si_upload_bindless_descriptor(sctx
, desc
);
1967 desc
->dirty
= false;
1970 /* Invalidate L1 because it doesn't know that L2 changed. */
1971 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1972 si_emit_cache_flush(sctx
);
1974 sctx
->bindless_descriptors_dirty
= false;
1977 /* Update mutable image descriptor fields of all resident textures. */
1978 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1980 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1981 struct si_texture_handle
*, tex_handle
) {
1982 struct si_bindless_descriptor
*desc
= (*tex_handle
)->desc
;
1983 struct si_sampler_view
*sview
=
1984 (struct si_sampler_view
*)(*tex_handle
)->view
;
1985 uint32_t desc_list
[16];
1987 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1990 memcpy(desc_list
, desc
->desc_list
, sizeof(desc_list
));
1991 si_set_sampler_view_desc(sctx
, sview
, &(*tex_handle
)->sstate
,
1992 &desc
->desc_list
[0]);
1994 if (memcmp(desc_list
, desc
->desc_list
, sizeof(desc_list
))) {
1996 sctx
->bindless_descriptors_dirty
= true;
2000 util_dynarray_foreach(&sctx
->resident_img_handles
,
2001 struct si_image_handle
*, img_handle
) {
2002 struct si_bindless_descriptor
*desc
= (*img_handle
)->desc
;
2003 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2004 uint32_t desc_list
[16];
2006 if (view
->resource
->target
== PIPE_BUFFER
)
2009 memcpy(desc_list
, desc
->desc_list
, sizeof(desc_list
));
2010 si_set_shader_image_desc(sctx
, view
, true,
2011 &desc
->desc_list
[0]);
2013 if (memcmp(desc_list
, desc
->desc_list
, sizeof(desc_list
))) {
2015 sctx
->bindless_descriptors_dirty
= true;
2019 si_upload_bindless_descriptors(sctx
);
2022 /* Update mutable image descriptor fields of all bound textures. */
2023 void si_update_all_texture_descriptors(struct si_context
*sctx
)
2027 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
2028 struct si_sampler_views
*samplers
= &sctx
->samplers
[shader
].views
;
2029 struct si_images_info
*images
= &sctx
->images
[shader
];
2033 mask
= images
->enabled_mask
;
2035 unsigned i
= u_bit_scan(&mask
);
2036 struct pipe_image_view
*view
= &images
->views
[i
];
2038 if (!view
->resource
||
2039 view
->resource
->target
== PIPE_BUFFER
)
2042 si_set_shader_image(sctx
, shader
, i
, view
, true);
2045 /* Sampler views. */
2046 mask
= samplers
->enabled_mask
;
2048 unsigned i
= u_bit_scan(&mask
);
2049 struct pipe_sampler_view
*view
= samplers
->views
[i
];
2053 view
->texture
->target
== PIPE_BUFFER
)
2056 si_set_sampler_view(sctx
, shader
, i
,
2057 samplers
->views
[i
], true);
2060 si_update_shader_needs_decompress_mask(sctx
, shader
);
2063 si_update_all_resident_texture_descriptors(sctx
);
2066 /* SHADER USER DATA */
2068 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2071 sctx
->shader_pointers_dirty
|=
2072 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2073 SI_NUM_SHADER_DESCS
);
2075 if (shader
== PIPE_SHADER_VERTEX
)
2076 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
2078 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
2081 static void si_shader_userdata_begin_new_cs(struct si_context
*sctx
)
2083 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2084 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
2085 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
2088 /* Set a base register address for user data constants in the given shader.
2089 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2091 static void si_set_user_data_base(struct si_context
*sctx
,
2092 unsigned shader
, uint32_t new_base
)
2094 uint32_t *base
= &sctx
->shader_userdata
.sh_base
[shader
];
2096 if (*base
!= new_base
) {
2100 si_mark_shader_pointers_dirty(sctx
, shader
);
2102 if (shader
== PIPE_SHADER_VERTEX
)
2103 sctx
->last_vs_state
= ~0;
2108 /* This must be called when these shaders are changed from non-NULL to NULL
2111 * - tessellation control shader
2112 * - tessellation evaluation shader
2114 void si_shader_change_notify(struct si_context
*sctx
)
2116 /* VS can be bound as VS, ES, or LS. */
2117 if (sctx
->tes_shader
.cso
) {
2118 if (sctx
->b
.chip_class
>= GFX9
) {
2119 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2120 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2122 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2123 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2125 } else if (sctx
->gs_shader
.cso
) {
2126 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2127 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2129 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2130 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2133 /* TES can be bound as ES, VS, or not bound. */
2134 if (sctx
->tes_shader
.cso
) {
2135 if (sctx
->gs_shader
.cso
)
2136 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2137 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2139 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2140 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2142 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2146 static void si_emit_shader_pointer(struct si_context
*sctx
,
2147 struct si_descriptors
*desc
,
2150 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2154 return; /* the pointer is not used by current shaders */
2156 va
= desc
->buffer
->gpu_address
+
2157 desc
->buffer_offset
;
2159 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, 2, 0));
2160 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
2161 radeon_emit(cs
, va
);
2162 radeon_emit(cs
, va
>> 32);
2165 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
2166 struct r600_atom
*atom
)
2169 uint32_t *sh_base
= sctx
->shader_userdata
.sh_base
;
2170 struct si_descriptors
*descs
;
2172 descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
2174 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2175 si_emit_shader_pointer(sctx
, descs
,
2176 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2177 si_emit_shader_pointer(sctx
, descs
,
2178 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2180 if (sctx
->b
.chip_class
>= GFX9
) {
2181 /* GFX9 merged LS-HS and ES-GS.
2182 * Set RW_BUFFERS in the special registers, so that
2183 * it's preloaded into s[0:1] instead of s[8:9].
2185 si_emit_shader_pointer(sctx
, descs
,
2186 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
);
2187 si_emit_shader_pointer(sctx
, descs
,
2188 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
);
2190 si_emit_shader_pointer(sctx
, descs
,
2191 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2192 si_emit_shader_pointer(sctx
, descs
,
2193 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2194 si_emit_shader_pointer(sctx
, descs
,
2195 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2196 si_emit_shader_pointer(sctx
, descs
,
2197 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2201 mask
= sctx
->shader_pointers_dirty
&
2202 u_bit_consecutive(SI_DESCS_FIRST_SHADER
,
2203 SI_DESCS_FIRST_COMPUTE
- SI_DESCS_FIRST_SHADER
);
2206 unsigned i
= u_bit_scan(&mask
);
2207 unsigned shader
= (i
- SI_DESCS_FIRST_SHADER
) / SI_NUM_SHADER_DESCS
;
2208 unsigned base
= sh_base
[shader
];
2211 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2213 sctx
->shader_pointers_dirty
&=
2214 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2216 if (sctx
->vertex_buffer_pointer_dirty
) {
2217 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2218 sh_base
[PIPE_SHADER_VERTEX
]);
2219 sctx
->vertex_buffer_pointer_dirty
= false;
2223 void si_emit_compute_shader_userdata(struct si_context
*sctx
)
2225 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2226 struct si_descriptors
*descs
= sctx
->descriptors
;
2227 unsigned compute_mask
=
2228 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_SHADER_DESCS
);
2229 unsigned mask
= sctx
->shader_pointers_dirty
& compute_mask
;
2232 unsigned i
= u_bit_scan(&mask
);
2234 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2236 sctx
->shader_pointers_dirty
&= ~compute_mask
;
2241 struct si_bindless_descriptor_slab
2243 struct pb_slab base
;
2244 struct r600_resource
*buffer
;
2245 struct si_bindless_descriptor
*entries
;
2248 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
2249 struct pb_slab_entry
*entry
)
2251 /* Do not allow to reclaim any bindless descriptors for now because the
2252 * GPU might be using them. This should be improved later on.
2257 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
2258 unsigned entry_size
,
2259 unsigned group_index
)
2261 struct si_context
*sctx
= priv
;
2262 struct si_screen
*sscreen
= sctx
->screen
;
2263 struct si_bindless_descriptor_slab
*slab
;
2265 slab
= CALLOC_STRUCT(si_bindless_descriptor_slab
);
2269 /* Create a buffer in VRAM for 1024 bindless descriptors. */
2270 slab
->buffer
= (struct r600_resource
*)
2271 pipe_buffer_create(&sscreen
->b
.b
, 0,
2272 PIPE_USAGE_DEFAULT
, 64 * 1024);
2276 slab
->base
.num_entries
= slab
->buffer
->bo_size
/ entry_size
;
2277 slab
->base
.num_free
= slab
->base
.num_entries
;
2278 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
2282 LIST_INITHEAD(&slab
->base
.free
);
2284 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
2285 struct si_bindless_descriptor
*desc
= &slab
->entries
[i
];
2287 desc
->entry
.slab
= &slab
->base
;
2288 desc
->entry
.group_index
= group_index
;
2289 desc
->buffer
= slab
->buffer
;
2290 desc
->offset
= i
* entry_size
;
2292 LIST_ADDTAIL(&desc
->entry
.head
, &slab
->base
.free
);
2295 /* Add the descriptor to the per-context list. */
2296 util_dynarray_append(&sctx
->bindless_descriptors
,
2297 struct r600_resource
*, slab
->buffer
);
2302 r600_resource_reference(&slab
->buffer
, NULL
);
2308 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
)
2310 struct si_context
*sctx
= priv
;
2311 struct si_bindless_descriptor_slab
*slab
=
2312 (struct si_bindless_descriptor_slab
*)pslab
;
2314 /* Remove the descriptor from the per-context list. */
2315 util_dynarray_delete_unordered(&sctx
->bindless_descriptors
,
2316 struct r600_resource
*, slab
->buffer
);
2318 r600_resource_reference(&slab
->buffer
, NULL
);
2319 FREE(slab
->entries
);
2323 static struct si_bindless_descriptor
*
2324 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2327 struct si_screen
*sscreen
= sctx
->screen
;
2328 struct si_bindless_descriptor
*desc
;
2329 struct pb_slab_entry
*entry
;
2332 /* Sub-allocate the bindless descriptor from a slab to avoid dealing
2333 * with a ton of buffers and for reducing the winsys overhead.
2335 entry
= pb_slab_alloc(&sctx
->bindless_descriptor_slabs
, 64, 0);
2340 desc
= container_of(entry
, desc
, entry
);
2342 /* Upload the descriptor directly in VRAM. Because the slabs are
2343 * currently never reclaimed, we don't need to synchronize the
2346 ptr
= sscreen
->b
.ws
->buffer_map(desc
->buffer
->buf
, NULL
,
2347 PIPE_TRANSFER_WRITE
|
2348 PIPE_TRANSFER_UNSYNCHRONIZED
);
2349 util_memcpy_cpu_to_le32(ptr
+ desc
->offset
, desc_list
, size
);
2351 /* Keep track of the initial descriptor especially for buffers
2352 * invalidation because we might need to know the previous address.
2354 memcpy(desc
->desc_list
, desc_list
, sizeof(desc
->desc_list
));
2359 static void si_invalidate_bindless_buf_desc(struct si_context
*sctx
,
2360 struct si_bindless_descriptor
*desc
,
2361 struct pipe_resource
*resource
,
2364 struct r600_resource
*buf
= r600_resource(resource
);
2365 uint32_t *desc_list
= desc
->desc_list
+ 4;
2366 uint64_t old_desc_va
;
2368 assert(resource
->target
== PIPE_BUFFER
);
2370 /* Retrieve the old buffer addr from the descriptor. */
2371 old_desc_va
= desc_list
[0];
2372 old_desc_va
|= ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc_list
[1]) << 32);
2374 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2375 /* The buffer has been invalidated when the handle wasn't
2376 * resident, update the descriptor and the dirty flag.
2378 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2381 sctx
->bindless_descriptors_dirty
= true;
2385 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2386 struct pipe_sampler_view
*view
,
2387 const struct pipe_sampler_state
*state
)
2389 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2390 struct si_context
*sctx
= (struct si_context
*)ctx
;
2391 struct si_texture_handle
*tex_handle
;
2392 struct si_sampler_state
*sstate
;
2393 uint32_t desc_list
[16];
2396 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2400 memset(desc_list
, 0, sizeof(desc_list
));
2401 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2403 sstate
= ctx
->create_sampler_state(ctx
, state
);
2409 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2410 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2411 ctx
->delete_sampler_state(ctx
, sstate
);
2413 tex_handle
->desc
= si_create_bindless_descriptor(sctx
, desc_list
,
2415 if (!tex_handle
->desc
) {
2420 handle
= tex_handle
->desc
->buffer
->gpu_address
+
2421 tex_handle
->desc
->offset
;
2423 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)handle
,
2425 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2426 &tex_handle
->desc
->entry
);
2431 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2433 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2438 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2440 struct si_context
*sctx
= (struct si_context
*)ctx
;
2441 struct si_texture_handle
*tex_handle
;
2442 struct hash_entry
*entry
;
2444 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2448 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2450 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2451 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2452 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2453 &tex_handle
->desc
->entry
);
2457 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2458 uint64_t handle
, bool resident
)
2460 struct si_context
*sctx
= (struct si_context
*)ctx
;
2461 struct si_texture_handle
*tex_handle
;
2462 struct si_sampler_view
*sview
;
2463 struct hash_entry
*entry
;
2465 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2469 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2470 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2473 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2474 struct r600_texture
*rtex
=
2475 (struct r600_texture
*)sview
->base
.texture
;
2477 if (depth_needs_decompression(rtex
)) {
2478 util_dynarray_append(
2479 &sctx
->resident_tex_needs_depth_decompress
,
2480 struct si_texture_handle
*,
2484 if (color_needs_decompression(rtex
)) {
2485 util_dynarray_append(
2486 &sctx
->resident_tex_needs_color_decompress
,
2487 struct si_texture_handle
*,
2491 if (rtex
->dcc_offset
&&
2492 p_atomic_read(&rtex
->framebuffers_bound
))
2493 sctx
->need_check_render_feedback
= true;
2495 si_invalidate_bindless_buf_desc(sctx
, tex_handle
->desc
,
2496 sview
->base
.texture
,
2497 sview
->base
.u
.buf
.offset
);
2500 /* Add the texture handle to the per-context list. */
2501 util_dynarray_append(&sctx
->resident_tex_handles
,
2502 struct si_texture_handle
*, tex_handle
);
2504 /* Add the buffers to the current CS in case si_begin_new_cs()
2505 * is not going to be called.
2507 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2508 tex_handle
->desc
->buffer
,
2509 RADEON_USAGE_READWRITE
,
2510 RADEON_PRIO_DESCRIPTORS
);
2512 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2514 sview
->is_stencil_sampler
, false);
2516 /* Remove the texture handle from the per-context list. */
2517 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2518 struct si_texture_handle
*,
2521 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2522 util_dynarray_delete_unordered(
2523 &sctx
->resident_tex_needs_depth_decompress
,
2524 struct si_texture_handle
*, tex_handle
);
2526 util_dynarray_delete_unordered(
2527 &sctx
->resident_tex_needs_color_decompress
,
2528 struct si_texture_handle
*, tex_handle
);
2533 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2534 const struct pipe_image_view
*view
)
2536 struct si_context
*sctx
= (struct si_context
*)ctx
;
2537 struct si_image_handle
*img_handle
;
2538 uint32_t desc_list
[16];
2541 if (!view
|| !view
->resource
)
2544 img_handle
= CALLOC_STRUCT(si_image_handle
);
2548 memset(desc_list
, 0, sizeof(desc_list
));
2549 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2551 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2553 img_handle
->desc
= si_create_bindless_descriptor(sctx
, desc_list
,
2555 if (!img_handle
->desc
) {
2560 handle
= img_handle
->desc
->buffer
->gpu_address
+
2561 img_handle
->desc
->offset
;
2563 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)handle
,
2565 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2566 &img_handle
->desc
->entry
);
2571 util_copy_image_view(&img_handle
->view
, view
);
2573 r600_resource(view
->resource
)->image_handle_allocated
= true;
2578 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2580 struct si_context
*sctx
= (struct si_context
*)ctx
;
2581 struct si_image_handle
*img_handle
;
2582 struct hash_entry
*entry
;
2584 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2588 img_handle
= (struct si_image_handle
*)entry
->data
;
2590 util_copy_image_view(&img_handle
->view
, NULL
);
2591 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2592 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2593 &img_handle
->desc
->entry
);
2597 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2598 uint64_t handle
, unsigned access
,
2601 struct si_context
*sctx
= (struct si_context
*)ctx
;
2602 struct si_image_handle
*img_handle
;
2603 struct pipe_image_view
*view
;
2604 struct r600_resource
*res
;
2605 struct hash_entry
*entry
;
2607 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2611 img_handle
= (struct si_image_handle
*)entry
->data
;
2612 view
= &img_handle
->view
;
2613 res
= (struct r600_resource
*)view
->resource
;
2616 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2617 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2618 unsigned level
= view
->u
.tex
.level
;
2620 if (color_needs_decompression(rtex
)) {
2621 util_dynarray_append(
2622 &sctx
->resident_img_needs_color_decompress
,
2623 struct si_image_handle
*,
2627 if (vi_dcc_enabled(rtex
, level
) &&
2628 p_atomic_read(&rtex
->framebuffers_bound
))
2629 sctx
->need_check_render_feedback
= true;
2631 si_invalidate_bindless_buf_desc(sctx
, img_handle
->desc
,
2633 view
->u
.buf
.offset
);
2636 /* Add the image handle to the per-context list. */
2637 util_dynarray_append(&sctx
->resident_img_handles
,
2638 struct si_image_handle
*, img_handle
);
2640 /* Add the buffers to the current CS in case si_begin_new_cs()
2641 * is not going to be called.
2643 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2644 img_handle
->desc
->buffer
,
2645 RADEON_USAGE_READWRITE
,
2646 RADEON_PRIO_DESCRIPTORS
);
2648 si_sampler_view_add_buffer(sctx
, view
->resource
,
2649 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2650 RADEON_USAGE_READWRITE
:
2651 RADEON_USAGE_READ
, false, false);
2653 /* Remove the image handle from the per-context list. */
2654 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2655 struct si_image_handle
*,
2658 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2659 util_dynarray_delete_unordered(
2660 &sctx
->resident_img_needs_color_decompress
,
2661 struct si_image_handle
*,
2668 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2670 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2672 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2673 sizeof(struct si_texture_handle
*);
2674 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2675 sizeof(struct si_image_handle
*);
2677 /* Skip adding the bindless descriptors when no handles are resident.
2679 if (!num_resident_tex_handles
&& !num_resident_img_handles
)
2682 /* Add all bindless descriptors. */
2683 util_dynarray_foreach(&sctx
->bindless_descriptors
,
2684 struct r600_resource
*, desc
) {
2686 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *desc
,
2687 RADEON_USAGE_READWRITE
,
2688 RADEON_PRIO_DESCRIPTORS
);
2691 /* Add all resident texture handles. */
2692 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2693 struct si_texture_handle
*, tex_handle
) {
2694 struct si_sampler_view
*sview
=
2695 (struct si_sampler_view
*)(*tex_handle
)->view
;
2697 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2699 sview
->is_stencil_sampler
, false);
2702 /* Add all resident image handles. */
2703 util_dynarray_foreach(&sctx
->resident_img_handles
,
2704 struct si_image_handle
*, img_handle
) {
2705 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2707 si_sampler_view_add_buffer(sctx
, view
->resource
,
2708 RADEON_USAGE_READWRITE
,
2712 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2713 num_resident_img_handles
;
2716 /* INIT/DEINIT/UPLOAD */
2718 /* GFX9 has only 4KB of CE, while previous chips had 32KB. In order
2719 * to make CE RAM as useful as possible, this defines limits
2720 * for the number slots that can be in CE RAM on GFX9. If a shader
2721 * is using more, descriptors will be uploaded to memory directly and
2724 * These numbers are based on shader-db.
2726 static unsigned gfx9_max_ce_samplers
[SI_NUM_SHADERS
] = {
2727 [PIPE_SHADER_VERTEX
] = 0,
2728 [PIPE_SHADER_TESS_CTRL
] = 0,
2729 [PIPE_SHADER_TESS_EVAL
] = 1,
2730 [PIPE_SHADER_GEOMETRY
] = 0,
2731 [PIPE_SHADER_FRAGMENT
] = 24,
2732 [PIPE_SHADER_COMPUTE
] = 16,
2734 static unsigned gfx9_max_ce_images
[SI_NUM_SHADERS
] = {
2735 /* these must be even due to slot alignment */
2736 [PIPE_SHADER_VERTEX
] = 0,
2737 [PIPE_SHADER_TESS_CTRL
] = 0,
2738 [PIPE_SHADER_TESS_EVAL
] = 0,
2739 [PIPE_SHADER_GEOMETRY
] = 0,
2740 [PIPE_SHADER_FRAGMENT
] = 2,
2741 [PIPE_SHADER_COMPUTE
] = 8,
2743 static unsigned gfx9_max_ce_const_buffers
[SI_NUM_SHADERS
] = {
2744 [PIPE_SHADER_VERTEX
] = 9,
2745 [PIPE_SHADER_TESS_CTRL
] = 3,
2746 [PIPE_SHADER_TESS_EVAL
] = 5,
2747 [PIPE_SHADER_GEOMETRY
] = 0,
2748 [PIPE_SHADER_FRAGMENT
] = 8,
2749 [PIPE_SHADER_COMPUTE
] = 6,
2751 static unsigned gfx9_max_ce_shader_buffers
[SI_NUM_SHADERS
] = {
2752 [PIPE_SHADER_VERTEX
] = 0,
2753 [PIPE_SHADER_TESS_CTRL
] = 0,
2754 [PIPE_SHADER_TESS_EVAL
] = 0,
2755 [PIPE_SHADER_GEOMETRY
] = 0,
2756 [PIPE_SHADER_FRAGMENT
] = 12,
2757 [PIPE_SHADER_COMPUTE
] = 13,
2760 void si_init_all_descriptors(struct si_context
*sctx
)
2763 unsigned ce_offset
= 0;
2765 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2766 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2768 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2769 bool gfx9_tcs
= false;
2770 bool gfx9_gs
= false;
2771 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2772 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2774 unsigned first_sampler_ce_slot
= 0;
2775 unsigned num_sampler_ce_slots
= num_sampler_slots
;
2777 unsigned first_buffer_ce_slot
= 0;
2778 unsigned num_buffer_ce_slots
= num_buffer_slots
;
2780 /* Adjust CE slot ranges based on GFX9 CE RAM limits. */
2781 if (sctx
->b
.chip_class
>= GFX9
) {
2782 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2783 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2785 first_sampler_ce_slot
=
2786 si_get_image_slot(gfx9_max_ce_images
[i
] - 1) / 2;
2787 num_sampler_ce_slots
= gfx9_max_ce_images
[i
] / 2 +
2788 gfx9_max_ce_samplers
[i
];
2790 first_buffer_ce_slot
=
2791 si_get_shaderbuf_slot(gfx9_max_ce_shader_buffers
[i
] - 1);
2792 num_buffer_ce_slots
= gfx9_max_ce_shader_buffers
[i
] +
2793 gfx9_max_ce_const_buffers
[i
];
2796 si_init_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[i
],
2797 si_const_and_shader_buffer_descriptors(sctx
, i
),
2799 first_buffer_ce_slot
, num_buffer_ce_slots
,
2800 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2801 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2802 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2803 RADEON_USAGE_READWRITE
,
2805 RADEON_PRIO_SHADER_RW_BUFFER
,
2806 RADEON_PRIO_CONST_BUFFER
,
2809 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, i
);
2810 si_init_descriptors(sctx
, desc
,
2811 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2812 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2813 SI_SGPR_SAMPLERS_AND_IMAGES
,
2814 16, num_sampler_slots
,
2815 first_sampler_ce_slot
, num_sampler_ce_slots
,
2819 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2820 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2821 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2822 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2825 si_init_buffer_resources(sctx
, &sctx
->rw_buffers
,
2826 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2827 SI_NUM_RW_BUFFERS
, 0, SI_NUM_RW_BUFFERS
,
2829 /* The second set of usage/priority is used by
2830 * const buffers in RW buffer slots. */
2831 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2832 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
,
2834 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2836 si_init_descriptors(sctx
, &sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2837 4, SI_NUM_VERTEX_BUFFERS
, 0, 0, NULL
);
2838 FREE(sctx
->vertex_buffers
.list
); /* not used */
2839 sctx
->vertex_buffers
.list
= NULL
;
2841 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2842 sctx
->total_ce_ram_allocated
= ce_offset
;
2844 if (sctx
->b
.chip_class
>= GFX9
)
2845 assert(ce_offset
<= 4096);
2847 assert(ce_offset
<= 32768);
2849 /* Set pipe_context functions. */
2850 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2851 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2852 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2853 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2854 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2855 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2856 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
2857 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2858 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2859 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2860 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2861 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2862 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2863 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2864 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2866 /* Shader user data. */
2867 si_init_atom(sctx
, &sctx
->shader_userdata
.atom
, &sctx
->atoms
.s
.shader_userdata
,
2868 si_emit_graphics_shader_userdata
);
2870 /* Set default and immutable mappings. */
2871 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2873 if (sctx
->b
.chip_class
>= GFX9
) {
2874 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2875 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2876 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2877 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2879 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2880 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2881 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2882 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2884 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2887 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2889 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2890 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2892 /* Assume nothing will go wrong: */
2893 sctx
->shader_pointers_dirty
|= dirty
;
2896 unsigned i
= u_bit_scan(&dirty
);
2898 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
],
2899 &sctx
->shader_userdata
.atom
))
2903 sctx
->descriptors_dirty
&= ~mask
;
2905 si_upload_bindless_descriptors(sctx
);
2910 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2912 /* Does not update rw_buffers as that is not needed for compute shaders
2913 * and the input buffer is using the same SGPR's anyway.
2915 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2916 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2917 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2919 /* Assume nothing will go wrong: */
2920 sctx
->shader_pointers_dirty
|= dirty
;
2923 unsigned i
= u_bit_scan(&dirty
);
2925 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
], NULL
))
2929 sctx
->descriptors_dirty
&= ~mask
;
2931 si_upload_bindless_descriptors(sctx
);
2936 void si_release_all_descriptors(struct si_context
*sctx
)
2940 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2941 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2942 si_const_and_shader_buffer_descriptors(sctx
, i
));
2943 si_release_sampler_views(&sctx
->samplers
[i
].views
);
2944 si_release_image_views(&sctx
->images
[i
]);
2946 si_release_buffer_resources(&sctx
->rw_buffers
,
2947 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2948 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2949 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2951 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2952 si_release_descriptors(&sctx
->descriptors
[i
]);
2954 sctx
->vertex_buffers
.list
= NULL
; /* points into a mapped buffer */
2955 si_release_descriptors(&sctx
->vertex_buffers
);
2958 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2962 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2963 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2964 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
].views
);
2965 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2967 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2968 si_vertex_buffers_begin_new_cs(sctx
);
2970 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2971 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2973 si_shader_userdata_begin_new_cs(sctx
);
2976 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2977 uint64_t new_active_mask
)
2979 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2981 /* Ignore no-op updates and updates that disable all slots. */
2982 if (!new_active_mask
||
2983 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2984 desc
->num_active_slots
))
2988 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2989 assert(new_active_mask
== 0);
2991 /* Upload/dump descriptors if slots are being enabled. */
2992 if (first
< desc
->first_active_slot
||
2993 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2994 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2996 /* Enable or disable CE for this descriptor array. */
2997 bool used_ce
= desc
->uses_ce
;
2998 desc
->uses_ce
= desc
->first_ce_slot
<= first
&&
2999 desc
->first_ce_slot
+ desc
->num_ce_slots
>= first
+ count
;
3001 if (desc
->uses_ce
!= used_ce
) {
3002 /* Upload or dump descriptors if we're disabling or enabling CE,
3004 sctx
->descriptors_dirty
|= 1u << desc_idx
;
3006 /* If we're enabling CE, re-upload all descriptors to CE RAM.
3007 * When CE was disabled, uploads to CE RAM stopped.
3009 if (desc
->uses_ce
) {
3011 u_bit_consecutive64(desc
->first_ce_slot
,
3012 desc
->num_ce_slots
);
3016 desc
->first_active_slot
= first
;
3017 desc
->num_active_slots
= count
;
3020 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
3021 struct si_shader_selector
*sel
)
3026 si_set_active_descriptors(sctx
,
3027 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
3028 sel
->active_const_and_shader_buffers
);
3029 si_set_active_descriptors(sctx
,
3030 si_sampler_and_image_descriptors_idx(sel
->type
),
3031 sel
->active_samplers_and_images
);